8.1 DIGITAL APPLICATIONS OF CCCII±

Transcription

1 CHAPTER 8 CCCII DIGITAL APPLICATIONS Application of CCCII in digital building blocks like comparator, CMOS clock generator and polar OR/NOR. 1T model of CCCII is presented and used in the realization of polar OR. 156

2 A CCCII is basically an ANALOG device and is usually designed with the aim of realizing Analog applications. However, it is observed that the voltage current characteristics of a CCCII resemble the characteristics of a polar OR. Apart from this natural exhibit, a CCCII shows potential to realize other digital functions. A few of such applications are presented here in this chapter. The DIGITAL APPLICATIONS include the realization of a polar CCCII; along with it s comparison with the standard CMOS OR. A realization is also presented for a CCCII- using a single N-MOS and is applied to realize a very high frequency Polar OR; The other Translinear CCCII based applications include a COMPARATOR and its extension to a high frequency CMOS CLOCK Generator. 8.1 DIGITAL APPLICATIONS OF CCCII± Here some important Digital Applications are discussed which have evolved during the design and study of the CCCII. The importance and novelty here is that the CCCII has never so far been appeared in literature from the angle of view with the digital applications. This appears due to the fact that the CCCII contains a large number of transistors than the transistors required by the basic gates. For example two-input NAND, NOR, OR and NOR all need only four MOSFETs in standard CMOS. Thirteen or nineteen transistors in a CCCII± is really a big figure to imagine in presence of standard CMOS gates. However, if the number of transistors used is not considered as a problem, then one can easily observe that the CCCII posses a few notable features [109]. (a) It is a current mode device, and qualifies the recent VLSI design criterion of low power, high bandwidth and high speed. 157

3 (b) Its architecture is found flexible, and the size of the transistors used need not always be as large as required in most analog applications. (c) The CCCII has improved output current drive, and can be utilized to improve frequency, bandwidth and speed. (d) CCCII offers the possibility of dropping down the functional power as it can drive it s required current even at ground potential, thereby reducing V-I product. (e) A CCCII± also offers to duplicate any number of copies of the realized function or it s complement with a feature that each output is independent. Power in the beginning is though considerable, but additional function outputs do not increase power considerably. (f) Designers are now trying to implement the current conveyors in field programmable applications. In such a scenario, it is perhaps easier to use CCCII based solutions than going to locate different other solutions [86]. These are some of the important features that might be of interest in enhancing the latest design view. From this view point, the analog CCCII± is also studied here for digital applications and a few applications are developed. Some of these applications were first considered in an M. Tech. thesis [25] under the authors guidance. This thesis was presented in the Masters Thesis Contest 2011, organized by the IEEE IAS (Industry Applications Society) and won the 3 rd Best M. Tech Thesis of 2011 award. It was also accepted for presentation in the 46 th Annual Meet 2011 and Workshop, October 11, 2011 at Orlando, Florida, USA. 158

4 This achievement paved the way and created a zeal for further studies on this topic. 8.2 BASIS OF THE DIGITAL APPLICATIONS If voltage pulses are applied to the input nodes and of the CCCII+, it is observed that output current I Z will exhibit characteristics similar to those of an OR gate. V Z+ I Z V CCCII+ V Z V V V Z V :V (a) (b) FIGURE 8.1: (a)- Basic CCCII+ building block. (b)- pattern of output voltage (V Z ) or current (I Z ) variation for inputs V and V. This can be verified by performing simple analysis of the circuit. Let 0 and 1 represent logic levels HIGH and LOW correspondingly, where HIGH stands for a voltage V>0 to drive the CCCII, and LOW for V=0, then the current I Z behaves as the following [19,20,65] V = V, = 0, V V R I Z = (8.1) or 11 2 V V = 0 = or V = V V, I = 0 (8.2) = Z V = 0 159

5 V = V, I Z V = (8.3) R In Eq above, 10 2 etc represent binary combinations. The suffix 2 is for binary systems. Before going into the details of analysis and results of this special functioning of the CCCII, it seems appropriate to describe the Binary and Polar OR functions BINAR OR Conventional OR functioning is confined between two logic levels ( 0, 1 ) only. It s symbol and truth table are presented here for a ready reference. TABLE 8.1: Unipolar OR characteristic,fig.8.2 V V V Z V V V Z FIGURE 8.2: Binary OR gate symbol POLAR OR The type of OR gate which exhibits different output polarities for two different sets of inputs is called a polar or bi-polar OR [87 88]. Here the term bipolar stands for the polarity of the output and not for the popular bipolar junction transistor technology. 160

6 TABLE 8.2: Polar OR characteristic, Fig.8.3 V V V Z V V ± V Z FIGURE 8.3: Polar OR symbol ± m FIGURE 8.4: Characteristic of circuit in Fig.8.1. TABLE 8.3: Performance details of the OR of Fig.3(a) Design Details Values Delay 30ps Average Power 64µW Biasing ±1V Peak Current ±13µA Offset Current 50.0nA (00 2 ) 3µA (11 2 ) NMOS PMOS R Z 0.1µm/0.1µm 0.3µm/0.1µm 50K (optional) 161

7 The truth table of the polar OR contains 0 outputs for equal inputs at nodes and (V = V ), but attains outputs of different polarities for unequal inputs. The circuit in Fig.8.1 is simulated using 45nm Technology on HSPICE base. Results and performance of this simulation are as follows OR GATE IN STANDARD CMOS Although the conventional CMOS is in totality different from the OR realized by using CCCII, it appears to be worthwhile to have a relative performance appraisal of the two methodologies because of the functional resemblance of the two systems. 1. Standard CMOS uses fewer transistors (04 NMOS, 0.2µm/0.1µm; 04 PMOS, 0.6µm/0.1µm; Active Area=2.4µm*0.1µm) than the transistors used in realization of CCCII (07 NMOS, 0.1µm/0.1µm; 04 PMOS, 0.3µm/0.1µm; Active Area= 2.5µm* 0.1µm). It is interesting to note that the Active Areas in the two cases is same. V B V A V A V B Vo V A V B V B V A SIZES: W/L NMOS : 180nm/90nm PMOS : 360nm/90nm This size is considered with a rapport to the INVERTER of aspect 180nm/90nm FIGURE 8.5: (a)- Standard CMOS OR Gate; (b)- output of the OR gate of part (a) The CMOS OR is designed with respect to the standard CMOS inverter. The standard inverter is one whose charging and discharging resistances are maintained same. It is a common practice to design the logic circuits with the 162

8 criterion of maintaining the charging and discharging resistances of the gate same. It is because if all the inputs of the logic gate are tied together, the gate can always be expressed as an inverter. In deep sub micron technologies, the NMOS and PMOS resistances are approximately in the ratio of 1 to 2. (a) (b) (c) 163

9 (d) FIGURE 8.6: Characteristics of the standard CMOS OR (a)- OR output; (b)- Voltage inputs; (c)- NMOS drain currents; (d)- PMOS drain currents. 2. If only the active areas are considered, the parasitic capacitances are expected to be comparative for the systems. It can be easily observed that for the case of intrinsic delays, the delay exhibited by the standard CMOS OR (85ps) is quite inferior to the delay exhibited by the CCCII OR realization (30ps). This difference is perhaps due to the superior driving load capability of the CCCII. 3. The Standard CMOS OR can attain only two logic levels. However, it is felt that the two level logic fails to simplify the circuit architectures. In such a case, multilevel logic realization is a needed solution, promising the system simplification and reducing lt s overall power requirements [87,88]. 4. Standard CMOS realization is also sensitive to the pattern of logic inputs applied to the circuit. CCCII realization is normally insensitive to logic input application, whether V A is applied first or V B. 5. Power considerations are important. The average power shown by the standard CMOS OR is 8µW, whereas the power requirement shown by the CCCII based OR is 64µW, a figure 8 times higher. But here a few considerations are important to make. 164

10 (i) The CCCII based OR is polar, whereas in standard CMOS, it seems impossible to realize polar logic, (ii) CCCII based OR is faster and has improved load driving capabilities. (iii) CCCII is a current mode device, and is not bound with voltage or current magnitudes. CCCII based OR is current mode solution whereas standard CMOS is voltage mode methodology and therefore has a voltage sensitive swing. (iv) The CCCII based OR can operate on voltage signals as well as on current signals alike. This flexibility is not available with CMOS. Simplest possible solution is to use diode connected MOSFET, but it has nonlinear characteristics. Linear converters could be a solution. Anyway the use of digital CMOS will complicate the system and distort the power scenario seriously. In current mode environment, it seems feasible to use CCCII based solution. (v) It is totally a new concept. Refinements at the circuit level are highly possible. TABLE 8.4: Performance details of the standard CMOS OR of Fig.8.5 Design Details Delay Values 85ps Average Power 10µW Biasing Peak Current NMOS PMOS 1V ±50µA 180nm/90nm 360nm/90nm 165

11 This development shows the potential that a CCCII can cope with the requirements of the digital environments. This concept is extended further to realize a differential CM OR. 8.3 CCCII BASED OR REALIZATION SCHEMES A general scheme for OR/NOR realization on differential output current basis is proposed in Fig.8.7. Two identical CCCII± of I and are used. An OR circuit working with V and V signals can be developed by using the driving A B circuit of Fig.8.7(a) along with the sensing circuit of Fig.8.7(b,c). Z + I Z Z+ V A CCCII_1 Z- Z 1 - OR Z 1 + Z 1 - NOR Z 1 + Z+ CCCII_2 Z 2 + Z 2 - Z 2 - Z 2 + V B Z- FIGURE 8.7: OR/NOR Realization topologies; (a) the logic driving circuit; (b) and (c) are sensing circuits for the OR/NOR functions respectively. Z+ V A CCCII_1 Z- I OR Z+ V B CCCII_2 Z- FIGURE 8.8: OR realization topology for the voltage inputs 166

12 OR realization on the basis of the scheme outlined in Fig.8.7 is represented in Fig.8.8. Analysis of this circuit is simple and is as follows. Both inputs are grounded. Therefore currents at inputs will be generated at zero potential, giving rise to a reduction in power. V A = V B = 0 ; I I = 0 (8.4) Z + = Z V = V = V ; A B 1 V I (8.5) A Z1+ = = I = I Z1 R V I (8.6) B Z 2+ = = I = I Z 2 R By KCL at any node of the load resistor R, I = 0 (8.7) V A = 1V ; = 0 Z V B V I (8.8) A Z1+ = = I = I Z1 R I Z = I (8.9) Z+ Z+ V A CCCII_1 Z- I Z V A CCCII_1 Z- I Z Z+ Z+ V B CCCII_2 Z- V B CCCII_2 Z- FIGURE 8.9: Output currents for inputs V A = V B = 1V FIGURE 8.10: Output currents for inputs V A = 1, V B = 0V 167

13 The CCCII is biased at ±1V. For OR is presented below. V A = 1V, V = 0, I Z = 2I. Performance of the B FIGURE 8.11: Simulation results of the OR in Fig.8.8 Table 8.4 represents the truth table of the polar OR gate and the Table 8.5 gives the functional details of the polar OR realization. TABLE 8.5: Functional Details of OR Realization of Fig.8.7. Here, LOGIC 1 = V DD = 1; LOGIC 0 = V; I=V DD /R A B I Z I 1 0 2I TABLE 8.6: Performance details of the proposed OR of Fig.8.7 Parameter Value Delay Average Power (62µW per CCCII) 50ps 124µW Biasing ±1V Peak Current Offset Current N/PMOS : Technology ±8µA 0.01µA 0.1µm/0.1µm 45nm CMOS 168

14 Similar OR/NOR circuits can be realized for current input signals. Again, the logic symbols are defined as earlier, the logic 1 = I, the Logic 0 = -I, I being the reference current. Circuit details and it s performance are given below in Fig.8.12 TABLE 8.7: Functional details of current input OR Circuit of Fig.8.11 I A I B I Z I I 0 I I -2I I I 2I I I 0 FIGURE 8.12: Current input OR realization The Polar truth table and other design details of the OR circuit of Fig.8.12 are given below in Table 8.6 and Table 8.7. FIGURE 8.13: Output current characteristics of the OR of Fig

15 TABLE 8.8: Performance details of the proposed OR of Fig.8.11 Design Details Values Delay Average Power (74µW per CCCII) Peak 43ps 148µW Biasing ±1V I Current Z ±13µA Offset Current 0.1nA (00 2 ) 6nA (11 2 ) N/PMOS : Technology 0.1µm/0.1µm 45nm CMOS 8.4 SINGLE TRANSISTOR BASED CCCII- MODEL In the above instances of OR/NOR realizations, it is observed that the use of the regular CCCII± is highly inefficient as far as average power is concerned. From the functional details of the realized circuits, it is evident that one unit of CCCII± consumes huge average power. For example, power details of the various CCCII based circuits show the following results. TABLE 8.7: 74µW/CCC, TABLE 8.5: 62µW/CCC, TABLE 8.3: 65µW/CCC. The conventional CMOS circuit methodology based OR realized in 45nm technology node, shows an average power consumption of about 10µW, a figure which is quite low compared to the power utilization of the CCCII based OR versions. Though the use of a CCC in digital applications is innovative in itself, and posses some striking features, but they pose a bad power scenario that renders them practically unsuitable for VLSI applications. 170

16 A promising solution that can eliminate some of the above problems is the single NMOS based model of the CCCII. Details of this model are shown in Fig A close study of the transistor characteristics suggests that the transistor itself can be used as a CC or more generally, a CCC, only the difference is that this model directly realizes CCCII-. This model can be described as follows. I 1 Z V I Z+ I Z M V I =0 CCCII- I 2 FIGURE 8.14: One transistor model of the CCCII; (a)- Circuit Details; (b)- block diagram If the reference currents are equal, I 2 = I 1, and the transistors operation can be assumed linear, then, I Z = I. and I V V = = gm( V V ) (8.10) R If the operation of the transistor is assumed linear, V G changed to ( V ± ) will G V G cause a similar change in the channel current, and hence the currents at the nodes and Z will be respectively ( I ± ) and ( I m ). (V V ) is the general gate I Z I Z drive, that is necessarily required for creating the channel. Again if the reference currents are reasonable and are based on simple transistors, then the impedances at the nodes and Z can be given by Z Z 1 1 ro ro 2 g (8.11) g m O ro1 m Z r (8.12) 171

17 where g m is the transconductance of the MOSFET used and is controlled by the biasing currents, is it s channel impedance at the drain and is the output ro r O 1 impedance of the reference current source I1. Therefore node offers a low impedance input node, node Z offers a high impedance node and the node is a high impedance node. The characteristics of this CCC can be summarized by the following set of linear equation. I = (8.13) Z I I = 0 (8.14) I V V = = g ( V V ) (8.15) R m = f ( I1 ); for I2 I (8.16) 1 g m = (a) (b) FIGURE 8.15: (a)- OR realization of using the single transistor model of the CCCII-. (b)- current is sensed by the ammeter V From the set of equations above, it is clear that the single transistor model of the current conveyor is in fact a current controlled current conveyor and can be expressed by the abbreviation CCCII-. After characterization, the CCCII- can be used almost as usual. This building block is now abbreviated as 1T_CCCII- from now onwards. The 1T_CCCII- model is biased through a current source 172

18 specifically designed keeping the target average power of 6µW. It is found difficult to reduce the reference currents to very low values, therefore, in order to keep the currents within reasonable limits, the biasing currents are obtained by single 1V source. The OR circuit is thus tested for both voltage signal input and for current signal input pulses. The results of the two simulations are presented below OR RESPONSE FOR VOLTAGE INPUTS The OR Circuit of Fig.8.15(b) significantly performs for voltage inputs. The response is obtained for 50% duty cycle 4ns period pulses. Fig.8.16 shows the response for voltage input pulses to be ORed. The sensed output current is approximately 1µA. (a) - Polar output current confirming to the polar OR (b) - Voltage signal inputs applied at nodes of the CCCII- FIGURE 8.16: Response for voltage signal input to the 1T-CCCII- OR of Fig.8.15 (a)- represents the output current of the polar OR of Fig.8.15(a); (b)- Voltage signal inputs applied at nodes of the CCCII- 173

19 8.4.2 OR RESPONSE FOR CURRENT INPUTS The OR Circuit performance is observed further improving for current signal inputs. The response is obtained for 50% duty cycle 4ns period 0 1V transition pulses. The second input pulse is shifted in time with respect to the other for the purpose of verification of the truth table of the polar OR. The response is presented in the following figure. DELA = 3ps AVERAGE POWER = 6µW ACTIVE AREA = 0.14µm2 (a) (b) FIGURE 8.17: Performance of the OR of Fig.8.15 for current Inputs Fig.8.17 shows the response for current input to the 1T-CCCII- based OR. The sensed output current is almost 1µA, same as the inputs. Furthermore, the circuit can be observed as a high frequency compatible circuit and is therefore again simulated for 50% duty cycle, 200ps period ±1µA pulses. The response is given in Fig

20 FIGURE 8.18: Response to current input signals of the reduced active area OR of Fig.8.15 The circuit is quite flexible and can satisfactorily operate on similar pulses but with 0 1µA transition. In all these above cases, it is to be pointed out that the delay is remarkably low. Specifically in the current signal input cases, the delay shown is approximately 3ps and 4ps. This performance is quite superior to that obtained by a conventional standard CMOS OR realization, Fig.8.6(a) and (b). TABLE 8.9: Performance details of Various OR realizations Parameter Norma CCCII based OR CMOS OR 1T CCCIIbased OR, V A V B I/P 1T CCCIIbased OR, I A I B I/P (Table 8.6, Fig.8.7) (Table 8.4, Fig.8.5) (Fig 8.15(b)) (Fig 8.15(b)) Delay 50ps 85ps 40ps 4.6ps Average Power (62µW per CCCII) 124µW 10µW 10µW 6µW Biasing ±1V 1V ±1V ±1V Peak Current ±8µA ±50µA ±2µA, smooth ±2µA, smooth Offset Current 0.01µA Spikes 300mV Single, 10µA over 40ps N/PMOS : 0.1µ/0.1µ 180n/90n 360n/90n Technology 45nm CMOS Negligible NMOS(biasing) : 45n/360n PMOS(biasing) : 90n/360n NMOS (CCC) : 90n/90n 175

21 Standard CMOS inverter is a voltage mode device and shows excellent voltage signal compatibility in cascading. This is because of the zero gate current in micron and sub micron technologies. This cascading compatibility starts deteriorating in deep sub micron and nanometer technologies because of the gate leakage ever increasing with the advancing technology. Expectations are that the ordinary CMOS may loose it s sheen because of the gate leakage. However, CCC solutions offer both high impedance input (voltage signals), and a low impedance input (current signal). The cascading can be done through both these nodes as and when required. In the leaky technologies, the effective cascading can be done using the low impedance node thereby reducing or avoiding the impact of leakage on circuit performance. 8.5 CCCII+ BASED COMPARATOR Comparator is a device that compares an input signal with a reference signal and generates output signal ±V O corresponding to the difference input being positive or negative. Usually OPAMP or allied devices have been in use. An OPAMP usually is a simple choice as it is a general purpose IC and is readily available. A comparator can be active or passive. A schmitt trigger is an active comparator as it s reference signal is dynamically set depending upon input [25,109]. Here a simple comparator is presented which comprises of a CCCII+, output being cascaded to a passive inverter presented in Fig.8.19 I V Z+ CCCII+ I Z V Z V O C Z C Z : Parasitic Capacitance (a) Comparator circuit diagram 176

22 (b) - Charging and Discharging characteristics and the Comparator Functioning FIGURE 8.19: Translinear CCCII+ based comparator. (a)- circuit diagram; (b)- charging and discharging characteristics and the comparator functioning Operation of this circuit is based upon charging or discharging of the intrinsic capacitance (C Z ) at the node V Z. As long as the signal V >0, node V Z is urged to supply current to the CCCII+ output node. This keeps the node V Z = 0, practically keeping the current I Z = 0 and hence V O = HIGH. When signal V < 0, current at node V Z changes direction, now tending to charge V Z. For a fixed input V, C Z charges and reduces the current to zero. Output in this case establishes V O = LOW. ±I Z charges up C Z to inverter threshold, V M, before transition from one state to another completes. V M is usually 50% of V DD. Thus the larger the difference signal ( V V ), the faster the capacitor charges or discharges, and hence faster is the transition. Z VM = = = 0. 7 CZ R CZ R CZ I V V V = τ τ τ V (8.17) When a voltage sweep is applied at V, so that it changes to a new value (V + V ). This change is reflected by current I Z as it linearly changes to (I Z + I Z ), where V I Z =. R 177

23 For incremental values, change in I Z is R time smaller, and remains insufficient to cause a substantial change in the charge on C Z, therefore V Z decreases slowly. It is only when the sweep crosses zero, that I Z quickly changes direction and the charge on C Z suddenly starts to build up in the other direction, and hence the inverter switching LOW HIGH takes place. This transfer characteristic is shown in Fig (a) (b) FIGURE 8.20: Transfer characteristics of the CCCII based comparator for voltage signal input. (a)- input = V ; (b)- input = V 178

24 Time instants at which switching of the comparator takes place can be controlled by selecting an appropriate inverter threshold with the help of the PMOS NMOS size ratio. Transient analysis of the comparator of Fig. 8.19(a) is performed by applying a triangular pulse at the node. The input signal is compared with the ground potential. The results are presented in Fig.8.21(a). (a) A similar analysis is performed for signal applied at the node, and the corresponding result is presented in Fig.8.21(b). (b) FIGURE 8.21: Transient analysis. (a)- Input V, (b)- Input V 179

25 8.6 HIGH FREQUENC CMOS CLOCK GENERATOR Clocking is an essential requirement of the VLSI systems so that the whole system is synchronized. Basically the CMOS means VLSI, therefore it is usually necessary that a compatible clocking system is to be used to synchronize the VLSI systems. A CMOS clock ordinarily has 50% ON Time and the 0 V DD amplitude transition, with comparatively vary high rate of rise so that the intended frequency of use is not affected by the clock. Here in this work an application is developed which generates high frequency voltage mode clock with ordinary CCCII± along with two passive CMOS inverters. One more passive inverter may be used for output coupling, as shown in the diagram below. The details of the circuit diagram and design are presented in Fig.8.22 [25]. Z- V 1 INV2 V 3 V 4 INV1 V 2 INV3 FIGURE 8.22: High frequency CCCII based CMOS clock generator Working of this circuit (Fig.8.16) is based upon the signals V 2 and V 3. Ideally the signals V 2 and V 3 vary between 0 1Volt. At nodes V 1, V 2 and V 3 there are parasitic capacitances due to the corresponding enjoined transistors. These capacitors are responsible for the working of the circuit. Charging and discharging of these capacitances by I Z- develops clock signal. This clock signal is shifted in time. Inverter between nodes V 2 and V 3 corrects this signal, though it is essential 180

26 for working of the circuit. Inverter between nodes V 3 and V 4 is used for a clean and buffered clock signal output. TABLE 8.10: Delay calculation details of the circuit of Fig.8.22 NODE NODE V 1 NODE V 2 NODE V 3 Constituent Parasites the NODE at roz = ro 18 ro 19 = 178KΩ CZ = C D18 + C D19 = 521af C = C + C af INV 1 GN GP = 906 ro INV1 = ron rop = 65. 7kΩ 1 r = ( g + g ) = 2. 37kΩ 9 10 C INV 1 = C DN + C DP = 209af C = C + C af C INV 2 GN GP = 311 = C 9 + C 10 = 756 af ro INV 2 = ron rop = 112kΩ C = C + C af C C INV 2 DN DP = 319 INV 3 = C DN + C DP = 187 = CS 5 + CS 6 = 930af af 1 r = ( gm + gm ) = 21kΩ 5 6 Lumped Values rv 1 = roz = 178KΩ CV1 = CZ + C INV 1 = 1427af r V 2 = 65.7k 2.37k = 2. 28kΩ C V 2 = 1275af r V = 112k 21k = 18kΩ 3 CV 3 = CS 5 + CS 6 = 1436af Time Constants τ V 1 = 254 ps τ V 2 = 2. 9 ps τ V 3 = 2. 3ps Working of the circuit of Fig.8.22 is based upon the signals V 2 and V 3. Ideally the signals V 2 and V 3 vary between 0 1Volt. At nodes V 1, V 2 and V 3 there are parasitic capacitances which are responsible for working of this circuit. Charging and discharging of these capacitances by I Z- develops clock signal. This clock signal is shifted in time. Inverter between nodes V 2 and V 3 corrects this signal, though it is essential for working of the circuit. Inverter between nodes V 3 and V 4 is used for a clean and buffered clock signal output. At various nodes charging and discharging of the parasitic capacitors determine the speed with which signal flows. Therefore delay calculation can be used as an analysis model for the determination of the clock frequency. The details required for the analysis of the circuit is as follows. 181

27 (a) - Buffered output of circuit given in Fig.8.22 (b) - enlarged view of Fig 8.23(a) FIGURE 8.23: (a)- Buffered output of circuit of Fig.8.22, (b)- enlarged view of Fig 8.23(a) Using the delay time constants from the above table (Table 8.8), loop delay and frequency of oscillation are [89] as follows. T LOOP = 0.69( ) = 179 ps (8.18) f 1 = = 5.6GHz (8.19) T LOOP 182

28 The resulting frequency of oscillation estimated by the simulator is 4.62GHz, a figure lower than what is calculated above in Eq In this handmade estimate, several capacitances and effects are ignored. However, the results are shown in Fig Features of the Circuit are: Generates a clock frequency of 4.62GHz Clock signal is highly fine Duty Cycle of the clock signal with T ON =91ps and T=216ps is 42% Average Power Requirement is only 116µW Circuit is current mode. Currents I Z+ or I Z- can be repeated any number of times and give so many independent clock signals of same frequency with little additional power per signal. Further, the output currents I Z+ and I Z- give clock signals of independent phases. These phases with duty cycle can be adjusted independently by choosing appropriate inverter thresholds. Therefore the multiphase clock signals can be easily generated. 183

29 CCCII is basically an analog device. It s extension to the digital applications is an innovative idea. In the applications like Comparator and Clock Generator, the main functionality is obtained from the CCCII, the inverter is used to set the required voltage levels since the Digital Logic is Binary. In presence of the well established standard CMOS Logic gates, use of such a technique seems irrelevant. But this can be found justifiable when one considers the drive capability of the CCC. The delay at a node is directly proportional to the drive available at the node to charge or discharge its capacitance. CCC serves this purpose well and therefore can be used as an alternative. Further, the inclusion of CCC in applications like FPA/FPGA etc, and in presence of the trend of mixed signal design, availability of techniques with a device used as a base device is usually found convenient than on swapping from device to device in the design. Furthermore, the data presented in Table 8.9 shows that the features of the Polar OR (in CCC) and conventional OR (standard CMOS) are quite comparable. 1T- Model of CCC (Table 8.9) can be found far superior than the standard CMOS and some other logic realizations. 184