Circuit-Level Considerations for an Ultra- Low Voltage FPGA with Unidirectional, Single-Driver Routing Fabric

Transcription

1 UNCLSSIFIED Circuit-Level Considerations for an Ultra- Low Voltage FPG with Unidirectional, Single-Driver Routing Fabric Peter Grossmann, Miriam Leeser 26 September 2011 The Lincoln Laboratory portion of this work was sponsored by the United States Government under ir Force contract number F C The opinions, interpretations, conclusions and recommendations are those of the authors and are not necessarily endorsed by the United States Government. SUVT UNCLSSIFIED

2 UNCLSSIFIED Subthreshold FPG Motivation Low power systems benefit from FPGs Improved energy efficiency/performance vs. microcontroller Improved design via reconfigurability Lower cost vs. SIC State of the art low power FPGs: 10s to 100s of mw Ultra-low power applications require 10s to 100s of µw Wireless sensor networks RFID Digital hearing aids Ultra-low power budgets motivate extreme voltage scaling Subthreshold supply voltages yield peak energy efficiency SUVT UNCLSSIFIED

3 UNCLSSIFIED FPG rchitecture Overview rray of tiles Configurable Logic locks (CLs) Programmable Routing Channels TILE Tile periphery connects to I/O blocks Logic functions, routing connectivity programmed via SRM. Sharma, Place and Route Techniques for FPG rchitecture dvancement, University of Washington, Island-style FPG SUVT UNCLSSIFIED

4 UNCLSSIFIED FPG Tile rchitecture Used In This Work Cluster-based island style tile 8-LE clusters good cluster count for low-power FPGs Logically equivalent inputs -- improves routing flexibility Directional, single driver routing Connection lock (C) 3 2 Logic lock (L) x4 4 :1 x8 LE x6 16:1 16:1 x6 2 6 Connection lock (C) x x3 16:1 16:1 x3 2 x 3 Switch lock (S) SUVT UNCLSSIFIED

5 UNCLSSIFIED Three Sub-V t FPG Circuit Design Decisions Configuration bit storage Two-input multiplexer design choices Wide-input multiplexer design choices Goal: Minimize Power, Delay, and rea Static power especially critical Sacrificing delay for static power acceptable Sacrificing area for power might be acceptable rea no longer critical for delay reduction Logic capacity requirements for many ultra-low power applications are modest Reducing die size for yield, cost considerations may drive area requirements SUVT UNCLSSIFIED

6 UNCLSSIFIED Configuration it Storage WL V DD ` L Standard 6T SRM it Cell 6T Latch Subthreshold FPG SRM use case: slow writes, no reads Cross-coupled inverters directly drive configuration inputs Pi Primary goals: low area, low static ti power SUVT UNCLSSIFIED

7 UNCLSSIFIED Leaf Cell Implementation Multiplexer Key Considerations Process technology matters IM 0.18µm SOI Input type matters Fast select lines needed for LUT Fast non-select lines needed for routing muxes Static power matters Many mux instances will be unused logic, routing resources rea still matters Each tile will contain the equivalent of ~ input muxes SUVT UNCLSSIFIED

8 UNCLSSIFIED Multiplexer Style Comparison Significant area, delay penalties for improved power in DTMOS Transmission gate multiplexer power not acceptable If area matters, plain old static CMOS appears to be best choice vg. Current nmux2 nmuxs2 nmux_ dtmos2 tnmux2 tnmux_ dtmos2 nmux_ sbc vg. Static Current /-Y Delay S-Y Delay rea SUVT UNCLSSIFIED

9 UNCLSSIFIED Wide Input Multiplexer Power Gating State-based power gating No additional programming g bits required Full State-ased Power Gating log 2 (N) / (N - 1) Flat State-ased Power Gating (N/2) / (N 1) Practical for FPGs wakeup time is irrelevant for routing muxes Possible pproaches Full power gate all muxes not on the selected path; requires additional logic Flat larger loads on sleep transistors t Hierarchical State-ased Power Gating (N/2) / (N - 1) Hierarchical reduces input capacitance on final select bit, lighter loads on sleep transistors SUVT UNCLSSIFIED

10 UNCLSSIFIED Comparison of State-ased Power Gating Implementations 16:1 LF Mux 16:1 LF Mux, Full 16:1 LF Mux, Hierarchical 16:1 LF Mux, Flat vg. Delay (ns) vg. Static Current (n) rea (µm 2 ) Full approach requires too much logic Flat, hierarchical approaches show good efficiency (8/15 = 0.53) Most hierarchical, flat area overhead due to isolation of power rails SUVT UNCLSSIFIED

11 UNCLSSIFIED Conclusion Use of 6T latch eliminates need to design around subthreshold SRM noise margins for configuration bits Multiple area/delay/power tradeoffs available for two- input multiplexers to implement routing fabrics State-based power gating for wide input multiplexers consume (N/2)/(N- 1) times the static power of nonpower gated counterparts Subthreshold FPGs benefit from circuit design that is aware of FPG use cases SUVT UNCLSSIFIED

12 UNCLSSIFIED MIT Lincoln Laboratory Lincoln Scholars Program Group 83 Group 88 LLCD Thank You PhD Committee Miriam Leeser (dvisor) Nicol McGruer (Northeastern) nantha Chandrakasan (MIT) Peter Wyatt (MITLL) SUVT UNCLSSIFIED

13 UNCLSSIFIED enefits of Unidirectional Routing Fabric Simplified circuitry for drivers no tristate buffers required Reduced capacitance on routing wires due to shorter wires and smaller loads Net improvement in area-delay product Doubling wire count vs. bidirectional routing resources not necessary Source: G. Lemieux, E. Lee, M. Tom, and. Yu, Directional and singledriver wires in FPG interconnect, Field-Programmable Technology, Proceedings IEEE International Conference on, 2004, pp Lemieux et. al (2004) SUVT UNCLSSIFIED