Programmable Logic Arrays (PLAs)

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Erin Caldwell
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#3: Programmable Logic - Regular Logic Structured esign Programmable Logic rrays (PLs)!

1 Programmable Logic! Regular logic " Programmable Logic rrays " Multiplexers/ecoders " ROMs! Field Programmable Gate rrays " Xilinx Vertex Random Logic Full ustom esign S 5 - Spring 27 Lec. #3: Programmable Logic - Regular Logic Structured esign Programmable Logic rrays (PLs)! Pre-fabricated building block of many N/OR gates " ctually NOR or NN " Personalized" by making or breaking connections among gates " Programmable array block diagram for sum of products form inputs N array product terms OR array outputs S 5 - Spring 27 Lec. #3: Programmable Logic - 2

2 Enabling oncept! Shared product terms among outputs example: F = + ' ' F = ' + F2 = ' ' + F3 = ' + personality matrix product inputs outputs term F F F2 F3 ' ' '' input side: = uncomplemented in term = complemented in term = does not participate output side: = term connected to output = no connection to output reuse of terms S 5 - Spring 27 Lec. #3: Programmable Logic - 3 efore Programming! ll possible connections available before "programming" " In reality, all N and OR gates are NNs S 5 - Spring 27 Lec. #3: Programmable Logic - 4

3 fter Programming! Unwanted connections are "blown" " Fuse (normally connected, break unwanted ones) " nti-fuse (normally disconnected, make wanted connections) ' ' '' F S 5 - Spring 27 Lec. #3: Programmable Logic - 5 F F2 F3 lternate Representation for High Fan-in Structures! Short-hand notation--don't have to draw all the wires " Signifies a connection is present and perpendicular signal is an input to gate notation for implementing F = + ' ' F = ' + ' '' ' ' S 5 - Spring 27 Lec. #3: Programmable Logic - 6 +'' '+'

4 Programmable Logic rray Example! Multiple functions of,, " F = " F2 = + + " F3 = ' ' ' " F4 = ' + ' + ' " F5 = xor xor " F6 = ( xnor xnor ) F F2 F3 F4 F5 F6 full decoder as for memory address bits stored in memory F F2 F3 F4 F5 F6 ''' '' '' ' '' ' ' S 5 - Spring 27 Lec. #3: Programmable Logic - 7 PL esign Example! to Gray code converter W X Y Z X X X X X X K-map for W X X X X X X X K-map for X X minimized functions: W = + + X = ' Y = + Z = ''' + + ' + ' ' X X X X X K-map for Y X X X X X K-map for Z S 5 - Spring 27 Lec. #3: Programmable Logic - 8

5 PL esign Example (cont d)! ode converter: programmed PL ' ''' ' ' minimized functions: W = + + X = ' Y = + Z = ''' + + ' + ' ' not a particularly good candidate for PL implementation since no terms are shared among outputs however, much more compact and regular implementation when compared with discrete N and OR gates W X Y Z S 5 - Spring 27 Lec. #3: Programmable Logic - 9 PL esign Example! to Gray code converter W X Y Z X X X X X X K-map for W X X X X X X X K-map for X X minimized functions: W = X = Y = Z = X X X X X K-map for Y X X X X X K-map for Z S 5 - Spring 27 Lec. #3: Programmable Logic -

6 PL esign Example #! to Gray code converter W X Y Z minimized functions: W = X = Y = Z = X X X X X X S 5 - Spring 27 Lec. #3: Programmable Logic - K-map for W X X X X X X K-map for Y X X X X X X K-map for X X X X X X X K-map for Z PL esign Example #2! Magnitude comparator '''' '' K-map for EQ K-map for NE '' ' ' ' ' '' ' '' K-map for LT K-map for GT S 5 - Spring 27 Lec. #3: Programmable Logic - 2 EQ NE LT GT

7 Multiplexer/emultiplexer: Making onnections! irect point-to-point connections between gates! Multiplexer: route one of many inputs to a single output! emultiplexer: route single input to one of many outputs control control multiplexer demultiplexer 4x4 switch S 5 - Spring 27 Lec. #3: Programmable Logic - 3 Multiplexers/Selectors! Multiplexers/Selectors: general concept " 2 n data inputs, n control inputs (called "selects"), output " Used to connect 2 n points to a single point " ontrol signal pattern forms binary index of input connected to output Z = ' I + I functional form logical form Z I I two alternative forms for a 2: Mux truth table I I Z S 5 - Spring 27 Lec. #3: Programmable Logic - 4

8 Multiplexers/Selectors (cont'd)! 2: : Z = ' I + I! 4: : Z = ' ' I + ' I + ' I2 + I3! 8: : Z = '''I + ''I + ''I2 + 'I3 + ''I4 + 'I5 + 'I6 + I7! In general, Z =! (m k I k ) 2 n - " in minterm shorthand form for a 2 n : Mux I I 2: k= Z I I I2 I3 4: Z I I I2 I3 I4 I5 I6 I7 8: Z S 5 - Spring 27 Lec. #3: Programmable Logic - 5 ascading Multiplexers! Large multiplexers implemented by cascading smaller ones I I I2 I3 I4 I5 I6 I7 4: 4: 2: control signals and simultaneously choose one of I, I, I2, I3 and one of I4, I5, I6, I7 control signal chooses which of the upper or lower 's output to gate to Z 8: Z I I I2 I3 I4 I5 I6 I7 2: 2: 2: 2: alternative implementation 4: 8: Z S 5 - Spring 27 Lec. #3: Programmable Logic - 6

9 Multiplexers as Lookup Tables (LUTs)! 2 n : multiplexer implements any function of n variables " With the variables used as control inputs and " ata inputs tied to or " In essence, a lookup table! Example: " F(,,) = m + m2 + m6 + m7 = ''' + '' + ' + = ''(') + '(') + '() + () : MUX S2 S S F S 5 - Spring 27 Lec. #3: Programmable Logic - 7 Multiplexers as LUTs (cont d)! 2 n- : can implement any function of n variables " With n- variables used as control inputs and " ata inputs tied to the last variable or its complement! Example: " F(,,) = m + m2 + m6 + m7 = ''' + '' + ' + = ''(') + '(') + '() + () : MUX S2 S S F F ' ' ' ' 2 3 4: MUX S S F S 5 - Spring 27 Lec. #3: Programmable Logic - 8

10 Multiplexers as LUTs (cont d)! Generalization n- control variables single data variable I I... I n- I n F I n I n '! Example: F(,,,) implemented by an 8: MUX four possible configurations of truth table rows can be expressed as a function of I n choose,, as control variables multiplexer implementation S 5 - Spring 27 Lec. #3: Programmable Logic : MUX S2 S S nnouncements! We took everyone on the wait list into the class " Result is that evening labs are very crowded! " Think of switching to mid-day labs to get more T face time! " First three labs are done individually need not commit to a project partner yet " Send to jeff@sims.berkeley.edu to request a lab change! First HW due Friday at 2 PM just before Lab Lecture " S 5 hand-in box outside and just to the right of 25 ory doors " iscussions Th@4, F@, to work through old homeworks in 25 ory! Second HW soon on class web site! Use google ucb.class.cs5 newsgroup for lab, hw, course questions! S 5 - Spring 27 Lec. #3: Programmable Logic - 2

11 emultiplexers/ecoders! ecoders/demultiplexers: general concept " Single data input, n control inputs, 2 n outputs " ontrol inputs (called selects (S)) represent binary index of output to which the input is connected " ata input usually called enable (G) :2 ecoder: O = G S O = G S 2:4 ecoder: O = G S S O = G S S O2 = G S S O3 = G S S 3:8 ecoder: O = G S2 S S O = G S2 S S O2 = G S2 S S O3 = G S2 S S O4 = G S2 S S O5 = G S2 S S O6 = G S2 S S O7 = G S2 S S S 5 - Spring 27 Lec. #3: Programmable Logic - 2 emultiplexers as General-Purpose Logic! n:2 n decoder implements any function of n variables " With the variables used as control inputs " Enable inputs tied to and " ppropriate minterms summed to form the function 2 3 3:8 E S2 S S ''' '' '' ' '' ' ' demultiplexer generates appropriate minterm based on control signals (it "decodes" control signals) S 5 - Spring 27 Lec. #3: Programmable Logic - 22

12 emultiplexers as General-Purpose Logic (cont d)! F = ' ' + ' ' +! F2 = ' +! F3 = (' + ' + ' + ') Enable 4:6 E '''' ''' 2 ''' 3 '' 4 ''' 5 '' 6 '' 7 ' 8 ''' 9 '' '' ' 2 '' 3 ' 4 ' 5 F3 F F2 S 5 - Spring 27 Lec. #3: Programmable Logic - 23 ascading ecoders! 5:32 decoder " x2:4 decoder " 4x3:8 decoders F 2:4 E S S 2 3 ''''E' 2 3:8 E S2 S S 2 3:8 E E S2 S S 2 ''E' 3:8 E S2 S S '''E' 2 3:8 E 'E S2 S S E E S 5 - Spring 27 Lec. #3: Programmable Logic - 24

13 Read-only Memories! Two dimensional array of s and s " Entry (row) is called a "word" " Width of row = word-size " Index is called an "address" " ddress is input " Selected word is output decoder n 2 - i j word lines (only one is active!decoder is just right for this) word[i] = word[j] = internal organization n- ddress bit lines (normally pulled to through resistor!selectively connected to by word line controlled switches) S 5 - Spring 27 Lec. #3: Programmable Logic - 25 ROMs and ombinational Logic! ombinational logic implementation (two-level canonical form) using a ROM F = ' ' + ' ' + ' F = ' ' + ' ' + F2 = ' ' ' + ' ' + ' ' F3 = ' + ' ' + ' F F F2 F3 truth table ROM 8 words x 4 bits/word address FFF2F3 outputs block diagram S 5 - Spring 27 Lec. #3: Programmable Logic - 26

14 ROM Structure! Similar to a PL structure but with a fully decoded N array " ompletely flexible OR array (unlike PL) n address lines inputs decoder 2 n word lines memory array (2 n words by m bits) outputs m data lines S 5 - Spring 27 Lec. #3: Programmable Logic - 27 ROM vs. PL! ROM " esign time is short (no need to minimize output functions) " Most input combinations are needed (e.g., code converters) " Little sharing of product terms among output functions " Size doubles for each additional input " an't exploit don't cares " heap (high-volume component) " an implement any function of n inputs " Medium speed! PL " esign tools are available for multi-output minimization " There are relatively few unique minterm combinations " Many minterms are shared among the output functions " Most complex in design, need more sophisticated tools " an implement any function up to a product term limit " Slow (two programmable planes) S 5 - Spring 27 Lec. #3: Programmable Logic - 28

15 Field-Programmable Gate rrays! PLs: s of gate equivalents! FPGs: -s gates! Logic blocks " Implement combinational and sequential logic! Interconnect " Wires to connect inputs and outputs to logic blocks! I/O blocks " Special logic blocks at periphery of device for external connections! Key questions: " How to make logic blocks programmable? " How to connect the wires? " fter the chip has been fabbed S 5 - Spring 27 Lec. #3: Programmable Logic - 29 Tradeoffs in FPGs! Logic block - how are functions implemented: fixed functions (manipulate inputs) or programmable? " Support complex functions, need fewer blocks, but they are bigger so less of them on chip " Support simple functions, need more blocks, but they are smaller so more of them on chip! Interconnect " How are logic blocks arranged? " How many wires will be needed between them? " re wires evenly distributed across chip? " Programmability slows wires down!are some wires specialized to long distances? " How many inputs/outputs must be routed to/from each logic block? " What utilization are we willing to accept? 5%? 2%? 9%? S 5 - Spring 27 Lec. #3: Programmable Logic - 3

16 Xilinx 4 Series Programmable Gate rrays! L - onfigurable Logic lock " 5-input, output function " or 2 4-input, output functions " optional register on outputs! uilt-in fast carry logic! an be used as memory! Three types of routing " direct " general-purpose " long lines of various lengths! RM-programmable " can be reconfigured IO IO IO IO IO IO IO IO L L Wiring hannels L L S 5 - Spring 27 Lec. #3: Programmable Logic - 3 The Xilinx 4 L S 5 - Spring 27 Lec. #3: Programmable Logic - 32

17 Two 4-Input Functions, Registered Output S 5 - Spring 27 Lec. #3: Programmable Logic Input Function, ombinational Output S 5 - Spring 27 Lec. #3: Programmable Logic - 34

18 L Used as RM S 5 - Spring 27 Lec. #3: Programmable Logic - 35 Xilinx 4 Interconnect S 5 - Spring 27 Lec. #3: Programmable Logic - 36

19 Xilinx FPG ombinational Logic Examples! Key: General functions are limited to 5 inputs " (4 even better - /2 L) " No limitation on function complexity! Example " 2-bit comparator: = and > implemented with L (GT) F = ' + ' + ' ' (EQ) G = ''''+ ' ' + ' '+! an implement some functions of > 5 input S 5 - Spring 27 Lec. #3: Programmable Logic - 37 Xilinx FPG ombinational Logic! Examples " N-input majority function: whenever n/2 or more inputs are " N-input parity functions: 5 input/ L; 2 levels yield 25 inputs! 5-input Majority ircuit L 9 Input Parity Logic L 7-input Majority ircuit L L L L S 5 - Spring 27 Lec. #3: Programmable Logic - 38

20 Xilinx FPG dder Example! Example " 2-bit binary adder - inputs:,,,, IN outputs: S, S, out in L L L L Full dder, 4 L delays to final carry out out S3 2 S2 S S in L out S3 S2 L 2 S S S 5 - Spring 27 Lec. #3: Programmable Logic x Two-bit dders (3 Ls each) yields 2 Ls to final carry out ombinational Logic Implementation Summary! Regular Logic Structures " Programmable Logic rrays # Programmable connections: N-OR (NOR-NOR) rrays " Multiplexers/decoders # Multipoint connections for signal routing # Lookup Tables " ROMs # Truth table in hardware " Field Programmable Gate rrays (FPGs) # Programmable logic (LUTs, Truth Tables) and connections " dvantages/disadvantages of each S 5 - Spring 27 Lec. #3: Programmable Logic - 4

Programmable Logic Arrays (PLAs)

Programmable Logic Arrays (PLAs) Programmable Logic Regular logic Programmable Logic rrays Multiplexers/ecoders ROMs Field Programmable Gate rrays Xilinx Vertex Random Logic Full ustom esign S 5 - Fall 25 Lec. #3: Programmable Logic -