05/11/2006. Lecture What does a computer do? Logic Manipulation. Data manipulation

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1 5//26 What does a computer do? Logic Manipulation Transistors Digital Logic Computers Computers store and manipulate information Information is represented digitally, as voltages Digital format avoids ambiguity below. interpreted as (5V CMOS logic) above 3. interpreted as (5V CMOS logic) Information can be manipulated in many ways: can be compared to other information mathematical operations define state of devices (display, speakers, motors, etc.) 2 Transistors: The Main uilding lock Transistors, as applied to logic designs, act as voltage- controlled switches gate n-channel MOSFET is closed when positive voltage () is applied, open when zero voltage p-channel MOSFET is open when positive voltage () is applied, closed when zero voltage (MOSFET means metal-oxide semiconductor field effect transistor) drain source V n-channel MOSFET voltage voltage gate source drain p-channel MOSFET V Data manipulation ll data manipulation is based on logic Logic follows well defined rules, producing predictable digital output from certain input Examples: ND C OR XOR NND NOT C NOR V V < < 3 bubbles mean inverted (e.g., NOT ND NND) 4 Lecture 2

2 5//26 Logic Gates The logic operations are carried out electronically by gates, represented by the symbols just introduced Gates are constructed out of transistors,, typically per gate Transistors simply act like switches,, controlling data flow Gate response is typically ~ nanosecond ( billionth sec.) Can theoretically build an entire computer using only NND (or NOR) gates nd then you can take over the world! (sinister laugh ) n inverter (NOT) from MOSFETS: input V output V V V input turns OFF lower (n-channel( n-channel) ) FET, turns ON upper (p-channel( p-channel), so output is connected to input turns ON lower (n-channel( n-channel) ) FET, turns OFF upper (p-channel( p-channel), so output is connected to V Net effect is logic inversion: 5; 5 Complementary MOSFET pairs CMOS V V NOT C 5 6 IN IN NND gate from scratch: V OUT C oth inputs at zero: lower two FETs OFF, upper two ON result is output HI oth inputs at : lower two FETs ON, upper two OFF result is output LOW IN at 5V, IN at V: upper left OFF, lowest ON upper right ON, middle OFF result is output HI IN at V, IN at : opposite of previous entry result is output HI NND 7 NND invert both inputs NND-based gate construction NOT C OR ND invert output (invert NND) NOR invert inputs and output (invert OR) 8 Lecture 2 2

3 5//26 rithmetic Example Let s s add two binary numbers: = 46 = 77 = 23 How did we do this? We have rules: = ; = = ; = (2): (, carry ); (carried ) = (3): (, carry ) Rules can be represented by gates If two input digits are &, output digit looks like XOR operation (but need to account for carry operation) XOR 9 Can make rule table: C in D C out Digits & are added, possibly accompanied by carry instruction from previous stage Output is new digit, D, along with carry value D looks like XOR of & when C in is D looks like XNOR of & when C in is C out is if two or more of,, C in are inary rithmetic in Gates 8-bit binary arithmetic (cascaded) C in E F G Input Intermediate Output in E F H G D C out H D C out C in Integrated Chip Each digit requires 6 gates Each gate has ~6 transistors ~36 transistors per digit C out D MS = 46 = 77 = 23 Carry-out tied to carry-in of next digit. Magically adds two binary numbers Up to ~3 transistors for this basic function. lso need,, /, & lots more. LS = Least Significant it Integrated one-digit binary arithmetic unit (prev. slide) 2 Lecture 2 3

4 5//26 Computer technology built up from pieces The foregoing example illustrates the way in which computer technology is built start with little pieces (transistors acting as switches) combine pieces into functional blocks (gates) combine these blocks into higher-level function (e.g., addition) combine these new blocks into cascade (e.g., 8-bit addition) blocks get increasingly complex, more capable Nobody on earth understands Pentium chip inside-out Grab previously developed blocks and run Let a computer design the gate arrangements (eyes closed!) Data Storage Within the computer, data is stored in volatile memory (RM) essentially charge held on a capacitor also possible to rig two NND gates to hold one bit called a flip-flop volatile because it goes away when turned off lso store data permanently, usually on magnetic media (floppies, hard drives, tapes) or on optical discs (CD-ROMs, DVDs) information encoded as polarization of magnetic domains older technology used wire coils around ferrite cores (like transformer) to detect/generate magnetic fields 3 4 Example: Flip-Flop Memory Input : Input : C D Outputs NND flip-flop D?? This simple arrangement of two NND gates retains a memory: Imagine and are in the high state (both ) C =, D = is valid, but so is C =, D = can set the state by dropping or low momentarily when and are restored to high, the previous state is remembered : e.g., went low D sticks on Digital Data Everywhere Remote Controls Computer Communications 5 Lecture 2 4

5 5//26 Most of today s s information is digital Most of today s s information is digital Computer communications Cell phone signals TV is moving this way TV remote controls Even our beloved in-class infrared transmitters Today, we ll look at a number examples start with H-ITT transmitter also check out TV remote (actually for stereo) look at serial data communication The H-ITT Transmitter Signal When you click your transmitter button: E: LED indicator comes on, and at same time, TWO bursts of infrared light come out: LED stays on even after transmission stops, until button is released * button: on release of button, LED flashes and two infrared bursts are sent st data packet 2 nd data packet bursts last 53 milliseconds, are 9 ms apart, and have a bitperiod of about.5 ms (about 2 bits per second) Let s s look at it on scope 7 8 H-ITT Transmitter Protocol Comparison of & first packets Transmitter sends an first packet Transmitter sends a second packet first packet Differences are minor, showing up only near beginning & end We will represent high states (light on) as s, and lows (off) as s second packet Notice standard widths: choices are single- or double-width (both for the zeros and the ones) 9 2 Lecture 2 5

6 5//26 Decoding the signal The different buttons: first four bits Sequence starts out: Notice the delimiters: This gives the signal its choppy appearance (never see 3 s or s in a row) ctual data appears between delimiters: s look fat, s look skinny Resulting bit-sequence for signal (both packets) is: end delimiter C first bit always 2 3 D E 4 5 button code transmitter ID (normal and inverted) checksum 2 << 6 22 The Transmitter ID bytes Transmitter number is binary-coded in the usual sense: Sum is: = this exactly the number pasted behind the battery Second packet inverts all the bits to ensure data integrity What s s with the Checksum? button code transmitter ID (normal first-packet version) checksum reak data into chunks of 8 bits (bytes) and add up: Checksums provide a sanity check on the data integrity Lecture 2 6

7 5//26 nother example using newer remote Stereo Remote Control button code transmitter ID (normal first-packet version) checksum You can use this (first, non-inverted burst) data to verify your understanding Don t t look at the answers if you want to challenge yourself first answers on last slide are: button code, transmitter ID, inverted packet contents also check that checksum adds up properly (ignore final carry digit) Similar to H-ITT transmitters in principle: bursts of infrared light carrying digital information punctuated by delimiters so no long sequences of s or s Key differences: signal initiated by a WKE UP! constant-on burst pattern that follows is repeated indefinitely until button is released I can never get fewer than three packets packet is variable in length depending on button data packet data packet data packet Sample patterns for data packet POWER VOL VOL 2 3 Different Code The radio remote uses a different scheme: does not use the delimiters like H-ITT did instead, uses to represent zero, and to represent sequence for the 5 button is: ID part data part in data part, least significant bit (LS) is first so the number part of 5 is least significant digit is first, so reverse order for more familiar form: = 5 remote ID? data Lecture 2 7

8 5//26 Serial Communication: Getting the Data Once the H-ITT receiver gets your IR signal, it must communicate this to the computer It does this through the serial port serial refers to the fact that data bits arrive in series (one at a time) alternative is parallel (one wire for each bit), where typically 8 bits (a byte) arrive simultaneously Most digital communications are of serial type IR transmitters! (only one channel for light) US, Firewire ethernet, modems cell phones Parallel sometimes used for printers, but most notably on computer motherboards now 32-bit wide communications is the standard parallel is faster, but more complicated to pull off: lots of wires look at the H-ITT Serial Datastream E-button on H-ITT (first of two packets): Serial datastream looks a lot different this one allows many zeros or ones in a row delimiters (called start bit and stop bit) bracket 8-bit data ( byte) in this case, s are positive voltage, s are negative (backwards!) happens much faster than IR: in this case 9,2 bits/sec (baud) Packet breakdown: first packet: button number (5 E), with LS first: next three packets are ID, also LS first within each last packet is checksum type of verification H-ITT bursts serial bursts 29 st data packet 2 nd data packet 3 Wrap-up: Digital Data Everywhere Our world now runs on information and most of this is broken down to binary bit codes for transmission, manipulation, storage Digital advantage is noise immunity very easy to tell a from a, even in the presence of environmental noise ssignments HW 4 due today Check website for reading assignments HW 5 T by end of today Q/O #3 due tomorrow (5/2) by 6 PM 3 ; 24935; Lecture 2 8

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1

Chapter 3. H/w s/w interface. hardware software Vijaykumar ECE495K Lecture Notes: Chapter 3 1 Chapter 3 hardware software H/w s/w interface Problems Algorithms Prog. Lang & Interfaces Instruction Set Architecture Microarchitecture (Organization) Circuits Devices (Transistors) Bits 29 Vijaykumar