Supertex inc. MD1213DB1 MD TC6320 Demoboard High Speed ±100V 2A Pulser. Block Diagram TC6320 MD1213. Demoboard Features. General Description

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1 MDDB MD + TC0 Demoboard High Speed ±00V A Pulser General Description The MDDB can drive a transducer as a single channel transmitter for ultrasound and other applications. The demoboard consists of one MD in a -Lead xx0.9mm QFN (K) package, combined with Supertex s TC0, an IC containing high voltage P- and N- channel FETs in a 8- Lead SOIC package. Logic control inputs INA, and OE of the MD are controlled via the six-pin head connector on the board. Due to the fast signal rise and fall time requirement, every ground wire of the ribbon cable must be used to connect from the logic signal source. When OE is enabled, it should recieve the same voltage as the logic source circuit s power supply. The MDDB output waveforms can be displayed directly using an oscilloscope by connecting the scope probe to the test point TP0- and TP0- (GND). The J jumper can select whether or not to connect the on-board equivalentload, a 0pF 00V capacitor paralleled with a.0kω, W resistor. Also, a coaxial cable can be used to easily connect to the user s transducer. Demoboard Features Demonstrates one channel ultrasound transmitter MD driving a TC0 power MOSFET ±.0 A source and sink current capability Logic control signal input connector SMA connectors for cable to a transducer.8 to.v CMOS logic interface Designing a Pulser with the MD Low input capacitance and fast switching speed are the important features of the MD s input stage. Its logic inputs have an input impedance of about 0kΩ in parallel with pf, and an internal speed of around 00MHz. The output enable pin, OE, determines the threshold voltage for the input-channel level translators. The input stage logic is fully compatible with.8v,.0v,.v,.v, or.0v CMOS logic. The level translators are also compatible with these logic voltage levels, up to the MOSFET s gate-driver voltage level, which is typically.0 to V. When OE is low, the chip disables its outputs, setting OUTA high and OUTB low. This condition helps to properly precharge the AC coupling capacitors that the user can optionally add in series with the gate-driver circuit of the external P/Nchannel FET pair. Block Diagram VH OE INA OUTA 0 to 00V.0µF OE INA Level Shifter 0 to 00V HV OUT XDCF C L R L OUTB TC0.0µF MD GND Doc.# DSDB-MDDB B0

2 MDDB The MD s output stage has separate power pins that enable users to select the output signal s high and low levels independently from the supply voltages used by the main the circuit. For example, the input logic levels could be 0V and.v, and the output levels may lie anywhere in the range of ±.0V. Typically, the MD s output has rise and fall times of about.0ns when driving a 000pF load. The output stage is capable of peak currents of up to ±.0A, depending on the system s supply voltages and load capacitance. Such high currents are necessary to drive the input capacitances of the output MOSFETs for fast switching speeds. The bottom of the MD -Lead QFN package has a thermal pad for power dissipation enhancement. It must externally connect to the VSS pin on the PCB. This pad is connected internally to the substrate of the IC circuit. It must have the lowest potential voltage of the circuit at all times, including during the power up or down periods, or it could cause circuit latch-up or damage. The Supertex TC0 is comprised of an N- and P-channel MOSFET pair with low threshold voltages (.0V maximum). This 8-Lead SO packaged device features 00V breakdown voltage,.0a peak current output capabilities, and low input capacitance (0pF maximum). The TC0 integrates the gate-source resistors and Zener diodes that a high voltage pulse-driver requires. The high output current capability of the TC0 MOSFET speeds output waveform rise and fall time, while their low input capacitance minimizes propagation delays. During power up/down conditions, the high voltage supplies V PP and V NN can inject transient voltages greater than 0V via the output transistor s parasitic gate-to-source capacitances. The maximum permissible gate-to-source voltage (V GS ) is ±0V. The TC0 s integral - 8V Zener diodes across its gate and source terminals protect against such transient voltages. But even if it is possible to slowly ramp the high voltage supplies, these Zener diodes are still crucial, as they also serve as the DC voltage restoration stage for the gates. Note that it is possible to vary the V PP and V NN voltages without making significant changes to the circuit configuration. For example, V NN can be 0V and V PP +00V for positive unipolar pulses. Or V NN can be -00V and V PP 0V for a negative unipolar pulser. If the user plans to operate the demoboard above 00V, he must adjust the bypass capacitors (C8 or C) to a voltage rating of 00V. Due to the BV limitation of the TC0, the differential voltage (V PP -V NN ) must not be greater then 00V. Operating Supply Voltages Symbol Parameter Min Typ Max Units Conditions Negative drive supply Positive drive supply Logic supply.8.. V --- V PP TC0 HV positive supply 0-00 V --- V NN TC0 HV negative supply V --- Board Layout V ( - ) V ( - ) Doc.# DSDB-MDDB B0

3 MDDB Current Consumption Symbol Typ Units Conditions I DD 0.7 ma = V I H 0.7 ma = V I CC 8 ma =.V I PP. ma V PP = 00V I NN. ma V NN = -00V Waveform C, 0MHz, 8 cycles, = = 0 Load: 0pF//.0k Voltage Supply Power-Up Sequence Logic voltage supply, and all OE = INA = = Low Positive drive voltage for, 0 or -.0V negative bias voltage for, and IC substrate voltage 0 to -.0V or negative driver voltage for 0 to +0 or positive driver voltage for V PP +/-HV supply, slew rate not exceed.0v/ms Note: The power-down sequence should be the reverse of the power-up sequence above Board Connector and Test Pin Description Logic Control Signal Input Connector Pin Name Description J- Logic voltage supply for J- OE MD OE signal for pulser output enable, when OE=0, TC0 P and N MOSFET both off. J- GND Logic ground J- INA --- J- GND Logic ground J- --- Power Supply Connector Pin Name Description J- +. logic voltage supply for J- VSS 0 or -.0V negative bias supply for, and SUB J- 0 or -.0V negative voltage supply for driver output stage J- GND Power supply ground J- VDD +0V positive driver voltage supply for and J- VH +0 or +.0V positive voltage supply for driver output stage J- VPP 0 to +00V positive high voltage supply with current limiting maximum to.0a J- GND High voltage power supply return, 0V J- VNN 0 to -00V Negative high voltage supply with current limiting maximum to -.0A Doc.# DSDB-MDDB B0

4 Schematic Diagram MDDB FB VPP TP9 0 8 U MD VDD VDD VH J TP OE R9 OUTA 9 00Ω TP INA TP C.0 C0 0n 00V U R 00Ω VNN P TC0 N 7 8 TP TP TP TP + + C 0 V J J XDCR + + C 0. DB C 0. C0 0. C.0 TP7 GND VSS C8 0. SUB VSS C7 0. OUTB 7 TP C9 0n 00V TP C 0 V J C 0 V C 0 V VDD DA DA VSS DB DB DA VH D B00- VPP C.0µ 00V D BAV99 C8.0µ 00V C.0µ 00V TP0 R0 00Ω C 0 TP8 J R 00Ω R.0kΩ.0W VNN C.0µ 00V D B00- Doc.# DSDB-MDDB B0

5 Waveforms MDDB Fig : INA,, OUTA, OUTB and HV OUT with 0pF//K Load, = =+V, = = +/-00V, 0MHz Fig : INA,, OUTA, OUTB and HV OUT with 0pF//K Load, = = +V, = = +/-00V, 0MHz Fig :INA,, OUTA, OUTB and HV OUT with 0pF//K Load, = =+V, = = +/-00V,.kHz does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 0 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-MDDB B0 Bordeaux Drive, Sunnyvale, CA 9089 Tel: