Supertex inc. MD1822DB3. MD TC8220: Three Level High Speed ±100V 3.0A Pulser Demoboard. Waveform Generator CPLD.

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1 MD8 + TC8: Three Level High Speed ±V.A Pulser Demoboard MD8DB Demoboard Features Ultrasound high voltage & high current RTZ pulser MD8 driving TC8 with two pairs of MOSFETs -level voltage pulse waveform outputs ±.A source and sink current capability MHz frequency clock on board Programmable logic waveform generation JTAG connection for CPLD programming Connectors for external clock and signals.v CMOS logic interface Applications Medical ultrasound imaging Piezoelectric transducer drivers Material flaw detection ATE and waveform generator Transducer power driver Capacitive and MEMS sensor driver Ultrasonic DT detection and sonar ranger General Description The MD8DB is a demoboard for the three level ±V.A pulser chip-set of the MD8 MOSFET driver and the TC8 MOSFET. The demoboard consists of one MD8 in the xmm -lead QF package driving the TC8 which has two pairs of high speed and high voltage complimentary P- and -MOSFETs in in one xmm, 8-lead DF package. This circuit is an ideal, cost-optimized, high voltage and high current RTZ ultrasound transmit pulser. The CPLD-programmable logic circuit ( MHz crystal oscillator) generates accurately timed high-speed waveforms on a separate CPL board. Multiple frequency and waveform combinations can be selected as bipolar pulse waveforms. An external clock input can be used if the on-board oscillator is disabled. The external trigger input can be used to synchronize the output waveforms. There are five push buttons for selecting demonstration waveform, frequency, phase, and mode functions. Color LEDs indicate the demo selection states. Jumpers on the board can select either the pf/.k on-board load, or user test loads. Block Diagram JTAG +.V +V EXTRG PE IC VDD/VH +V EXCLK MHz OSC E EXT CLK I Waveform Generator CPLD ID IA IB -V C L pf R L.k XDCR X WAVE FREQ SEL CLMP EAB LED LED PWR EA MOD VSS/VL MD8 TC8 Doc.# DSDB-MD8DB A9

2 MD8DB Board and PCB Layout MD8DB Actual size = mm x 7mm Operating Supply Voltages and Current (on J) Symbol Parameter Min Typ Max Units Suggested Current Limit * Logic supply.8.. V ma GD Circuit ground or V - - V --- V DD MD8 positive supply.. V ma TC8 HV positive supply - V.mA TC8 HV negative supply - - V.mA ote: * Current limits should be changed according the testing waveform, frequency and duty cycles. Push Button Operation Functions Button Symbol WAVE FREQ SEL EA PHASE Description Demo waveforms selection Demo waveform frequency selection ot Used MD8 PE pin control ot Used Doc.# DSDB-MD8DB A9

3 MD8DB J CH E G MHzX D V O C U C C. T TP7 YLW R k C. R8 TP TP C TP. V SS TP7 J8 TP TP JTAG PP V V DD U MD8 PE IC ID IA IB GD VDD VSS VSS 7 VH VL V DD VH OUTC OUTD OUTA OUTB VL 7 SW 8 9 CD nf UB P P C µf V 7 9 R 8 R. TC8K D9 MMBDBRM C8 p V J9 8 7 GD GD GD WAV FRE SEL EABLE 7 PHASE.C..C. 9 TMS TDI TDO TCK VCC VCC VCC P E C D A B 8 9 I I I I Schematic Diagram LED LED LED PWR EA 9 8 J EX=Low J EXCLK J7 EXTRG D D D D D R C R R9 R k TP R k TP TP8 R k TP TP TP YLW YLW GR RED TESTA C E H X T R k TESTB TESTC CLK R k R G R k R7 k R k U XC97XZ - VQ R k R k C7. C8. C9. R8 R9 R R TP C. R9 R TP TP R R7 C. DB TP D7 B- C. TP D8 B- TP SW R C7. SW R7 C8. SW R8 C9. SW R9 C. R C. DA J Header CC nf CB nf 7 C µf V UA R R R R.9k W TXOUT TP CA nf R8 Doc.# DSDB-MD8DB A9

4 Demo Waveforms Demo Waveform A (8-Cycle) Demo Waveform A` (8-Cycle) MD8DB P I I TX V Demo Waveform B (-Cycle) Demo Waveform B` (-Cycle) P I I TX V Demo Waveform C (.-Cycle) Demo Waveform C` (.-Cycle) P I I TX V Doc.# DSDB-MD8DB A9

5 MD8DB Demo Waveforms (cont.) Demo Waveform D(8-Cycle w/o Damping) P I I TX V Demo Waveform E (-Cycle w/o Damping) P I I TX V Doc.# DSDB-MD8DB A9

6 Test Waveforms MD8DB Fig : Input and output waveforms at V DD = V, / = ±7V, Load = pf//.k. Fig : Input and output waveforms at V DD = V, / = ±7V, Load = pf//.k. Doc.# DSDB-MD8DB A9

7 MD8DB Test Waveforms (cont.) Fig : Input and output waveforms at V DD =V, / = ±7V, Load = pf//.k. Fig : Input to output delay and rise time of output at V DD = V, / = ±7V, Load = pf//.k, I OUT = pf(v/.ns) =.A. Doc.# DSDB-MD8DB A9 7

8 MD8DB Test Waveforms (cont.) Fig : Input to output delay and fall time of output at V DD = V, / = ±7V, Load = pf//.k, I OUT = pf(v/.ns) =.A. JTAG or Boundary Scan Mode JTAG or Boundary Scan mode is an industry standard (IEEE 9., or ) serial programming mode. External logic from a cable, microprocessor, or other device is used to drive the JTAG specific pins, Test Data Out (TDO), Test Data In (TDI), Test Mode Select (TMS), and Test Clock (TCK). This mode has gained popularity due to its standardization and ability to program CPLD through the same four JTAG pins. The data in this mode is loaded at one bit per TCK. JTAG Connector Pin umber Description J8- TMS Test Mode Select of CPLD. J8- TDI Test Data In of CPLD. J8- TDO Test Data Out of CPLD. J8- TCK Test Clock of CPLD. J8- GD Logic Power Supply Ground V for programming and testing only. J8- VCC Logic Power Supply +.V for CPLD programming or testing only. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. o responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSDB-MD8DB A9 8 Bordeaux Drive, Sunnyvale, CA 989 Tel: