Supertex inc. VN10K. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.

Transcription

1 VN1K N-Channel Enhancement-Mode Vertical DMOS FET Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral source-drain diode High input impedance and high gain Applications Motor controls Converters Amplifiers Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.) Ordering Information Part Number Package Option Packing VN1KN3-G 1/Bag VN1KN3-G P2 VN1KN3-G P3 VN1KN3-G P5 VN1KN3-G P13 VN1KN3-G P14 2/Reel -G denotes a lead (Pb)-free / RoHS compliant package. Contact factory for Wafer / Die availablity. Devices in Wafer / Die form are lead (Pb)-free / RoHS compliant. Absolute Maximum Ratings Parameter Value Drain-to-source voltage BS Drain-to-gate voltage BV DGS Gate-to-source voltage ±3V Operating and storage temperature -55 O C to +15 O C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Typical Thermal Resistance Package Doc.# DSFP-VN1K B31411 θ ja 132 O C/W General Description This enhancement-mode (normally-off) transistor utilizes a vertical DMOS structure and Supertex s well-proven, silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally-induced secondary breakdown. Supertex s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Product Summary BS /BV DGS Pin Configuration Product Marking SiVN 1K YYWW SOURCE (max) DRAIN GATE YY = Year Sealed WW = Week Sealed = Green Packaging Package may or may not include the following marks: Si or SS (min) 6V 5. 75mA

2 Thermal Characteristics Package (continuous) (pulsed) Power C = 25 O C VN1K 31mA 1.A 1.W 31mA 1.A Notes: (continuous) is limited by max rated T j. (VN16N3 can be used if an (continuous) of 5mA is needed.) R RM Electrical Characteristics (T A = 25 O C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage V = V, = 1µA (th) Gate threshold voltage V =, = 1.mA Δ(th) Change in (th) with temperature mv/ O C =, = 1.mA I GSS Gate body leakage na = 15V, = V = V, = 45V SS Zero gate voltage drain current µa V GS = V, = 45V, T A = 125 C (ON) On-state drain current A = 1V, = 1V Static drain-to-source on-state resistance V GS = 5.V, = 2mA = 1V, = 5mA Δ Change in with temperature %/ O C = 1V, = 5mA Forward transductance mmho = 1V, = 5mA C ISS Input capacitance = V, C OSS Common source output capacitance pf = 25V, C RSS Reverse transfer capacitance f = 1.MHz t (ON) Turn-on time t (OFF) Turn-off time ns V DD = 15V, = 6mA, R GEN = 25 V SD Diode forward voltage drop V = V, I SD = 5mA t rr Reverse recovery time ns = V, I SD = 5mA Notes: 1. All D.C. parameters 1% tested at 25 O C unless otherwise stated. (Pulse test: 3µs pulse, 2% duty cycle.) 2. All A.C. parameters sample tested. Switching Waveforms and Test Circuit 1V INPUT V 1% 9% Pulse Generator VDD R L OUTPUT t (ON) t (OFF) R GEN t d(on) t r t d(off) t f VDD OUTPUT 1% 1% INPUT D.U.T. V 9% 9% Doc.# DSFP-VN1K B

3 Typical Performance Curves VN1K 1.1 BS Variation with Temperature On-Resistance vs. Gate-to-Source Voltage 1 =.1V BS (normalized) 1. (ohms) T j ( O C) Transfer Characteristics = 1V 3µs, 2% Output Conductance vs Drain Current 1. = 25V 8µs, 1%.6.4 (mhos).1 Reduction Due to Heating Capacitance vs. Drain-to-Source Voltage 5 Transconductance vs Gate-Source Voltage 25 4 C ISS 2 = 1V 3µs, 2% Duty Cycle C (picofarads) 3 2 Gfs (m ) C OSS 5 C RSS Doc.# DSFP-VN1K B

4 VN1K Typical Performance Curves (cont.) Output Characteristics 1. = 1V 8V 7V.8 6V 1..8 Saturation Characteristics = 1V 7V 9V 8V 6V.6.4 5V.6.4 5V 4V.2 3V 2V V.2 3V 2V Transconductance vs. Drain Current Power Dissipation vs. Case Temperature 2. 2 (m ) 15 1 P D (watts) 1. 5 = 1V 3µs, 2% (ma) T C ( O C) 1 Maximum Rated Safe Operating Area 1 Switching Waveform 1..1 (DC) T C = 25 O C Output Voltage Input Voltage t Time (ns) Doc.# DSFP-VN1K B

5 3-Lead Package Outline (N3) VN1K D Seating Plane A L e1 e Front View b c Side View E1 1 3 E 2 Bottom View Dimensions (inches) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 213 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-VN1K B31411 Symbol A b c D E E1 e e1 L MIN NOM MAX * JEDEC Registration. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings not to scale. Supertex Doc.#: DSPD-3TO92N3, Version E Bordeaux Drive, Sunnyvale, CA 9489 Tel: