Understanding MOSFET Data. Type of Channel N-Channel, or P-Channel. Design Supertex Family Number TO-243AA (SOT-89) Die

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1 Understanding MOSFET Data Application Note The following outline explains how to read and use Supertex MOSFET data sheets. The approach is simple and care has been taken to avoid getting lost in a maze of technical jargon. The VN3205 data sheet was chosen as an example because it has the largest choice of packages. The product nomenclature shown applies only to Supertex proprietary products. VN3205 Device Structure V: Vertical DMOS (discretes & quads) D: Vertical Depletion-Mode DMOS discretes T: Low threshold vertical DMOS discretes L: Lateral DMOS discretes Type of Channel N-Channel, or P-Channel Design Supertex Family Number Drain-to-Source Breakdown Voltage divided by : 50V Advanced DMOS Technology This enhancement-mode (normally-off) DMOS FET transistors utilize a vertical DMOS structure and Supertex s wellproven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and negative temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally-induced secondary breakdown. Supertex vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speed are desired. This section outlines main features of the product. N-Channel Enhancement-Mode Vertical DMOS FETs Ordering Information Device TO-92 Package Options 14-Lead PDIP TO-243AA (SOT-89) Die BS /BV DGS (V) max (Ω) VN3205 VN3205N3-G VN3205P-G VN3205N8-G VN3205ND min Drain to source breakdown voltage & drain to gate breakdown voltage. Maximum from drain to source when device is fully turned on. Minimum drain current when device is fully turned on.

2 Package Options TO-92 SOT-89 Low power Plastic Cost effective Mainly commercial applications Low profile Low θ JC thermal Commercial and industrial applications Ordering Information Device TO-92 Package Options 14-Lead PDIP TO-243AA (SOT-89) Die BS /BV DGS (V) max (Ω) VN3205 VN3205N3-G VN3205P-G VN3205N8-G VN3205ND min 14-Lead DIP Wafer Waffle Pack Dual in line plastic 4 die in one package Commercial and industrial applications NW: Die in wafer form 6 inch diameter wafers Reject dice are inked ND: die in waffle pack Die can be visually inspected to commercial (standard) or military visual criteria (specify while ordering) 2

3 Absolute Maximum Ratings Extreme conditions a device can be subjected to electrically and thermally. Stress in excess of these ratings will usually cause permanent damage. Absolute Maximum Ratings Parameter Drain-to-source voltage Drain-to-gate voltage Value BS BV DGS Gate-to-source voltage ±20V Ratings given in product summary. Operating and storage temperature -55 C to +150 C Most Supertex FETs are rated for ±20V. ±voltage handling capability allows quick turn off by reversing bias. External protection should be used when there is a possibility of exceeding this rating. Stress exceeding ±20V will result in gate insulation degradation and eventual failure. Soldering temperature* +300 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds. Maximum allowable temperature at leads while soldering, 1.6mm away from case for 10 seconds. All Supertex devices can be stored and operated satisfactorily within these junction temperature (T J ) limits. Appropriate derating factors from curves and change in parameters due to reduced/elevated temperatures have to be considered when temperature is not 25 C. Operation at T J below maximum limit can enhance operating life. 3

4 Thermal Characteristics Device characteristics affecting limits of heat produced and removed from device. Die size, and packaging type are the main factors determining these thermal limitations. Thermal Characteristics Package I D (continuous) * I D (pulsed) Power C = 25 O C (W) θ jc ( O C/W) θ ja ( O C/W) TO Lead PDIP TO-243AA (T A = 25 O ) Notes: * I D (continuous) is limited by max rated T J, T A = 25 O C. Total for package. Mounted on FR5 board, 25mm x 25mm x 1.57mm. I DR I DRM I D (continuous) Maximum continuous current carrying capability of device. Depends mainly on: - on state. P D - maximum power dissipation for package. Die size. Maximum junction temperature. ID (pulsed) Maximum non-continuous pulse current carrying capability for a 300µs 2% duty cycle pulsed. Depends mainly on:. P D max. Diameter of bonding wire. Die size. Maximum junction temperature. Power Dissipation Maximum power package can dissipate when case temperature is 25 C. When case temperature is higher than 25 C, use P D vs. T C curve to determine dissipation permissible. I DRM 300µs, 2% duty cycle pulsed. Current handling capability of drain source diode. Factors affecting value same as I D (pulsed). I DR Continuous current handling capability of drain to source diode. Factors affecting value same as I D (continuous). θ JA Thermal from junction to air. Depends mainly on package and die size. θ JC Thermal from junction to case. Depends mainly on package and die size To determine T J use equation: T J = P D x θ JC + T C 4

5 Electrical Characteristics Electrical Characteristics (T A = 25 O C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage V I D (th) Gate threshold voltage V = Δ(th) Change in (th) with temperature mv/ O C = Gate body leakage current na = ±20V, = 0V Zero gate voltage drain current µa = Max Rating ma = 0.8 Max Rating, T A = 125 O C On-state drain current A = 10V, = 5.0V Static TO-92 and PDIP drain-tosource Ω TO-243AA = 0.75A on-state TO-92 and PDIP TO-243AA Δ Change in with temperature %/ O C Forward transconductance mho = 25V = 2.0A Input capacitance Common source output capacitance pf Reverse transfer capacitance f = 1.0MHz t d(on) Turn-on delay time t V DD r Rise time ns I D = 2.0A, Turn-off delay time R GEN = 10Ω Fall time Diode forward voltage drop V I SD Reverse recovery time ns I SD = 1.0A BS (TH) Please see product summary (part I). Positive temperature coefficient. See curve BS vs. T J. Voltage required from gate to source to turn on device to certain I D current value given in condition column. I D measurement condition is low for small die and higher for larger die. Since the gate is insulated from the rest of device by a silicon dioxide insulating layer, this parameter depends on thick-ness/integ rity of layer and size of device. Measured at maximum permissible voltage from gate to source: ±20V. Values of this parameter are often tens/hundreds of times less than pub lished maximum value. Electrical screening is done at 100nA since test equipmenunctions slowly at lower values, which is not practical for mass production. Consulactory for screening lower values. Δ(TH) Threshold voltage reduces when temperature increases and vice versa. Value at temperature other than 25 O C can be determined by (TH) (normalized) vs. T J curve. 5

6 Electrical Characteristics Electrical Characteristics (T A = 25 O C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage V I D (th) Gate threshold voltage V = Δ(th) Change in (th) with temperature mv/ O C = Gate body leakage current na = ±20V, = 0V Zero gate voltage drain current µa = Max Rating ma = 0.8 Max Rating, T A = 125 O C On-state drain current A = 10V, = 5.0V Static TO-92 and PDIP drain-tosource Ω TO-243AA = 0.75A on-state TO-92 and PDIP TO-243AA Δ Change in with temperature %/ O C Forward transconductance mho = 25V = 2.0A Input capacitance Common source output capacitance pf Reverse transfer capacitance f = 1.0MHz t d(on) Turn-on delay time t V DD r Rise time ns I D = 2.0A, Turn-off delay time R GEN = 10Ω Fall time Diode forward voltage drop V I SD Reverse recovery time ns I SD = 1.0A Δ This is the leakage currenrom drain to source when device is fully turned off. Measured by applying maximum permissible voltage between drain and source (BS ) and gate shorted to source ( = 0). Special electrical screening possible at lower values since max. published values are higher to achieve practical testing speeds. Defined as the minimum drain current when device is turned on. Supertex measures min. at = 10V. Although Supertex specifies a typical value of, the designer should use minimum value as the worst case. Positive temperature coefficient. Enhances stability due to current sharing during parallel operation. Drain to source measured when device is partially turned on at = 4.5V, and fully turned on at = 10V. Designers should use maximum values for worst case condition. When better turn on characteristics (ie., low ) is required for logic level inputs, Supertex s low threshold TN & TP devices may be used. Typical value of can be calculated at various conditions by using output characteristics or saturation characteristics family of curves (I D vs. ). increases with higher drain currents. curve has a slight slope for low values of I D, but rises rapidly for high values. 6

7 Switching Characteristics Extremely fast switching compared to bipolar transistors, due to absence of minority carrier storage time during turn off. Switching times depend almost totally on interelectrode capacitance, R S (source impedance) and R L (load impedance) as shown on test circuit. Represents gain of the device and can be compared to H FE of a bipolar transistor. Value is the ratio of change in I D for a change in : = I D Rises rapidly with increasing I D, and then becomes constant in the satur-ation region. See vs. I D curve.,, Supertex interdigitated structures have lowest in the industry for comparable die sizes and exhibit excellent switching characteristics. Values of these capacitances are high at low voltages across them. Please see capacitance vs curves for details. Negligible effect of temperature on capacitances. The following equation may be used for calculating effective value of with Miller Effect. = C GS + (1+ R L ) C GD C GD DRAIN Electrical Characteristics (T A = 25 O C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage V I D (th) Gate threshold voltage V = Δ(th) Change in (th) with temperature mv/ O C = Gate body leakage current na = ±20V, = 0V Zero gate voltage drain current µa = Max Rating ma = 0.8 Max Rating, T A = 125 O C On-state drain current A = 10V, = 5.0V Static TO-92 and PDIP drain-tosource Ω TO-243AA = 0.75A on-state TO-92 and PDIP TO-243AA Δ Change in with temperature %/ O C Forward transconductance mho = 25V = 2.0A Input capacitance Common source output capacitance pf Reverse transfer capacitance f = 1.0MHz t d(on) Turn-on delay time t V DD r Rise time ns I D = 2.0A, Turn-off delay time R GEN = 10Ω Fall time Diode forward voltage drop V I SD Reverse recovery time ns I SD = 1.0A (volts) T d(on) During this period, the drive circuit charges up to (TH). Since no drain currenlows prior to turn on, and consequently remain constant. Region I on the vs. Q G curve shows linear change in voltage with increasing Q G Gate Drive Dynamic Characteristics I II III = 10V = 40V 325pF = C GD + C GS 2 C DS = C GD + C DS GATE C GS SOURCE = C GD 215 pf Q G (nanocoulombs) 7

8 Switching Characteristics t r When is driven to a voltage exceeding (TH), conduction from drain source begins. increases causing increase in due to Miller Effect charge requirements to Region II increase considerably. Gain stabilizes in Region III and Miller Effect is nullified, resulting in a linear change in for increase in Q G. The sequence of events now begins to reverse. discharges through R GEN. The rise of is initially slowed by increase of output capacitance. Electrical Characteristics (T A = 25 O C unless otherwise specified) Sym Parameter Min Typ Max Units Conditions BS Drain-to-source breakdown voltage V I D (th) Gate threshold voltage V = Δ(th) Change in (th) with temperature mv/ O C = Gate body leakage current na = ±20V, = 0V Zero gate voltage drain current µa = Max Rating ma = 0.8 Max Rating, T A = 125 O C On-state drain current A = 10V, = 5.0V Static TO-92 and PDIP drain-tosource Ω TO-243AA = 0.75A on-state TO-92 and PDIP TO-243AA Δ Change in with temperature %/ O C Forward transconductance mho = 25V = 2.0A Input capacitance Common source output capacitance pf Reverse transfer capacitance f = 1.0MHz t d(on) Turn-on delay time t V DD r Rise time ns I D = 2.0A, Turn-off delay time R GEN = 10Ω Fall time Diode forward voltage drop V I SD Reverse recovery time ns I SD = 1.0A rises as the load resistor charges the output capacitance. The reverse recovery time is the time needed for the carrier gradient, formed during forward biasing, to be depleted when the biasing is reversed. An external fast recovery diode may be connected from drain to source to improve recovery time. This is the forward voltage drop of the parasitic diode between drain and source. Diode may be used as a commutator in H bridge configurations or in a synchronous rectifier mode. Excessive fly back voltages may be clamped by this diode in a totem pole configuration. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 2013 All rights reserved. Unauthorized use or reproduction is prohibited Bordeaux Drive, Sunnyvale, CA Tel: