Obsolete. Supertex inc. MD Channel Low-Noise Amplifier. General Description. Features. Applications. Typical Application Circuit

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1 Supertex inc. 4-Channel Low-oise Amplifier MD3880 Features 2.5 ± 0.125V operation 4 independent channels Fully differential inputs and outputs 0.74nV/ Hz input-referred noise at 18.5dB gain Ultra low current noise 0.35pA / Hz 600kΩ /17.5pF internal input impedance 100MHz amplifier bandwidth Linear-in-dB continuous variable gain control Four digital programmable gain settings for GA 60MHz whole channel bandwidth at maximum gain 70dB maximum channel gain Variable gain scaling control Active input impedance matching Applications Medical ultrasound receiver LA & TGC Doppler signal amplification Transducer signal conditioning Typical Application Circuit EBC DC A 1 I 1 I 1 A 1 A 2 I 2 I 2 A 2 A 3 I 3 I 3 A 3 A 4 I 4 I 4 A 4 LA LA LA LA C5 Internal Reference General Description The MD3880 is a 4-channel, variable gain amplifier (VGA) paired with a low noise amplifier (LA) that delivers fully differential input and output for ultrasound applications. The 18.5dB gain of the LA allows the whole channel to have 0.74nV/ Hz of input-referred voltage noise at 5MHz. The LA is capable of active impedance control to improve noise performance, provided that the applications can take advantage of input impedance matching. The output of the LA is fed directly into the VGA without using an external coupling capacitor. The VGA is composed of a voltage controlled attenuator () and a programmable gain amplifier (GA). The can be continuously varied linear-in-db by a control voltage (V TGC ) from 0dB to a maximum 47dB. In addition, the gain of the GA can be varied between four discrete settings. +2.5V VDD GA OUT 1 OUT 1 OUT 2 OUT 2 GA GA GA OUT 3 OUT 3 OUT 4 OUT 4 GD GSC TGC G1 G0

2 Ordering Information in Configuration Device MD3880 ackage Option 84-Lead BCC+ 7.00x7.00mm body 0.80mm height (max) 0.50mm pitch MD3880B2-G in A1 Mark A1 B1 A44 B40 B32 A35 A34 B31 -G indicates package is RoHS compliant ( Green ) B11 B21 A12 A23 Absolute Maximum Ratings arameter, positive supply V I, any input pin voltage range Operating temperature Storage temperature Value -0.5V to +3.5V -0.5V to -40 C to +85 C -65 C to +150 C ower dissipation 2.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. A13 B12 roduct Marking YYWW MD3880B2 LLLLLLLLL 84-Lead BCC+ (Top View) B20 A22 L = Lot umber YY = Year Sealed WW = Week Sealed = Green ackaging ackage may or may not include the following marks: Si or 84-Lead BCC+ ackage Operating Supply Voltages (Over operating conditions unless otherwise specified, = +2.5V, T A = 25 C) Sym arameter Min Typ Max Units Conditions ower supply V T A = -40 C to +85 C I DDQ supply current ma ower down, DC=1, total of all channels I DD supply current ma DC = 0 WR ower dissipation mw Total of all channels mw er channel SRR SRR db f = 100kHz Logic Data and Clock Inputs Characteristics (Over operating conditions unless otherwise specified, = +2.5V, T A = 25 C) Sym arameter Min Typ Max Units Conditions V IH Input logic high voltage V --- V IL Input logic low voltage V --- I IH Input logic high current µa --- I IL Input logic low current µa --- C I Input logic pin capacitance pf --- 2

3 Electrical Characteristics (All typical values are under the condition of T A = + 25 C, = 2.5V, Load resistance = 1.0kΩ across the differential outputs, C LOAD = 1.0pF, f I = 10MHz, G0 = 0, G1 = 0, V GSC = 2.5V, V CM = 1.25V, GAI LA = 18.5dB, Single-ended input: R S = R I = 50Ω. R I is formed by active termination with R FB = 237Ω and C FB, Differential signal output, unless otherwise noted.) Low oise Amplifier Sym arameter Min Typ Max Units Conditions G LA Amplifier gain db --- R I Input resistance kω Without active termination C I Input capacitance pf Without active termination I BIAS Input bias current na From ESD leakage Common mode rejection G0 = G1 = V CMRR db DD, V TGC = 2.0V, ratio f = 1.0MHz V I Input voltage range - ±210 - mv AC-coupled V I-OISE Input voltage noise, 5MHz nv/ Hz Without active termination I I-OISE Input current noise pa/ Hz Without active termination db f = 5.0MHz, without active termination F oise figure R db S = R I = 50Ω, f = 5.0MHz with active termination BW Bandwidth MHz Small signal bandwidth Overall Channel Sym arameter Min Typ Max Units Conditions Gain Whole channel gain db Without active termination, max. gain BW VGA -3dB bandwidth MHz Small signal bandwidth at max. gain SR VGA Slew rate V/µs --- VO VGA Output signal range V RL > 1.0kΩ differentially R OUT Output Impedance Ω f = 5.0MHz, single ended I OUTS Output short-circuit current - ±40 - ma --- V I-OISE Input voltage noise nv/ Hz At max. gain and 5.0MHz IMD HD3 HD2 Intermodulation distortion, two-tone Third harmonic distortion MHz, V OUT = 1.0V, 30dB gain dbc MHz, V OUT = 1.0V, 30dB gain Second harmonic distortion V OUT = 1.0V, 1.0MHz, 30dB gain V OUT = 1.0V, 10MHz, 30dB gain dbc V OUT = 1.0V, 1MHz, 10dB gain V OUT = 1.0V, 10MHz, 10dB gain V OUT = 1.0V, 1MHz, 30dB gain V OUT = 1.0V, 10MHz, 30dB gain dbc V OUT = 1.0V, 1MHz, 10dB gain V OUT = 1.0V, 10MHz, 10dB gain A OUT1dB 1dB compression point dbm V OUT = 1.0V, f= 10MHz, 8dB gain 3

4 Overall Channel Sym arameter Min Typ Max Units Conditions CSTK Crosstalk db G0 and G1 = 1, 30dB gain, 1.0MHz, 1.0V at adjacent channel Δt gd Group delay variation - ±2.0 - ns 2 MHz < f < 50 MHz, Full Gain Range t OLR Overload recovery time ns 8dB Gain, V I = 50mV to 1.0V change, f = 10MHz V DC-OUT DC output level, V I = V --- ote: V I is the voltage at the non-inverting node of the amplifier. Accuracy Sym arameter Min Typ Max Units Conditions G SLOE Gain slope db/v V GSC = 2.5V G MAT Ch. to ch. gain matching - ±0.1 - db V TGC = 0V or 2.0V E GAI Gain error - ±0.8 - db Referenced to best fit db-linear curve, 0.5V < V TGC < 1.7V V OS-OUT Output offset voltage - ±20 - mv Reference to 1.25V Gain Control Interface Sym arameter Min Typ Max Units Conditions V TGC Gain control voltage 0-2 V Linear in db, See gain scaling diagram V GSC Gain slope voltage V About 41dB/V at 2.0V and 33dB/V at 2.5V R GSC Input resistance of GSC kω --- R TGC Input resistance of TGC MΩ Connected to ¾ V GSC td TGC Response time µs 95% full gain change GA Gain Control Table G1, G0 GA Gain (db) 0,0 35 0, ,0 46 1, TGC and GSC Voltage for Gain Scaling Attenuation (db) 0 Maximum Slope Minimum Slope Configurations for Active Feedback R S C C C FB R FB LA A TGC Voltage (V) 4

5 in Configuration in # in ame in # in ame in # in ame in # in ame A1 I 1 A22 AGD A43 GD B20 C A2 I 1 A23 AVDD A44 AGD B21 OUT 4 A3 A 1 A24 AVDD B1 A 1 B22 CM4 A4 A 2 A25 AGD B2 AVDD B23 OUT 4 A5 AVDD A26 OUT 3 B3 AGD B24 A A6 A 2 A27 CM3 B4 I 2 B25 AVDD A7 A 3 A28 OUT 3 B5 I 2 B26 AGD A8 AVDD A29 OUT 2 B6 AGD B27 AVDD A9 A 3 A30 CM2 B7 I 3 B28 AVDD A10 AGD A31 OUT 2 B8 I 3 B29 AGD A11 I 4 A32 OUT 1 B9 A 4 B30 CM1 A12 I 4 A33 AVDD B10 AVDD B31 OUT 1 A13 AGD A34 AVDD B11 A 4 B32 C A14 AGD A35 AGD B12 C B33 C A15 EBC A36 GD B13 GD B34 C A16 AGD A37 VDD B14 DC B35 C A17 GSC A38 VDD B15 AVDD B36 C A18 CM0 A39 GD B16 C B37 C A19 A0 A40 GD B17 A1 B38 C A20 G1 A41 VDD B18 G0 B39 C A21 GD A42 VDD B19 TGC B40 C in Description in ame VDD GD AVDD AGD Description VDD voltage supply Ground Analog supply Analog ground I 1~4 ositive polarity LA input of channel 1~4 I 1~4 egative polarity LA input of channel 1~4 A 1~4 A 1~4 Channel 1~4 LA positive output Channel 1~4 LA negative output OUT 1~4 ositive polarity GA output of channel 1~4 OUT 1~4 egative polarity GA output of channel 1~4 DC EBC GSC DC = 1, power down and enable external biasing, 450kΩ intermal pull down External current biasing Input of gain scaling control for all channels A0, A1 Reserved, should connect to A G0, G1 GA Gain select inputs (G0 = LSB, G1 = MSB) TGC Attenuator control input CM0~4 0.1µF bypass capacitors to ground 5

6 84-Lead BCC+ ackage Outline (B2) 7.00x7.00mm body, 0.80mm height (max), 0.50mm pitch ote: 1. A in 1 identifier must be located in the index area indicated. The in 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A1 A2 b D D2 E E2 e R e T L L1 Dimension (mm) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. o responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http// Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSF-MD3880 B Top View Side View MI OM BSC BSC 0.30 MAX Drawings not to scale. Supertex Doc. #: DSD-84BCC+B2 C D ote 1 (Index Area E/2 x D/2) A1 E A2 A Seating lane 11 x e T 6 10 x e T E2 D2 8 x e T 9 x e T Bottom View e T/2 e T View A View A e R L1 Terminal Tip in A1 Mark L L b B40 A44 A1 B1 View A 0.10 REF Supertex inc Bordeaux Drive, Sunnyvale, CA Tel: