32-Channel High Voltage Amplifier Array
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1 32-Channel High Voltage Amplifier Array Features 32 independent high voltage amplifiers 3 operating voltage 295V output voltage 2.2V/µs typical output slew rate Adjustable output current source limit Adjustable output current sink limit Internal closed loop gain of 72V/V 12MΩ feedback impedance Layout ideal for die applications Applications MEMS (microelectromechanical systems) driver Piezoelectric transducer driver Optical crosspoint switches (using MEMS technology) General Description The Supertex HV256 is a 32-channel, high voltage, amplifier array integrated circuit. It operates on a single high voltage supply, up to 3, and two low voltage supplies, V DD and V NN. The input voltage range is from to 4.96V. The internal closed loop gain is 72V/V, giving an output voltage of 295V when 4.96V is applied. Input voltages of up to 5. can be applied, but will cause the output to saturate. The maximum output voltage swing is 5. below the V PP high voltage supply. The outputs can drive capacitive loads of up to 3pF. The maximum output source and sink current can be adjusted by using two external resistors. An external R SOURCE resistor controls the maximum sourcing current and an external R SINK resistor controls the maximum sinking current. The current limit is approximately 12.5V divided by the external resistor value. The setting is common for all 32 outputs. A low voltage silicon junction diode is made available to help monitor the die temperature. Typical Application Circuit Micro Processor DAC DAC DAC DAC HV High Voltage Op-Amp Array x y y MEMS Array x DAC DAC 3 31 R SOURCE R SINK 3 31 AGND
2 Ordering Information Device 1-Lead MQFP 2.x14.mm body 3.15mm height (max).65mm pitch 3.2mm footprint HV256 HV256FG-G -G indicates package is RoHS compliant ( Green ) Pin Configuration Lead MQFP (FG) (top view) 3 Absolute Maximum Ratings Parameter Value V PP, High voltage supply 31 AV DD, Analog low voltage positive supply 8. DV DD, Digital low voltage positive supply 8. AV NN, Analog low voltage negative supply -7. Product Marking Top Marking HV256FG LLLLLLLLLL YYWW CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin A = Assembler ID = Green Packaging 1-Lead MQFP (FG) DV NN, Digital low voltage negative supply Logic input voltage V to DV DD V SIG, Analog input signal to 6. Storage temperature range -65 C to 15 C Maximum junction temperature 15 C Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Operating Conditions Sym Parameter Min Typ Max Units Conditions V PP High voltage positive supply V --- V DD Low voltage positive supply V --- V NN Low voltage negative supply V --- I PP V PP supply current ma V PP = 3, All = No load I DD V DD supply current ma V DD = 6. to 7.5V I NN V NN supply current ma V NN = -4.5V to -6.5V T J Operating temperature range C --- 2
3 Electrical Characteristics (over operating conditions, unless otherwise specified Sym Parameter Min Typ Max Units Conditions voltage swing - V PP -5. V --- Input voltage range - 5. V --- OS Input voltage offset - - ±5 mv Input referred SR slew rate rise V/µs No load slew rate fall V/µs No load BW -3dB channel bandwidth KHz V PP = 3 A O Open loop gain db --- A V Closed loop gain V/V --- R FB Feedback resistance from to ground MΩ --- C LOAD capacitive load - 3 pf --- I SOURCE sourcing current limiting range µa R SOURCE = 25KΩ I SINK sinking current limiting range µa R SINK = 25KΩ R SOURCE R SINK External resistance range for setting maximum current source External resistance range for setting maximum current sink Temperature Diode KΩ KΩ --- CT DC DC channel to channel crosstalk db --- PSRR Power supply rejection ratio for V PP, V DD, V NN db --- Sym Parameter Min Typ Max Units Conditions PIV Peak inverse voltage V cathode to anode V F Forward diode drop V I F = 1µA, anode to cathode at T A = 25 C I F Forward diode current µa anode to cathode T C V F temperature coefficient mv/ C anode to cathode 3
4 HV256 Block Diagram BYP- BYP- BYP- To internal bus To internal bus To internal bus RSOURCE RSINK Output Current Source Limiting for all HVOUT Output Current Sink Limiting for all HVOUT + 71R - R R - R R - GND R Anode Cathode 4
5 Power Up/Down Issues External Diode Protection The device can be damaged due to improper power up / down sequence. To prevent damage, please follow the acceptable power up / down sequences, and add two external diodes as shown in the diagram on the right. The first diode is a high voltage diode across and, where the anode of the diode is connected to and the cathode of the diode is connected to. Any low current, high voltage diode, such as a 1N44, will be adequate. The second diode is a Schottky diode across and DGND, where the anode of the Schottky diode is connected to, and the cathode is connected to DGND. Any low current Schottky diode such as a 1N5817 will be adequate. Acceptable Power Up Sequences The HV256 can be powered up with any of the following sequences listed below. 1) 2) 3) 4) Inputs and Anode 1) 2) 3) 4) Inputs and Anode 1) & 2) Inputs 3) 4) Anode Acceptable Power Down Sequences The HV256 can be powered down with any of the following sequences listed below. 1) Inputs and Anode 2) 3) 4) 1) Inputs and Anode 2) 3) 4) 1) Anode 2) 3) Inputs 4) & External Diode Protection Connection 1N44 or similar 1N5817 or similar DGND Suggested Power Up/Down Sequence The HV256 needs all power supplies to be fully up and all channels refreshed with V SIG = to force all high voltage outputs to. Before that time, the high voltage outputs may have temporary voltage excursions above or below GND level depending on selected power up sequence. To minimize the excursions: 1. The and power supplies should be applied at the same time (or within a few nanoseconds). Suggested ramp up speed should be 1msec or longer and ramp down to be 1msec or longer. Recommended Power Up/Down Timing 3 VIN HVOUT Gnd +/- V offset X V -5.5V Level at Power Up Before Power Up Sequence Before 6.5V 6.5V -5.5V -5.5V HVOUT -5.5V HVOUT 6.5V 5
6 RSINK / RSOURCE The _BYP, _BYP, and _BYP pins are internal, high impedance current, mirror gate nodes, brought out to mantain stable opamp biasing currents in noisy power supply environments..1uf/ 25V bypass capacitors, added from the _BYP pin to, from _BYP pin to, and from _BYP to, will force the high impedance gate nodes to follow the fluctuation of power lines. The expected voltages at the _BYP, and _BYP pins are typically 1.5 volts from their respectful power supply. The expected voltage at _BYP is typically 3. below V PP. BYP _ Cap.1uF / 25V Current limit BYP_ Set by RSOURCE BYP_ BYP_ Cap.1uF / 25V To internal biasing HVOpamp 31 HVOpamp BYP_ Set by RSINK BYP _ Cap.1uF / 25V Current limit Typical Characteristics I SINK vs R SINK ( = 3, = 6.5V, = 5.5V, TA = 25 O C) I SOURCE vs R SOURCE ( = 3, = 6.5V, = 5.5V, TA = 25 O C) I SINK (µa) I SOURCE (µa) max min 1 max min 25k 15k 25k R SINK (KΩ) 25k 15k 25k R SOURCE (KΩ) 6
7 Typical Characteristics (cont.) Temperature Diode vs Temperature (V PP = 3, V DD = 6.5V, V NN = 5.5V) -5-4 V NN PSRR vs Frequency (V PP = 3, V DD = 6.5V, V NN = 5.5V, T A = 25 O C) V f (mv) max min max min max min -1 O C 25 O C 85 O C V NN PSRR (db) k 1k 1k 1M Frequency 3 1μA 2μA 4μA 6μA 8μA 1μA Diode Biasing Current (µa) 3.5 Input Offset vs and Temperature (V PP = 3, V DD = 6.5V, V NN = 5.5V ) V PP PSRR (db) V PP PSRR vs Frequency (V PP = 3, V DD = 6.5V, V NN = 5.5V, T A = 25 O C) Input Offset (mv) Offset at -1 O C Offset at 25 O C Offset at 85 O C V DD PSRR (db) k 1k 1k 1M Frequency (Hz) V DD PSRR vs Frequency (V PP = 3, V DD = 6.5V, V NN = 5.5V, T A = 25 O C) 1 1 1k 1 1 1M Frequency (Hz) Gain (Volts) Gain vs (V PP = 3, V DD = 6.5V, V NN = 5.5V, T A = -1 O, +25 O, +85 O C ) (Volts) 7
8 Pad Configuration (not drawn to scale) Do Not Bond. Leave Floating. Do Not Bond. For testing only. Anode BYP- BYP- GND GND Cathode RSINK RSOURCE BYP- 31 Do Not Bond. Leave Floating GND GND 8
9 Pad Coordinates Chip size: 1716μm x 583μm Center of die is (,) Pad Name X (μm) Y (μm) Pad Name X (μm) Y (μm) BYP RSOURCE RSINK CATHODE ANODE BYP BYP GND GND Pad Name X (μm) Y (μm) GND GND
10 Pin Description Pin # Function Description Amplifier outputs High voltage positive supply. There are two pads NC No connect. 39 GND Digital ground. There are four pads. 1
11 Pin Description (cont.) Pin # Function Description 4 Analog low voltage negative supply. There are four pads. 41 NC No connect. 42 Analog low voltage positive supply. There are four pads. 43 GND Digital ground. There are four pads. 44 Analog low voltage negative supply. There are four pads. 45 Analog low voltage positive supply. There are four pads NC No connect Amplifier inputs
12 Pin Description (cont.) Pin # Function Description Amplifier inputs NC No connect. 86 GND Digital ground. There are four pads. 87 Analog low voltage positive supply. There are four pads. 88 Analog low voltage negative supply. There are four pads. 89 GND Digital ground. There are four pads. 9 NC No connect. 91 Analog low voltage positive supply. There are four pads. 92 BYP- 93 BYP- A low voltage 1. to 1nF decoupling decoupling capacitor across and BYP- is required. A low voltage 1. to 1nF decoupling decoupling capacitor across and BYP- is required. 94 Analog low voltage negative supply. There are four pads. 95 ANODE Anode side of of a low voltage silicon diode that can be used to monitor die temperature. 96 CATHODE Cathode side of of a low voltage silicon diode that can be used to monitor die temperature. 97 RSINK External resistor from RSINK to sets output current sinking limit. Current limit is approximately 12.5V divided by RSINK resistor value. 98 RSOURCE External resistor from RSOURCE to sets output current sourcing limit. Current limit is approximately 12.5V divided by RSOURCE resistor value. 99 BYP- A low voltage 1. to 1nF decoupling decoupling capacitor across and BYP- is required. 1 High voltage positive supply. There are two pads. 12
13 1-Lead MQFP Package Outline (FG) 2.x14.mm body, 3.15mm height (max),.65mm pitch, 3.2mm footprint HV256 D D1 E θ1 Note 1 (Index Area E1/4 x D1/4) E1 L2 Gauge Plane 1 1 e Top View b L L1 View B θ Seating Plane View B A A2 Seating Plane A1 Side View Note: 1. A Pin 1 identifier must be located in the index area indicated. The Pin 1 identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A1 A2 b D D1 E E1 e L L1 L2 θ θ1 Dimension (mm) MIN 2.5* * 19.8* 16.95* 13.8*.73 O 5 O NOM BSC REF BSC MAX * 2.2* 17.45* 14.2* O 16 O JEDEC Registration MS-22, Variation GC-2, Issue B, Dec * This dimension is not specified in the original JEDEC drawing. The value listed is for reference only. Drawings are not to scale. Supertex Doc. #: DSPD-1MQFPFG, Version E1178. (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. website: http// 28 All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-HV256 D Bordeaux Drive, Sunnyvale, CA 9489 Tel:
14 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Microchip: HV256FG HV256PG
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More informationDimmable, Low Noise, Dual EL Lamp Driver. 100µH Coilcraft LPS MΩ VREG VOUT LX CS 3 12 VDD EL1 2.0MΩ HV861K7-G. REL-Osc COM1 2. RSW-Osc.
Supertex inc. HV86 Features Adjustable output regulation for dimming Lamp fade-in/fade-out capability Low audible noise 80V PP output voltage for higher brightness.v enable input logic high Single cell
More informationSupertex inc. MD0105. Four-Channel High Voltage Protection T/R Switch. Features. General Description. Applications. Typical Application Circuit +130V
Four-Channel High Voltage Protection T/R Switch Features Up to ±30V input voltage protection Low on resistance - 5Ω typical Fast switching speed Four electrically isolated channels No external supplies
More informationSupertex inc. TN2640. N-Channel Enhancement-Mode Vertical DMOS FETs. Features
TN264 Features Low threshold (2.V max.) High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage pplications Logic level
More informationSupertex inc. HV9861A. LED Driver with Average-Mode, Constant Current Control HV9861A. Features. General Description. Applications
Supertex inc. LED Driver with Average-Mode, Constant Current Control Features Fast average current control Programmable constant off-time switching PWM / linear dimming input Output short circuit protection
More informationSupertex inc. TP2540. P-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
Features Low threshold (-2.4V max.) High input impedance Low input capacitance (6pF typical) Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output leakage Applications
More informationSupertex inc. TN0702. N-Channel Enhancement-Mode Vertical DMOS FET. Features
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More informationSupertex inc. TN0106. N-Channel Enhancement-Mode Vertical DMOS FET
TN16 N-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold - 2.V max. High input impedance Low input capacitance - 5pF typical Fast switching speeds Low on-resistance Free from secondary
More informationLow Charge Injection 24-Channel SPST High Voltage Analog Switch with Bleed Resistors. Level Shifters. Latches D LE CLR D LE CLR D LE CLR D LE CLR
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More informationSupertex inc. DN2540. N-Channel Depletion-Mode Vertical DMOS FETs. General Description. Features. Applications. Ordering Information
Supertex inc. DN254 N-Channel Depletion-Mode Vertical DMOS FETs Features High input impedance Low input capacitance Fast switching speeds Low on-resistance Free from secondary breakdown Low input and output
More informationFour-Channel, High Speed, ±65V 750mA Ultrasound Pulser. General Description C2 C3 C4 VSUB. P-Driver. N-Driver. RGND 1 of 4 Channels GREF VNF HV738
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More informationSupertex inc. TP2104. P-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
TP214 Features High input impedance and high gain Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral source-drain diode Free from secondary
More informationSupertex inc. TN2106. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability Integral source-drain diode High input impedance and
More informationSupertex inc. VN10K. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
VN1K N-Channel Enhancement-Mode Vertical DMOS FET Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability
More informationSupertex inc. HV Pin Hotswap, Inrush Current Limiter Controllers (Negative Supply Rail) Features. General Description.
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More informationSupertex inc. TN0604. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
TN64 N-Channel Enhancement-Mode ertical DMOS FET Features Low threshold (1.6 max.) High input impedance Low input capacitance (14pF typical) Fast switching speeds Low on-resistance Free from secondary
More informationSupertex inc. VN0109. N-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
VN19 N-Channel Enhancement-Mode Vertical DMOS FET Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds Excellent thermal stability
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More informationSupertex inc. TP2510. P-Channel Enhancement-Mode Vertical DMOS FET TP5AW. Features. General Description. Applications. Ordering Information
TP251 P-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold (-2.4V max.) High input impedance Low input capacitance (125pF max.) Fast switching speeds Low on-resistance Free from secondary
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TN51 N-Channel Enhancement-Mode Vertical DMOS FET Features Low threshold (.V max.) High input impedance Low input capacitance (15pF max.) Fast switching speeds Low on-resistance Free from secondary breakdown
More informationSupertex inc. VP2206. P-Channel Enhancement-Mode Vertical DMOS FET. Features. General Description. Applications. Ordering Information.
Features Free from secondary breakdown Low power drive requirement Ease of paralleling Low C ISS and fast switching speeds High input impedance and high gain Excellent thermal stability Integral source-to-drain
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Sequential Linear LED Driver Features Minimal component count (base config: + 4 resistors + diode bridge) No magnetics, no capacitors Up to 3W output >5Lm/W using efficient LEDs 85-90% electrical efficiency
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More informationSupertex inc. HV859. High Voltage EL Lamp Driver for Low Noise Applications. Features. General Description. Applications. Typical Application Circuit
High Voltage EL Lamp river for Low Noise Applications Features Patented audible noise reduction Patented lamp aging compensation 0 V PP output voltage for higher brightness Patented output timing for high
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