Supertex inc. HV Channel, 128-Level Amplitude Gray-Shade Display Column Driver. Features. General Description. Applications

Transcription

1 -Channel, 28-Level Amplitude Gray-Shade Display Column Driver Features HVCMOS technology 5.0V CMOS inputs Capable of 28 levels of gray shading Modulation voltage up to +80V 24MHz data throughput rate outputs per device (can be cascaded) Pin-programmable shift direction (DIR) D/A conversion cycle time is 20µs Diodes in output structure allow usage in energy recovery systems Available in 3-sided 64-lead gull wing package Applications Electroluminescent Displays Polycholesteric Displays General Description The is a -channel driver IC for gray shade display use. It is designed to produce varying output voltages between V. This amplitude modulation at the output is facilitated by an external ramp voltage V R. See Theory of Operation for detailed explanation. This device consists of dual 6-bit shift registers, data latches and comparators, and control logic to preform 28 levels of gray shading. There are bits of data inputs. Data is shifted through the shift registers at both edges of the clock, resulting in a data transfer rate of twice that of the shift clock frequency. When the DIR pin is high, CSI/CSO is the input/ output for the chip select pulse. When DIR is low, CSI/CSO is the output/input for the chip select pulse. When the DIR pin is high, it allows the to shift data in the counter-clockwise direction when viewed from the top of the package. When the DIR pin is low, data is shifted in the clockwise direction. The output circuitry allows the energy which is stored in the output capacitance to be returned to V PP through the body diode of the output transistor. Functional Block Diagram V DD V R V PP CSI SC Low Voltage High Voltage LC CC CSO DIR D - D Shift Register Latches Comparator Counter Source Follower Output Buffer I BIAS Control ~ VCTL RCTL C0344

2 Ordering Information Part Number Package Option Packing PG-G 64-Lead PQFP 66/Tray -G denotes a lead (Pb)-free / RoHS compliant package Pin Configuration 64 Absolute Maximum Ratings Parameter Supply voltage, V DD Value -0.5V to +.5V Supply voltage, V PP -0.5V to +90V Logic input levels -0.5V to V DD +0.5V Ground current.5a Operating temperature range Storage temperature range 0 C to +25 C -65 C to +50 C Continuous total power dissipation 2 2.0W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. Notes:. Duty cycle is limited by the total power dissipated in the package. 2. For operation above 25 C ambient derate linearly to 25 C at 20mW/ C. Product Marking Top Marking PG LLLLLLLLLL YYWW CCCCCCCC AAA 64-Lead PQFP (top view) L = Lot Number YY = Year Sealed WW = Week Sealed C = Country of Origin A = Assembler ID = Green Packaging Package may or may not include the following marks: Si or 64-Lead PQFP Typical Thermal Resistance Package 64-Lead PQFP θ ja 4 O C/W Recommended Operating Conditions Sym Parameter Min Typ Max Units V DD Low-voltage digital supply voltage Low-voltage analog supply voltage V V IH High-level input voltage (analog & digital) V DD - - V DD V V IL Low-level input voltage (analog & digital) V V BIAS I PP control circuit bias voltage V V CTL I PP control circuit control voltage V V PP High voltage supply V V R Ramp voltage 0 - V PP -2 V f SC Shift clock operating frequency (at V DD = 5.5V) MHz C0344 2

3 Electrical Characteristics (over recommended operating conditions at T A = 25 C unless otherwise noted) Low Voltage DC Characteristics (Digital) Sym Parameter Min Typ Max Units Conditions I DD V DD supply current ma f SC = 2MHz, f CC = 2MHz I DDQ Quiescent V DD supply current µa All V IN = 0V, V DD = 5.5V I IH High-level input current µa V IH = V DD I IL Low-level input current µa V IL = 0V C IN 2 Input capacitance (D ~ D, LC, SC, CC) pf V IN = 0V, f =.0MHz I OH High-level output current ma V DD = 4.5V, V OH = 0.9V DD I OL Low-level output current ma V DD = 4.5V, V OL = 0.V DD Notes:. All typical values are at V DD = 5.0V. 2. Guaranteed by design. Low Voltage DC Characteristics (Analog) I DD V DD supply current µa f SC = 2MHz, f CC = 2MHz I DDQ Quiescent V DD supply current µa All V IN = 0V, V DD = 5.5V High Voltage Bias Circuit for Output Variation Control I PP V PP supply current for bias circuit ma High Voltage DC Characteristics I AOH I AOL ΔV O High-voltage analog output source current High-voltage analog output sink current Maximum delta voltage between high voltage outputs of the same level See performance curves See performance curves ma ma Depending on external bias circuit, see Table. V PP = 80V. See Test Circuit V PP = 80V, V DD = 4.5V, V AO = 2.0V - - ±0.2 V At all gray levels AC Characteristics (V DD = 5.5V, T A = 25 C) Logic Timing f SC Shift clock operating frequency MHz --- f DIN Data-in frequency MHz --- t SS CSI/CSO pulse to shift clock setup time ns --- t HS CSI/CSO pulse to shift clock hold time ns --- t WA CSI pulse width ns --- t DS Data to shift clock setup time ns --- t DH Data to shift clock hold time ns --- t WD Data-in pulse width ns --- t WLC Load count pulse width ns --- t DLCR Load count to ramp delay µs --- t DRCC 3 Ramp to count clock delay µs --- t DSL Shift clock to load count delay time ns --- C0344 3

4 Logic Timing (cont.) Sym Parameter Min Typ Max Units Conditions t CSC Shift clock cycle time ns --- t WSC Shift clock pulse width ns --- t CCC Count clock cycle time ns --- t WCC Count clock pulse width ns --- V R Timing t CR Cycle time of ramp signal µs --- t RR Ramp rise time µs --- t HR 4 Ramp hold time µs --- t FR Ramp fall time µs C LOAD = nf Notes: 3. Count clock starts counting after 0.4µs min. This is equivalent to a time duration for a linear ramp V R to ramp from 0 to 3.0V, assuming the minimum value of t RR, ramp size time of 2µs for V R = 80V. 4. The maximum ramp hold time may be longer than 5 µs, but the output voltage will droop due to leakage. Table : Schemes to control I PP bias current, typical I PP Option Option 2 V BIAS (V) V CTL (V) R CTL (kω) I PP (ma) V BIAS (V) V CTL (V) R CTL (kω) I PP (ma) - + V CTL VCTL RCTL R CTL - + V BIAS Function Table Function DIR Shift data from to Shift data from to Data In (D - D) Load shift register X X CSI CSO SC LC CC V R H Data Output L L L Data... L Data Output L L L Data... L L L - Load counter X X Pre-defined L L L - Counting/voltage by or 2 X X L L Initiates conversion V - R Notes: L = Low logic level H = High logic level = Low to high transition = Transition of both edges X = Don t care C0344 4

5 Functional Block Diagram L/E Data Latches Latches and Comparators RS F/F See Output Stage Detail GND VR VPP Output Stage VCTL RCTL Dual 6-bit Shift Registers 2 L/E Data Latches Latches and Comparators RS F/F Output Stage 2 3 L/E Data Latches Latches and Comparators RS F/F Output Stage 3 L/E Data Latches Latches and Comparators CC RS F/F Output Stage DIR I/O Buffers SC SC I/O Buffers Shift Clock Buffer Data In Buffers Clear Pulse Generator Count Load Load Count Buffer Counter Reset Counter Count Clock Buffer CSI CSO SC D D LC CC Note: SC = Shift Clock, LC = Load Count, CC = Count Clock, CSI = Chip Select Input, CSO = Chip Select Output *Data rate = 2x the SC frequency Input and Output Equivalent Circuits VDD VDD IN OUT LVGND LVGND Logic Inputs Logic Data Output Output Stage Detail VR V PP C H VCTL RCTL Internal Logic & Bias Circuit Q Q 2 C0344 5

6 Test Circuit High-voltage Analog Output Source Current (I AOH ). For gray shade # ( ). VR VPP = 80V 0V 0V + Logic Output Stage HVOUT +.0kΩ V TST - LVGND HVGND 0kΩ. Set = Low 2. Apply V PP = 80V 3. Apply a step voltage of 0V at V R (slew rate = 4.V/µs) 4. Measure voltage across the.0kω resistor 5. Output source current can be calculated by using V TST /.0KΩ Typical Panel Connections D ~ D DIR = LOW VR, VPP LVGND, HVGND, SC, LC, CC, CSO Display Panel (Example) VR, VPP LVGND, HVGND, SC, LC, CC, CSI DIR = HIGH D ~ D C0344 6

7 Timing Diagrams (a) Basic System Timing t CR VR t RR t HR t FR Chip Select Input (CSI) Load First Device Load Second Device Load Last Device Chip Select Output (CSO) Shift Clock (SC) IN (D - D) Data from Data Bus (See Detailed Timing) Load Count* (LC) t DLCR Count Clock (CC) * will clear to zero with load count. (b) Detailed Device Timing t WA LOADING LAST DEVICE NEXT LOADING CYCLE Chip Select Input (CSI) t HS t SS t CSC t WSC Shift Clock (SC) SC SC2 SC 6 SC SC 6 Data (D-D) SET SET 2 SET 3 SET 3 SET SET SET 3 Load Count (LC) t DS t DH t WD t DSL twlc Count Clock (CC) Count Clock t WCC t CCC Count Clock 28 t DRCC t DLCR VR 0V 3V C0344

8 Gray Shade Decoding Scheme Gray Scale Voltage Shade Number D D6 D5 D4 D3 D2 D ( ) VR Gray Scale Voltage Clock Cycle ( ) Typical Performance Curves 5 Source Output Characteristics 5 Sink Output Characteristics 2 2 I O (milliamperes) 9 6 I O (milliamperes) V GS Volts V GS Volts C0344 8

9 Theory of Operation The has two primary functions: ) Loading data from the data bus and, 2) Gray-shade conversion(converting latched data to output voltages). Since the device was developed initially for flat panel displays, the operation will be described in terms that pertain to that technology. As shown by the Typical Panel Connections, several packages are mounted at the top and bottom of a display panel. Data exists on a -bit bus (adjacent PC board traces) at top and bottom. The D through D inputs of each chip take data from the bus when either a CSI or CSO pulse is present at the chip. These pulses therefore act as a combination CHIP SELECT and LOCATION STROBE. Because of the way the chip pins are sequenced, data on the bus at the bottom of the display panel will be entered into the left-most chip as, 2, etc. up to. The CSI pulse will accomplish this with DIR = High. Loading Data from Data Bus Here is the full data-entry sequence: ) The micro controller puts data on the bus ( bits) 2) To enter the data into the sets of latches on the first chip, the shift clock rises. This positive transition is combined with the CSI pulse and is generated only once to strobe the data into the first set of latches. (These latches eventually send data to the ). The data on the bus then changes, the shift clock falls, and this negative transition is combined with the CSI pulse, which is now propagated internally, to strobe the new data into the next set of latches (which will end up as 2). This internal CSI pulse therefore runs at twice the shift clock rate. 3) When the last set of latches in the first chip has been loaded ( ), the CSI pulse leaves chip and enters chip 2. The exit pin is called CSO and the chip 2 entry pin is CSI. For chips at the top of the panel things are reversed: DIR is low, entry pins are CSO and exit pins are CSI, because the data-into-latches sequence is in descending order, down to. When data has been loaded into all outputs of all chips (top and bottom of the display panel), the load count pin is pulsed. On its rising transition, all output levels are reset to zero and all the data in the input latches is transferred to a like number of comparator latches, (thus leaving the data latches ready to receive new data during the following operations). After the transfer, the load count pin is brought low. This transition begins the events that convert the binary data into a gray-shade level. Gray-shade Conversion ) The COUNT CLOCK is started. An external signal is applied to the COUNT CLOCK pin, causing the counter on each chip to increment from binary to (0 to 2). 2) At the same time, the V R voltage is applied to all chips, via charging transistors, causing the HOLD CAPACITOR (CH) on each output to experience a rise in voltage. 3) The logic control compares the count in the comparator latch to the count clock. The gate voltage of Q and the output voltage will ramp up at the same rate as VR. 4) Once V R has reached the maximum voltage, then all the pixels will be at the final value. (See Gray Scale Voltage.) Output Voltage Variation The output voltage of the is determined by the logic and the ramp voltage V R. It is possible that the output voltage may be coupled to an unacceptable level due to its adjacent outputs through the panel. In order to solve this problem, internal logic (refer to Output Stage Detail) is integrated in the IC to minimize the effect. Two external pins VCTL and RCTL allow the feasibility to control the current flowing through Q2. The VCTL pin is connected to a voltage source and the RCTL pin is connected to ground through a resistor (2.0V and 56KΩ are used for a particular panel). The internal bias circuit will drive the resistor to a voltage level that is equal to the VCTL voltage at steady state through an operational amplifier. The current flowing through Q and Q2 will be limited to VCTL/RCTL. This combination of VCTL and RCTL will reduce the output voltage variation to less than ±0.2V of delta voltage for each gray shade, independent of its adjacent output voltages. 4) The buses may of course be separate, and data can be strobed in on an interleaved basis, etc., but those complications will be left to systems designers. C0344 9

10 Pin Descriptions Pin # Function Description High-voltage outputs HVGND This is ground for the high-voltage (output) section. HVGND and LVGND should be connected together externally. 8 VR High voltage ramp input for charging the output stage hold capacitors (CH). This input can be linear or non-linear as desired. 9 VPP This input biases the output source followers. 20 NC No connect. 2 VDD (analog)* Low-voltage analog supply voltage. 22 CSI Input pin for the chip select pulse (when DIR is high). Output pin for the chip select pulse (when DIR is low). 23 NC No connect. 24 VCTL 25 RCTL 26 SC (shift clock) 2 LVGND 28 DIR 29 VDD (digital)* Voltage supply pin to prevent output voltage from being affected by its adjacent outputs (V CTL = 2.0V for a particular panel). The combination of V CTL and R CTL will reduce the output voltage variation to less than ±0.2V of delta voltage between high voltage outputs of the same level at all gray levels. Current sense resistor to ground to prevent output voltage from being affected by its adjacent outputs (R CTL = 56KΩ for a particular panel). See VCTL function above. Triggers data on both rising and falling edges. This implies that the data rate is always twice the clock rate (data rate = 20MHz if clock rate = 0MHz). This is ground for the logic section. HVGND and LVGND should be connected together externally. When this pin is connected to VDD, input data is shifted in ascending order, i.e., corresponding to to. When connected to LVGND, input data is shifted in descending order, i.e., corresponding to to. Low-voltage digital supply voltage. * Analog VDD and digital VDD may be connected seperately for better noise immunity. C0344 0

11 Pin Descriptions (cont.) Pin # Function Description 30 D 3 D6 D5 33 D4 34 D3 35 D2 36 D 3 NC No connect. Inputs for binary-format parallel data. 38 LVGND This is ground for the logic section. HVGND and LVGND should be connected together externally. 39 NC No connect. 40 LC (Load Count) Input for a pulse whose rising edge causes data from the input latches to enter the comparator latches, and whose falling edge initiates the conversion of this binary data to an output level (D-to-A). Also, the will clear to zero after the load count is initiated. 4 NC No connect. 42 CC (Count Clock) 43 CSO Input to the count clock generator whose increments are compared to the data in the comparator latches. Input pin for the chip select pulse (when DIR is low). Output pin for the chip select pulse (when DIR is high). 44 NC No connect. 45 VPP This input biases the output source followers. 46 NC No connect. 4 VR High-voltage ramp input for charging the output stage hold capacitors (CH).This input can be linear or non-linear as desired. 48 HVGND This is ground for the high-voltage (output) section. HVGND and LVGND should be connected together externally High-voltage outputs C0344

12 64-Lead PQFP (3-Sided) Package Outline (PG) 20.00x4.00mm body, 3.40mm height (max), 0.80mm pitch, 3.90mm footprint L3 64 D D Note (Index Area D/4 x E/4) E E Note 2 b e θ Top View View B A A2 A Side View Seating Plane L L L2 θ View B Gauge Plane Seating Plane Note:. A Pin identifier must be located in the index area indicated. The Pin identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. 2. The leads on this side are trimmed. Symbol A A A2 b D D E E e L L L2 L3 θ θ Dimension (mm) (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the (website: http//) 204 All rights reserved. Unauthorized use or reproduction is prohibited. C0344 MIN O 5 O NOM BSC REF BSC REF 3.5 O - MAX O 6 O Drawings not to scale. Supertex Doc. #: DSPD-64PQFPPG, Version NR Bordeaux Drive, Sunnyvale, CA Tel: