High Speed, Integrated Ultrasound Driver IC +10V OUTPA1. 10nF OUTNA1. 10nF DV DD OUTPA2. 10nF OUTNA2. 10nF 48 AVSS -50V 0V OUTPA3 V SS OUTNA3 +10V

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1 Supertex inc. MD7 High Speed, Integrated Ultrasound Driver IC Features Drives two ultrasound transducer channels Generates five-level waveform Drives high voltage MOSFETs ±.0A source and sink peak current Up to 0MHz output frequency V/ns slew rate ±3.0ns matched delay times Second harmonic is less than -40dB Two separate gate drive voltages.8 to 3.3V CMOS logic interface Applications Medical ultrasound imaging Piezoelectric transducer drivers Non-Destructive Testing (NDT) Metal flaw detection Sonar transmitter General Description The Supertex MD7 is a two-channel, five-level, high voltage and high speed transmitter driver IC. It is designed for medical ultrasound imaging applications, but can also be used for metal flaw detection, Non-Destructive Testing (NDT), and for driving piezoelectric transducers. The MD7 is a two-channel logic controller circuit with low impedance MOSFET gate drivers. There are two sets of control logic inputs, one for channel A and one for channel B. Each channel consists of three pairs of MOSFET gate drivers. These drivers are designed to match the drive requirements of the Supertex TC630. The MD7 drives six TC630s. Each pair consists of an N-channel and a P-channel MOSFET. They are designed to have the same impedance and can provide peak currents of over.0 amps. Typical Application Circuit µF 0.µF 0.µF + 0.µF FB DVDD DGND DVDD DVSS DGND DVDD DGND AVDD 6 DV 30 DD 39 0.µF EN 47 Control Logic SEL 3 & Level 37 POSA / POSA Translator NEGA / NEGA 3 HVENA / POSA 4 HVENA / NEGA CLAMPA V 0.µF 46 VLL MD7 (/ of I/O) 34 OUTPA OUTNA OUTPA 0.µF 0nF 0nF 0nF OUTNA 0nF TC µf µf µf TRANSDUCER 0.µF 48 AVSS -5 µf 0.µF 4 5 AVSS AVSS SUB 44 OUTPA3 V SS 3 OUTNA3 DGND DVSS DVDD DVDD - AGND DVDD DVDD DGND µF Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

2 MD7 Ordering Information Device 48-Lead LQFP 7.00x7.00mm body.60mm height (max) 0.50mm pitch Package Options 48-Lead QFN 7.00x7.00mm body.00mm height (max) 0.50mm pitch Pin Configurations 48 MD7 MD7FG-G MD7K6-G -G indicates package is RoHS compliant ( Green ) Lead LQFP (FG) (top view) 48-Lead QFN (K6) (top view) Package Marking Top Marking Absolute Maximum Ratings Parameter Value V LL logic supply voltage -0.5V to +5.5V AV DD,, positive gate drive supply -0.5V to +5V, positive gate drive supply -0.5V to +5V YYWW MD7FG LLLLLLLLL Bottom Marking CCCCCCCC AAA YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = Green Packaging *May be part of top marking AV SS, DV SS, negative gate drive supply -5V to +0.5V Thermal resistance (θ JA ): 48-Lead LQFP* 48-Lead QFN* 50 C/W 9 C/W Maximum junction temperature +5C Storage temperature -65 C to 50 C Power dissipation.w Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. *.0oz 4-layer 3x4 PCB Operating Supply Voltages and Currents (Over operating conditions unless otherwise specified, AV DD = = =, AV SS = DV SS = -, V LL = 3.3V, T A = 5 C) Sym Parameter Min Typ Max Units Conditions V LL Logic supply V --- AV DD Positive drive bias supply V --- Positive gate drive supply V --- Positive gate drive supply V --- AV SS, DV SS Negative gate drive and bias supply V --- I VLL Logic supply current Package may or may not include the following marks: Si or 48-Lead LQFP (FG) MD7K6 LLLLLLLLL YYWW AAA CCC L = Lot Number YY = Year Sealed WW = Week Sealed A = Assembler ID C = Country of Origin = Green Packaging Package may or may not include the following marks: Si or 48-Lead QFN (K6) I AVDD Positive bias current I AVSS & I DVSS Negative drive and bias supply current I DVDD Positive drive current ma All channels on at 5.0Mhz, no load Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

3 MD7 Operating Supply Voltages and Currents (cont.) (Over operating conditions unless otherwise specified, AV DD = = =, AV SS = DV SS = -, V LL = 3.3V, T A = 5 C) I DVDD Positive drive current ma I AVDDQ V AVDD quiescent current ma I AVSSQ V AVSS quiescent current ma I DVDDQ V DVDD quiescent current µa I DVDDQ V DVDD quiescent current µa I VLLQ Logic supply current ma All channels on at 5.0Mhz, D VDD = 5.0, no load EN = low, All inputs low or high. DC Electrical Characteristics (Over operating conditions unless otherwise specified, AV DD = = =, AV SS = DV SS = -, V LL = 3.3V, T A = 0 to 70 C) P-Channel Gate Driver Outputs Sym Parameter Min Typ Max Units Conditions R SINK Output sink resistance Ω I SINK = 00mA R SOURCE Output source resistance Ω I SOURCE = 00mA I SINK Peak output sink current A --- I SOURCE Peak output source current A --- N-Channel Gate Driver Outputs Sym Parameter Min Typ Max Units Conditions R SINK Output sink resistance Ω I SINK = 00mA R SOURCE Output source resistance Ω I SOURCE = 00mA I SINK Peak output sink current A --- I SOURCE Peak output source current A --- Logic Inputs Sym Parameter Min Typ Max Units Conditions V IH Input logic high voltage 0.8V LL - V LL V --- V IL Input logic low voltage 0-0.V LL V --- I IH Input logic high current µa --- I IL Input logic low current µa --- Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

4 MD7 AC Electrical Characteristics (Over operating conditions unless otherwise specified, AV DD = = =, AV SS = DV SS = -, V LL = 3.3V, T A = 0 to 70 C) Sym Parameter Min Typ Max Units Conditions f OUT Output frequency range MHz --- t PH t PL Propagation delay when output is from low to high Propagation delay when output is from high to low ns No load, see timing diagram ns No load, see timing diagram t r Output rise time ns 000pF load, see timing diagram t f Output fall time ns 000pF load, see timing diagram Δt DM Delay time matching - - ±3.0 ns No load, from device to device Δt DLAY Output jitter ps Standard deviation of t D samples (k) SR Output slew rate - - V/ns Measured at TC630 output HD nd harmonic distortion db with 00Ω load Power-Up Sequence Step Connection Description AV SS, DV SS Negative gate drive supply and substrate bias V LL, AV DD, & Logic supply, positive gate drive supply and bias Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

5 MD7 Truth Table for Channels A and B (For SEL = L) Logic Control Inputs to Output to Output 3 to 3 Output SEL EN HVEN/ POS HVEN/ NEG Clamp POS/ POS NEG/ NEG P N P N P3 N3 ON ON ON ON OFF OFF ON ON OFF OFF OFF OFF OFF OFF OFF ON ON OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON ON OFF ON OFF OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF X X X X X OFF OFF OFF Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

6 MD7 Truth Table for Channels A and B (For SEL = H) SEL EN Clamp Logic Control Inputs to Output to Output 3 to 3 Output HVEN/ POS HVEN/ NEG POS/ POS NEG/ NEG OFF OFF P N P N P3 N OFF ON ON OFF OFF OFF OFF ON ON OFF OFF OFF ON ON OFF OFF ON OFF 0 0 ON ON OFF OFF OFF ON ON OFF ON OFF OFF 0 0 ON ON OFF OFF 0 0 OFF ON 0 0 ON OFF ON ON OFF 0 ON ON OFF OFF OFF ON ON OFF OFF OFF ON 0 0 ON ON OFF OFF 0 0 OFF ON 0 0 ON OFF OFF ON ON 0 ON ON OFF OFF 0 0 OFF ON 0 0 ON OFF ON OFF ON 0 ON ON 0 0 OFF OFF 0 OFF ON 0 ON OFF ON ON ON ON ON 0 X X X X X OFF OFF OFF OFF OFF Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

7 MD7 Test Circuit for Channel A +0 + AVDD Out-PA 0nF GPA3 PA A + DVDD + DVDD +3.3V VLL Out-NA 0nF GNA3 NA -0 R LOAD 00 EN POSA/POSA NEGA/NEGA HVENA/POSA HVENA/NEGA Channel A Control Logic and Level Translation Out-PA Out-NA 0nF 0nF GPA3 GNA3 PA NA +5 CLAMP A -5 SEL AGND 3 DGND - AVSS DV SS Out-PA3 GPA3 PA3 DVSS Out-NA3 GNA3 NA3 3 Timing Diagram / of MD7 3x TC630 V LL HVENA / POSA HVENA / NEGA V LL POSA / POSA V LL NEGA / NEGA V LL f OUT A t r, rise time from 0.9 to 0.9 t f, fall time from 0.9 to 0.9 t r, rise time from 0.9 to 0.9 t f, fall time from 0.9 to V IN 50% 50% t PH t PL OUT 0% t r 90% 90% t f 0% Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

8 MD7 Block Diagram +0.0μF 0nF AV DD 0nF -0.0μF +0.0μF Piezoelectric Transducer B 0nF POSA / POSA NEGA / NEGA HVENA / POSA HVENA / NEGA CLAMPA 0nF -0.0μF V SS VLL SEL EN Control Logic and Level Translator +0.0μF 0nF POSB / POSB NEGB / NEGB 0nF -0.0μF HVENB / POSB +0 HVENB / NEGB CLAMPB 0nF.0μF Piezoelectric Transducer B 0nF -0 AVSS.0μF DVSS AGND DGND V SS Supertex MD7 Supertex TC630 Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

9 MD7 Pin Description (48-Lead LQFP & 48-Lead QFN) Pin # Name Description POSA / POSA Logic input control for channel A. When SEL = L, the pin is POSA. When SEL = H, the pin is POSA. NEGA / NEGA Logic input control for channel A. When SEL = L, the pin is NEGA. When SEL = H, the pin is NEGA. 3 HVENA / POSA Logic input control for channel A. When SEL= L, the pin is HVENA. When SEL = H, the pin is POSA. 4 HVENA / NEGA Logic input control for channel A. When SEL = L, the pin is HVENA. When SEL = H, the pin is NEGA. 5 CLAMPA Used with SEL = H. Logic input control for OUT-PA3 and OUT-NA3. Connect to ground when SEL = L. 6 AV DD Supplies analog circuitry portion of the gate driver. Should be at the same potential as. 7 AGND Analog Ground. 8 CLAMPB Used with SEL = H. Logic input control for OUT-PB3 and OUT-NB3. Connect to ground when SEL = L. 9 HVENB / NEGB Logic input control for channel B. When SEL = L, the pin is HVENB. When SEL = H, the pin is NEGB. 0 HVENB / POSB Logic input control for channel B. When SEL = L, the pin is HVENB. When SEL = H, the pin is POSB. NEGB / NEGB Logic input control for channel B. When SEL = L, the pin is NEGB. When SEL = H, the pin is NEGB. POSB / POSB Logic input control for channel B. When SEL = L, the pin is POSB. When SEL = H, the pin is POSB. 3 SEL Logic input select. See truth tables for SEL = L and SEL = H. 4 Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected 5 AVSS to the IC substrate. They are required to connect to the most negative potential of voltage supplies. 6 DVSS Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and the main Output stage. Should be at the same potential as AVSS. 7 OUT-PB3 Output P-Channel gate driver for channel B 8 DGND Digital Ground. 9 output stage for OUT-PA, OUT-NA, OUT-NA3, OUT-PB, OUT-NB, and OUT-NB3. hould be at the same potential as AV DD. 0 Out-PB Output P-Channel gate driver for channel B output stage for OUT-PA, OUT-NA, OUT-PB, and OUT-NB. Can be at a different potential than. Out-PB Output P-Channel gate driver for channel B 3 N/C No connect. 4 Out-NB Output N-Channel gate driver for channel B 5 output stage for OUT-PA, OUT-NA, OUT-PB, and OUT-NB. Can be at a different potential than. Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

10 MD7 Pin Description (48-Lead LQFP & 48-Lead QFN) (cont.) Pin # Name Description 6 DGND Digital Ground. 7 Out-NB Output N-Channel gate driver for channel B 8 output stage for OUT-PA, OUT-NA, OUT-NA3, OUT-PB, OUT-NB, and OUT-NB3. Should be at the same potential as AV DD. 9 Out-NB3 Output N-Channel gate driver for channel B 30 DGND Digital Ground. 3 output stage for OUT-PA, OUT-NA, OUT-NA3, OUT-PB, OUT-NB, and OUT-NB3. Should be at the same potential as AV DD. 3 OUT-NA3 Output N-Channel gate drivers for channel A. 33 output stage for OUT-PA, OUT-NA, OUT-NA3, OUT-PB, OUT-NB, and OUT-NB3. Should be at the same potential as AV DD. 34 Out-NA Output N-Channel gate drivers for channel A. 35 DGND Digital Ground. 36 output stage for OUT-PA, OUT-NA, OUT-PB, and OUT-NB. Can be at a different potential than. 37 Out-NA Output N-Channel gate drivers for channel A. 38 N/C No connect. 39 Out-PA Output P-Channel gate drivers for channel A 40 output stage for OUT-PA, OUT-NA, OUT-PB, and OUT-NB. Can be at a different potential than. 4 OUT-PA Output P-Channel gate drivers for channel A 4 output stage for OUT-PA, OUT-NA, OUT-NA3, OUT-PB, OUT-NB, and OUT-NB3. Should be at the same potential as AV DD. 43 DGND Digital Ground. 44 Out-PA3 Output P-Channel gate drivers for channel A 45 DVSS Gate drive supply voltage for OUT-PA3 and OUT-PB3. Supplies digital circuitry portion and the main output stage. Should be at the same potential as AVSS. 46 VLL Logic supply voltage. 47 EN Logic input enable control. When EN = L, all P-channel output drivers are high and all N- channel output drivers are low. 48 AVSS Negative driver supply for OUT-PA3, OUT-PB3 and bias circuits. They are also connected to the IC substrate. They are required to connect to the most negative potential of voltage supplies. Center Pad AVSS For the QFN package, the center pad is at AVSS potential. It should be externally connected to AVSS. Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

11 MD7 48-Lead LQFP Package Outline (FG) 7.00x7.00mm body,.60mm height (max), 0.50mm pitch D D E Note (Index Area D/4 x E/4) E 48 b e Top View View B L Gauge Plane A A Seating Plane L L θ Seating Plane A Side View View B Note:. A Pin identifier must be located in the index area indicated. The Pin identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator. Symbol A A A b D D E E e L L L θ Dimension (mm) MIN.40* * 6.80* 8.80* 6.80* O NOM BSC REF BSC 3.5 O MAX * 7.0* 9.0* 7.0* O JEDEC Registration MS-06, Variation BBC, Issue D, Jan. 00. * This dimension is not specified in the JEDEC drawing. Drawings are not to scale. Supertex Doc. #: DSPD-48LQFPFG Version, D Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel:

12 MD7 48-Lead QFN Package Outline (K6) 7.00x7.00mm body,.00mm height (max), 0.50mm pitch 48 D D 48 Note (Index Area D/ x E/) Note (Index Area D/ x E/) e E E b Top View Bottom View View B θ Note 3 A A Side View A3 Seating Plane Note L View B L Notes:. A Pin identifier must be located in the index area indicated. The Pin identifier can be: a molded mark/identifier; an embedded metal marker; or a printed indicator.. Depending on the method of manufacturing, a maximum of 0.5mm pullback (L) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol A A A3 b D D E E e L L θ MIN * * O Dimension NOM (mm) REF BSC - - MAX * * O JEDEC Registration MO-0, Variation VKKD-6, Issue K, June 006. * This dimension is not specified in the JEDEC drawing. This dimension differs from the JEDEC drawing. Drawings are not to scale. Supertex Doc.#: DSPD-48QFNK67X7P050, Version C (The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to Supertex inc. does not recommend the use of its products in life support applications, and will not knowingly sell them for use in such applications unless it receives an adequate product liability indemnification insurance agreement. Supertex inc. does not assume responsibility for use of devices described, and limits its liability to the replacement of the devices determined defective due to workmanship. No responsibility is assumed for possible omissions and inaccuracies. Circuitry and specifications are subject to change without notice. For the latest product specifications refer to the Supertex inc. (website: http// 0 Supertex inc. All rights reserved. Unauthorized use or reproduction is prohibited. Doc.# DSFP-MD7 B08 Supertex inc. 35 Bordeaux Drive, Sunnyvale, CA Tel: