High Speed Quad MOSFET Driver

Transcription

1 High Speed Quad MOSFET Driver Features General Description 6ns rise and fall time 2A peak output source/sink current.2v to 5V input CMOS compatible ±5V to ±2V supply voltage operation Smart Logic threshold Low jitter design Quad matched channels Drives two N and two Pchannel MOSFETs Outputs can swing below ground Builtin level translator for negative gate bias Userdefi ned damping for returntozero application Low inductance quad fl at nolead package Thermallyenhanced package Applications Ultrasound PN code transmitter Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation High speed level translator High voltage bipolar pulser Typical Application Circuit 3.3V CMOS Logic Inputs +0V 0.22 F OE IN A INB INC LT +0V OUT A 3 The Supertex MD82 is a highspeed quad MOSFET driver. It is designed to drive two N and two Pchannel high voltage DMOS FETs for medical ultrasound applications but may be used in any application that needs a high output current for a capacitive load. The input stage of the MD82 is a highspeed level translator that is able to operate from logic input signals of.2 to 5.0 volt amplitude. An adaptive threshold circuit is used to set the level translator threshold to the average of the input logic 0 and logic levels. The level translator uses a proprietary circuit which provides DC coupling together with highspeed operation. The output stage of the MD82 has separate power connections enabling the output signal L and H levels to be chosen independently from the driver supply voltages. As an example the input logic levels may be 0V and.8v the control logic may be powered by +5V and 5V and the output L and H levels may be varied anywhere over the range of 5V to +5V. The output stage is capable of peak currents of up to ±2 amps depending on the supply voltages used and load capacitance. The OE pin serves a dual purpose. First its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly when OE is low the outputs are disabled with the A and C outputs high and the B and D outputs low. This assists in properly precharging the coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS. A builtin level shifter provides PMOS gate negative bias drive. This enables the userdefi ned damping control to generate returntozero bipolar output pulses. 0nF +00V 0nF 2 00V OUTB OUTG OUTC 0.7 F 0 9 2K Supertex TC6320 F F 6 IND OUTD 8 GND V 0nF Supertex MD F Supertex TC2320

2 Ordering Information Device Package Option 6lead xx0.9 QFN MD82 MD82K6G G indicates package is RoHS compliant ( Green ) Absolute Maximum Ratings Parameter Value Logic Supply Voltage 0.5V to +3.5V Output High Supply Voltage 0.5V to +0.5V Output Low Supply Voltage 0.5V to +0.5V Vss Low Side Supply Voltage 7V to +0.5V Negative Supply Voltage 3.5V to +0.5V Logic Input Levels 0.5V to +7V Maximum Junction Temperature +25 C Storage Temperature 65 C to 50 C Soldering Temperature 235 C Package Power Dissipation 2.2W Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. 6Lead QFN (K6) Pin Configuration 6 3 MD Top View 2 9 Pin Description Pin # Function Description IN B Logic input. Controls OUT B when OE is high.. 2 Supply voltage for Nchannel output stage. 3 GND Device ground. Supply voltage the auxiliary gate drive. 5 IN C Logic input. Controls OUT C when OE is high. 6 IN D Logic input. Controls OUT D when OE is high. 7 Supply voltage for lowside analog level shifter and gate drive circuit. 8 OUT D 9 OUT C 0 OUT G Auxiliary output driver. Supply voltage for Pchannel output stage 2 OUT B 3 OUT A Supply voltage for highside analog level shifter and gate drive circuit. 5 IN A Logic input. Controls OUT A when OE is high. 6 OE Output enable logic input. Note: Thermal pad and pin # must be connected externally. 2

3 DC Electrical Characteristics ( = = 2V = = GND = 0V = 2V V OE = 3.3V T J = 25 O C) Symbol Parameter Min Typ Max Units Conditions Logic supply voltage.5 3 V Low side supply voltage V Output high supply voltage +2 V Output low supply voltage 2 V Negative supply voltage 3 2 V May connect to if OUT G not used I DDQ quiescent current.5 ma I HQ quiescent current 0 µa No input transitions OE = I NEGQ quiescent current 0 µa I DD average current 7.0 ma I H average current 22 ma One channel on at 5.0Mhz No load I NEG average current.5 ma V V IH Input logic voltage high OE V V IL Input logic voltage low V I IH Input logic current high.0 µa For logic inputs IN A IN B IN C and IN D I IL Input logic current low.0 µa V IH OE Input logic voltage high.2 5 V V IL OE Input logic voltage low V For logic input OE R IN Input logic impedance to GND KΩ C IN Logic input capacitance 5 0 pf Outputs ( = = 2V = = GND = 0V = 2V V OE = 3.3V T J = 25 O C) Symbol Parameter Min Typ Max Units Conditions R SINK Output sink resistance 2.5 Ω I SINK = 50mA R SOURCE Output source resistance 2.5 Ω I SOURCE = 50mA I SINK Peak output sink current 2.0 A I SOURCE Peak output source current 2.0 A 3

4 AC Electrical Characteristics ( = = 2V = = GND = 0V = 2V V OE = 3.3V T J = 25 O C) Symbol Parameter Min Typ Max Units Conditions t irf Input or OE rise & fall time 0 ns Logic input edge speed requirement t PLH Propagation delay when output is from low to high 7 ns Propagation delay when output is t PHL 7 ns from high to low t C LOAD = 000pF see timing diagram POE Propagation delay OE to output 9 ns Input signal rise/fall time 2ns t PCG Propagation delay IN C to OUT G 28 ns t r Output rise time 6 ns t f Output fall time 6 ns l t r t f l Rise and fall time matching.0 ns l t PLH t PHL l Propagation low to high and high to low matching.0 ns for each channel t dm Propagation delay matching ±2.0 ns Device to device delay match Logic Truth Table Logic Inputs Output OE IN A IN B OUT A OUT B H L L H L H H H L H H H L X X OE IN C IN D OUT C OUT G OUT D H L L H L H H H L H H H L X X

5 Application Information For proper operation of the MD82 low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The IN A IN B IN C IN D and OE pins should be connected to a logic source with a swing of GND to V CC where V CC is.2 to 5.0 volts. When input logic(s) is high output(s) will swing to and when input(s) logic is low output(s) will swing to. All inputs must be kept low until the device is powered up. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD82 is capable of operating up to 00MHz with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads the bypass capacitors should be as close to the chip pins as possible. Unless the load specifi cally requires bipolar drive the and pins should have low inductance feedthrough connections directly to a ground plane. If these voltages are not zero then they need bypass capacitors in a manner similar to the positive power supplies. The power connection should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. Output drivers OUT A and OUT C drive the gate of an external Pchannel MOSFET while output drivers OUT B and OUT D drive the gate of an external Nchannel MOSFET and they all swing from to. The auxiliary output drive OUT G swings from to and drives the gate of an external Pchannel MOSFET via a 2KΩ series resistor. The voltages of and decide the output signal levels. These two pins can draw fast transient currents of up to 2A so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to.0µf may be appropriate with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths current loop area and using suffi cient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will reduce the output voltage slew rate at the terminals of a capacitive load. The OE pin sets the threshold level of logic for inputs (V OE + V GND ) / 2. When OE is low OUT A and OUT C are at. OUT B and OUT D are at. Auxiliary output OUT G is at regardless of the inputs IN A or IN B. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to.2v even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. Best timing performance is obtained for OUT C when the voltage of ( ) = ( ). 5

6 6Lead QFN Package Outline (K6) D A Datum A or B INDEX AREA (D/2 xe/2) D/2 B l 2x aa a C E/2 E Terminal Tip 5 e/2 e Chamfer/Radius N N NX ccc C 0.08 C A A aaa C 2x TOP VIEW SIDE VIEW D2 D2/2 A3 SEATING PLANE C Symbol Min Height Dimensions Nom D BSC. 0 E BSC. 0 e 0.65 Max D E Tolerance of Form & Position aaa 0.5 bbb 0.0 ccc 0.0 ddd 0.05 Issue A b l X N l E2/ 2 A e B E2 A A ref L INDEX AREA (D/2 xe/2) SEE DETAIL B N N A BTM VIEW NXb bbb C A B ddd C Issue AA A Bottom ID Dimensions BB CC DD Notes:. Dimensioning and tolerancing conform to ASME Y.5m All dimensions are in millimeters all angles are in degrees ( O ). 3. The terminal # identifier and terminal numbering convention shall conform to JEDEC publication 95 SPP002. Details of terminal # identifier are optional but must be located within the zone indicated. The terminal #identifier may be either a mold or marked feature.. Depending on the method of lead termination at the edge of the package pull back (L) may be present. L minus L to be equal to or greater than 0.33mm. 5. Dimension B applies to metallized terminal and is measured between 0.5mm and 0.30mm from the terminal tip. If the terminal has the optional radius on the other end of the terminal the dimension B should not be measured in that radius area. (The package drawing(s) in this data sheet may not refl ect the most current specifi cations. For the latest package outline information go to Doc.# DSFPMD82 NR2206 6