SC1101. Asynchronous Voltage Mode PWM Controller. POWER MANAGEMENT Description. Features. Applications. Typical Application Circuit

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1 Description The SC11 is a versatile, low-cost, voltage-mode PWM controller designed for low output voltage DC/DC power supply applications. A simple, fixed-voltage buck regulator can be implemented using the SC11 with a minimum of external components. Internal level shift and drive circuitry eliminates the need for an expensive p-channel, high-side switch. The small device footprint allows for compact circuit design. SC11 features include a temperature compensated voltage reference, triangle wave oscillator, current limit comparator, frequency shift over-current protection, and an internally compensated error amplifier. Pulse by pulse current limiting is implemented by sensing the differential voltage across an external resistor, or an appropriately sized PC board trace. SC11 Asynchronous oltage Mode PWM Controller Features Low cost / small size Switch mode efficiency up to 9% 1% reference voltage accuracy Over current protection 00mA output drive SO- package Applications Pentium P Core Supply Low Cost Microprocessor Supplies Peripheral Card Supplies Industrial Power Supplies High Density DC/DC Conversion The SC11 operates at a fixed frequency of 200kHz, providing an optimum compromise between efficiency, external component size, and cost. Typical Application Circuit Q1 IRLR L1 uh R 0.0 out = A C1 C2 /6. C /6. D2 MBRDL C C9 C C11 R6 76. *see note R R1 R2 R 1 CC U1 SC11 C R 2.2 C C CS(-) CS() FB BST 7 6 P C7 * NOTE: R6 = R7 x (out/1.2-1) rounded to nearest 1%value Revision: May 2, 200 1

2 Absolute Maximum Ratings Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Maximum Units Input oltage Electrical Characteristics CC to -0. to 7 Ground Differential P to ± 1 Boost Input oltage Operating Ambient Temperature Range T MB Storage Temperature Range BST to -0. to 1 A to 70 T STG to 12 0 C - C Maximum Junction Temperature T J 12 C Lead Temperature (Soldering) Sec. T EAD Thermal Thermal Resistance Junction to Ambient Resistance Junction to Case L 00 θ JA 6 Unless specified: CC =.7 to.2, = P = 0, O = 2., T A = 2 C, BST = 12. Per test circuit, unless otherwise specified. C 1 C/ W θ JC 0 C/ W Parameter Symbol Conditions Min Typ Max Units Reference EF Feedback Bias Current R.2 Quiescent Current I Q Current into Over 0 to 12 C Temp. range I FB. 0 CC pin ua. 0 ma Load Regulation I O = 1A to A % Line Regulation I O = A 0. % C urrent Limit Threshold CS() to CS(-) m Oscillator Frequency khz Oscillator Frequency Shift FB < / 2 0 khz REF Max Duty Cycle 90 9 % Sink/Source Current I O BST - =. / ULO Threshold LO - P = 2 00 U. Note: (1) This device is ESD sensitive. Use of standard ESD handling precautions is required. ma 200 Semtech Corp. 2

3 Pin Configuration Top iew CC 1 CS(-) 2 7 FB CS() P 6 BST ( Lead Plastic SOIC) Ordering Information 1) D evice SC11CS.TR (2) S C11CSTRT ( Packag e SO- Temp Range ( T ) J 0 to 12 C Notes: (1) Only available in tape and reel packaging. A reel contains 200 devices. (2) Lead free product. This product is fully WEEE and RoHS compliant. Pin Descriptions Pin Number Pin Name Pin Function 1 CC Device input voltage. 2 C S(-) Current sense input (Negative). C S( ) Current sense input (Positive). P Device power ground. D H High side driver output. 6 BST High side driver (Boost). C C 7 F B Error amplifier input (-). G ND Signal ground. Block Diagram 200 Semtech Corp.

4 Applications Information Layout Guidelines Careful attention to layout requirements are necessary for successful implementation of the SC11 PWM controller. High currents switching at 200kHz are present in the application and their effect on ground plane voltage differentials must be understood and minimized. 1). The high power parts of the circuit should be laid out first. A ground plane should be used, the number and position of ground plane interruptions should be such as to not unnecessarily compromise ground plane integrity. Isolated or semi-isolated areas of the ground plane may be deliberately introduced to constrain ground currents to particular areas, for example the input capacitor and bottom Schottky ground. 2). The loop formed by the Input Capacitor(s) (Cin), the Top FET (Q1) and the Schottky (D1) must be kept as small as possible. This loop contains all the high current, fast transition switching. Connections should be as wide and as short as possible to minimize loop inductance. Minimizing this loop area will reduce EMI, lower ground injection currents, resulting in electrically cleaner grounds for the rest of the system and minimize source ringing, resulting in more reliable gate switching signals. ). The connection between the junction of Q1, D1 and the output inductor should be a wide trace or copper region. It should be as short as practical. Since this connection has fast voltage transitions, keeping this connection short will minimize EMI. The connection between the output inductor and the sense resistor should be a wide trace or copper area, there are no fast voltage or current transitions in this connection and length is not so important, however adding unnecessary impedance will reduce efficiency. ) The Output Capacitor(s) (Cout) should be located as close to the load as possible, fast transient load currents are supplied by Cout only, and connections between Cout and the load must be short, wide copper areas to minimize inductance and resistance. ) The SC11 is best placed over an isolated ground plane area. and P should be returned to this isolated ground. This isolated ground area should be connected to the main ground by a trace that runs from the pin to the ground side of (one of) the output capacitor(s). If this is not possible, the pin may be connected to the ground path between the Output Capacitor(s) and the Cin, Q1, D1 loop. Under no circumstances should be returned to a ground inside the Cin, Q1, D1 loop. 6) cc for the SC11 should be supplied from the supply through a Ω resistor, the cc pin should be decoupled directly to by a µf ceramic capacitor, trace lengths should be as short as possible. 7) The Current Sense resistor and the divider across it should form as small a loop as possible, the traces running back to CS() and CS(-) on the SC11 should run parallel and close to each other. ) To minimize noise pickup at the sensitive FB pin, the feedback resistors should both be close to the SC11 with the bottom resistor (Rb) returned to ground at the pin. Under oltage Lockout The under voltage lockout circuit of the SC11 assures that the high-side MOSFET driver outputs remain in the off state whenever the supply voltage drops below set parameters. Lockout occurs if CC falls below.. Normal operation resumes once CC rises above Semtech Corp.

5 Applications Information (Cont.) Layout diagram for the SC11 O = REF (1 Ra/Rb) 12 IN uf 0.001uF 1 2 SC11CS CC CS(-) FB 7 Rb CS() BST 6 P Q1 D1 Cin uh Cout out Heavy lines indicate high current paths. Ra Application Circuit to A (Bootstrapped) D1 LL2 C7 Q1 IRLR L1 uh R 0.0 C1 C2 /6. C /6. D2 MBRDL C C9 C C11 R6 76. *see note R7 127 out = A R1 R2 R 1 CC U1 SC11 C R 2.2 C C CS(-) CS() FB BST 7 6 P * NOTE: R6 = R7 x (out/1.2-1) rounded to nearest 1%value 200 Semtech Corp.

6 Typical Characteristics Error Amplifier, Gain and Phase Load Regulation IN = PIN Descriptions Gain (db) Gain Phase E0 E.0E 0.0E E6.0E6 Frequency (Hz) Phase (deg) % 0.% 0.6% 0.% 0.2% 0.0% -0.2% -0.% -0.6% -0.% -% Output Current, (A) Line Regulation O = 2.; I O = A Efficiency IN = 2.0% 1.% % 0.% 0.0% -0.% -% -1.% -2.0% Input oltage, () 0% 9% 90% % 0% 7% 70% 6% 60% Output Current, (A) Output Ripple oltage IN = ; O =.; I O = A 200 Semtech Corp. 6

7 Outline Drawing - SO- 2X E/2 ccc C 2X N/2 TIPS aaa C SEATING PLANE C N A 1 2 D e D E1 E e/2 B A2 A A1 bxn bbb C A-B D DIMENSIONS INCHES MILLIMETERS DIM MIN NOM MAX MIN NOM MAX A A A b c D E E.26 BSC 6.00 BSC e.00 BSC 1.27 BSC h L L1 (.01) () N aaa.00 0 bbb ccc GAGE PLANE H h h c SIDE IEW SEE DETAIL A 0.2 L (L1) DETAIL A 01 NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H-. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS.. REFERENCE JEDEC STD MS-012, ARIATION AA. Minimum Land Pattern - SO- X DIMENSIONS DIM INCHES MILLIMETERS C (.20) (.20) (C) G Z G P X Y Y Z P Contact Information NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET. 2. REFERENCE IPC-SM-72A, RLP NO. 00A. Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 9012 Phone: (0) FAX (0) Semtech Corp. 7