SC2677. Dual Synchronous Voltage Mode Controller with Current Sharing Circuitry. POWER MANAGEMENT Description. Features.

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1 POWER MNGEMENT Description SC26 Dual Synchronous oltage Mode Controller with Sharing Circuitry Features The SC26 is a versatile 2 phase, synchronous, voltage mode PWM controller that may be used in two distinct ways. First, the SC26 is ideal for applications where point of use output power exceeds any single input power budget. lternatively, the SC26 can be used as a dual switcher. The SC26 features a temperature compensated voltage reference, an under voltage lockout over current protection and internal level-shifted, highside drive circuitry. In current sharing configuration, the SC26 can produce a single output voltage from two separate voltage sources (which can be different voltage levels) while maintaining current sharing between the channels. sharing is programmable to allow loading each input supply as required by the application. In dual switcher configuration, two feedback paths are provided for independent control of the separate outputs. The device will provide a regulated output from flexibly configured inputs (3.3,, 12), provided is present for CC. The phasing between the two switchers is adjustable to minimize the input and output ripple. Simplified pplication Schematic 300kHz to 1MHz externally programmable frequency operation Soft Start and Enable function Power Good output provided Under voltage short circuit protection Phase-shifted switchers minimize ripple High efficiency operation, >90% Programmable output(s) as low as 0. Industrial temperature range TSSOP- package Bias voltage as low as 4. djustable phase shift between channels Two Phase, Sharing Controller Flexible, same or separate IN Programmable current sharing Thermal distribution via multi-phase output pplications Graphics cards Peripheral add-in card Dual-Phase power supply Power supplies requiring two outputs + M1 L1 1 2 out1 +12 C1 C3 M2 C2 PWRGD ENBLE R2 R1 R3 C R4 C4 R U1 19 PWRGD REF FREQ CC SS/EN 4 1 +IN2 PHSING IN1 COMP1 BST1 SC26 -IN2 COMP2 BST DH2 DH DL2 DL P BSTC R C6 R8 R6 0R0 C R10 C8 R11 R L2 1 2 out2 M3 C9 M4 C10 Revision: NO. 1, 04 1

2 POWER MNGEMENT bsolute Maximum Rating Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied. Parameter Symbol Limits Units CC to IN to 1 P to ± 1 BST1, BST2 to to BSTC to to -IN1, +/-IN2 to COMP1, COMP2 to DH1, DH2 to to DL1, DL2 to to BSTC PWRGD to Electrical Characteristics Unless Specified: CC = 4. to.2, = P = 0, FB = O, T J = 2 C, BSTC = BST = 12 1) - 3 peak (0nS) CC 0. 3 ( + PHSING SS/EN to to Thermal Thermal Operating Operating Storage Resistance Junction to Case Resistance Junction to mbient θ JC 1 C/ W θ J 90 C/ W mbient Temperature Range T 0 to 0 C Junction Temperature Range T J 0 to 12 C Temperature Range Lead Temperature (Soldering) 10 sec T ED T STG 6 to +10 L 00 - C 3 C Parameter Conditions Min Typ Max Units Output oltage OUT = B Supply oltage Supply ULO ULO Hysteresis CC.49 F CC. CC = 10 m Ramp up Threshol d 2.84 CC 00 1 m Reference 0. Reference Load Regulation REF source 10u ~ 100u 0. 2 % Reference Output Gain (Gm) Line Regulation Line Regulation (Error mplifier) < C C < 1 0. % < I N < 1 0. % COMP pin source 100u 4 6 m/ Bias Offset (Slave Error mplifier) m Max (Error mplifier) Source 0 20 u Sink u Input Bias -IN1, +IN2, -IN2 2 µ Short Circuit Protection Threshold 4 6 % Oscillator Frequency Range khz 04 Semtech Corp. 2

3 POWER MNGEMENT Electrical Characteristics (Cont.) Unless Specified: CC = 4. to.2, = P = 0, FB = O, T J = 2 C, BSTC = BST = 12 Parameter Conditions Min Typ Max Units Oscillator Frequency R SET = 2.kohm khz Oscillator Max Duty Cycle F OSC = 00kHz % Phasing of DH2 and DL1 = C PHSING DH Sink DH Sink DH Source DH Source DL Sink DL Sink DL Source DL Source DH - P = DH - P = BSTH - DH = BSTH - DH = DL - PGNG = DL - P = BSTL - DL = BSTL - DL = Dead Time Note ns 2) S oft Start Charge Soft Soft Start Enable Start End 2) S oft Start Transition Threshold ( 0 ( ynchronous mod e µ 0% duty cycle 400 m 100% duty cycle 82 m S 1.22 Power Good Threshold OUT r amping up 83% 88% 93% OUT Power Good Pull Down Sink = 2m 0. 4 NOTES: (1) Measured from 0% to 0% pulse amplitude. (2) The soft start pin sources 0µ to an external capacitor. The converter operates in synchronous mode above the soft start transition threshold and in asynchronous mode below it. (3) Power good is an open collector output which is pulled low when the output voltage is under %. (4) This device is ESD sensitive. Use of standard ESD handling precautions is required. () 1ns maximum at 0 C. Marking Information (TSSOP-) TOP yyww = Datecode (Example: 9908) xxxx = Semtech Lot # (Example: 90101) 04 Semtech Corp. 3

4 POWER MNGEMENT Pin Configuration Top iew Ordering Information 1) D evice ( Package SC26TSTR TSSOP- 2) S C26TSTRT ( TSSOP- SC26EB-1 SC26EB-2 Share Evaluation Board Dual Channel Evaluation Board Notes: (1) Only available in tape and reel packaging. reel contains 200 devices. (2) Lead free package. (TSSOP- Pin) Pin Descriptions EXPNDED PIN DESCRIPTION Pin 1: (REF) Internal 0. reference. Connected to the + input of the master channel error amplifier. Pin 2: (FREQ) External frequency adjustment. Connect a resistor to to set the switching frequency. Please see more information in pplication section. Pin 3: (CC) Bias pin for the controller. Connect a ceramic decoupling capacitor from this pin to with minimum trace length. Pin 4: (+IN2) + input of the slave error amplifier. Pin, 16: (-IN2, -IN1) - inputs of the error amplifiers. Pin 6, 1: (COMP2, COMP1) Compensation pins of the error amplifiers. Pin, 14: (BST2, BST1) Supply pins for the high side drivers. Usually connected to bootstrap circuit. Pin 8, 13: (DH2, DH1) Gate drive pins for the top MOSFETs. Requires a small series resistor. Pin 9, 12: (DL2, DL1) Gate drive pins for the bottom MOSFETs. Requires a small series resistor. Pin 10: (P) Power. Return of the high side and low side gate drivers. Pin 11: (BSTC) Supply pin for bottom MOSFET gate drivers. Pin 1: (PHSING) This pin controls the phase shift between master and slave for optimum noise immunity. Use a resistive divider from the FREQ pin (pin 2) to, and connect the tap of the resistive divider to pin 1. Please see more information in pplication section. Pin 18: (SS/EN) Soft start pin. Connect a ceramic capacitor from this pin to, and there is an internal current source charging up this capacitor during soft start. The PWM operation can be disabled if this pin is pulled low. Pin 19: (PWRGD) Power good signal. This is an open collector output. It is pulled low internally if output voltage is outside the power good window. Pin : () nalog. Return of the analog signals and bias of the chip. 04 Semtech Corp. 4

5 POWER MNGEMENT Block Diagram 1.2 0u NOTES (1) Channel 1 is the Master and Channel 2 is the Slave in current sharing configuration. (2) For dual output operation, tie +IN2 to REF and the two PWM channels are independent. 04 Semtech Corp.

6 PWRGD ENBLE R.K C3 1000uF R13 4.6k C40 C36 0. R31 C4 1000uF U1 SC26 C41 C39 C24 0. C38 M1 R2 0R0 R32 0R0 IPD06N03L IPD06N03L C26 2nF R K M 1-,2Xwg18,8 Turns,4mohm C21 1nF L1 2uH 1 2 L2 R K 2uH 1 2 R8 1.8K C4 C49 C uF C REF 19 FREQ PWRGD 3 18 CC SS/EN 4 1 +IN2 PHSING 16 -IN2 -IN1 6 1 COMP2 COMP1 14 BST2 BST DH2 DH DL2 DL P BSTC + C1 C28 1.0uF C2 R19.9K 2.2 C 1000uF C uF C2 M IPD06N03L C23 IPD06N03L M3 C33 2nF R R1 1.0 R K 1-,2Xwg18,8 Turns,4mohm R3 1.0 C60 1nF R24.0K R26 3.4K C3 2nF C3 2nF C12 C48 C13 C14 C1 C 1800uF R36 0R0 C 1800uF C4 C6 1800uF C46 +out 1.4/16 SC26 POWER MNGEMENT Evaluation Schematic 2 Channels with Sharing 04 Semtech Corp. 6

7 POWER MNGEMENT pplications Information - Theory of Operation Main Loop(s) The SC26 is a dual, voltage mode synchronous Buck controller. The two separate channels are identical and share only IC supply pins (cc and ), output driver ground (P) and pre-driver supply voltage (BSTC). They also share a common oscillator generating a sawtooth waveform for channel 1 and an dephased sawtooth for channel 2. Channel 2 has both inputs of the error amplifier uncommitted and available externally. This allows the SC26 to operate in two distinct modes. a) Two independent channels with either common or different input voltages and different output voltages. The two channels each have their own voltage feedback path from their own output. In this mode, positive input of the error amplifier 2 is connected externally to ref. If the application uses a common input voltage, the sawtooth phase shift between the channels provides some measure of input ripple current cancellation. It is possible to sequence the start up of the channel with an RC delay between the reference and +IN2. The capacitor will be internally reset during ULO and soft start. The controller provides a power good signal. This is an open collector output, which is pulled low if the output voltage is outside of the power good window. Soft Start/Enable The Soft Start/Enable (SS/EN) pin serves several functions. If held below the Enable threshold, both channels are inhibited. DH1 and DH2 will be low, turning off the top FETs. Between the Soft Start Enable threshold and the Soft Start End threshold, the duty cycle is allowed to increase. t the Soft Start End threshold, maximum duty cycle is reached. In practical applications the error amplifier will be controlling the duty cycle before the Soft Start End threshold is reached. To avoid boost problems during start-up in current share mode, both channels start up in asynchronous mode, and the bottom FET body diode is used for circulating current during the top FET off time. When the SS/EN pin reaches the Soft Start Transition threshold, the channels begin operating in synchronous mode for improved efficiency. The soft start pin sources approximately 0u and soft start timing can be set by selection of an appropriate soft start capacitor value. b) Two channels operating in current sharing mode with common output voltage and either common input voltage or different input voltages. In this mode, channel 1 operates as a voltage mode Buck controller, as before, but error amp 2 monitors and amplifies the difference in voltage across the output current sense resistors of channel 1 and channel 2 (Master and Slave) and adjusts the Slave duty cycle to match output currents. To controller also works well for using the output choke winding resistance as current sensing element (please refer the application schematic for details). The amount of the current of the slave channel vs.. the master channel can be programmed according to the application. This feature is especially useful when two input sources are used and each source has its power budget. The offset of the current sharing error amplifier is trimmed whthin the range of -2m to 0. The polarity being such that the slave is OFF if the master has no current. Power Good Frequency Set and Phasing The switching frequency can be programmed by connecting a resistor from the FREQ pin to. The PHSING pin controls the phase shift between the master sawtooth and slave sawtooth which allows the adjustment of the phase shift for maximum noise immunity by controlling the timing between master and slave transition. resistive divider is used from the FREQ pin to and the divided voltage is fed to the PHSING pin as depicted. R13 3.K R K U1 REF 19 FREQ PWRGD 18 CC SS/EN 1 +IN2 PHSING 16 -IN2 -IN1 1 COMP2 COMP1 14 BST2 BST1 13 DH2 DH1 12 DL2 DL P BSTC SC Semtech Corp.

8 POWER MNGEMENT pplications Information Oscillator Frequency (khz) Phase (deg) Shutdown The output short circuit protection is done by output undervoltage detection. Upon output short circuit and when the output voltage drops bellow a certain percentage of the regulation target (see elctrical characteristics table for details, the PWM will be disabled and the output will be dsiabbled and latched off. The latch can be reset by power cycling. Layout Guidelines (R13+R19) vs.oscillator Frequency (R13+R19) (kohm) phasing vs Phase Shift phasing () Power and signal traces must be kept separated for noise considerations. Feedback, current sense traces and analog ground should not cross any traces or planes carrying high switching currents, such as in the input loop or the phase node. The input loop, consisting of the input capacitors and both MOSFETs must be kept as small as possible. Since all of the high switching currents occur in the input loop, the enclosed loop area must be kept small to minimize inductance and radiated and conducted noise emissions. Designing for minimum trace length is not the only factor It is important to keep the gate traces short, the IC must be close to the power switches. It is recommended to use at least 2 mil width or wider trace when ever possible. good placement can help if the controller is placed in the middle of the two PWM channels. Grounding requirements are always important in a buck converter layout, especially at high power. Power ground (P) should be returned to the bottom MOSFET source to provide the best gate current return path. nalog ground () shape should be used for the anaglog returns such as chip decoupling, frequency setiing, reference voltage (or soft starting cap), and the compensation. This groung shap should be single point connected to the P shape near the ground side of the output capacitors. This will provide noise free analog ground for operation stablity, and also provide best possible remote sensing for the feedback voltage. In case two output rails need to be regulated, the shape should single point connected to the geometrica center of the P for the two point of loads. The single ponit tie is a must to prevent the power current from flowing on the shape, so that the analog circuitry in the controller has an electrically quiet reference and to provide the greatest noise free operation. Keep in mind that the pin is never allowed to have bigger than 1 voltage difference vs the P pin. This usually achievable by using a ground plan for P in PCB layout. Using ground plane for P can reduce the physical separation between the two grounds, such that even the fast current transitions in the P plane can not generate voltage spikes exceeding the 1 level, therefore preventing unstable and erratic behavior from happening. The feedback divider must be close to the IC and be returned to analog ground. sense traces must be run parallel and close to each other and to analog ground. The IC must have a ceramic decoupling capacitor across its supply pins, mounted as close to the device as possible. The small ceramic, noise-filtering capacitors on the current sense lines should also be placed as close to the IC as possible. for best design, often a more optimum layout can be achieved by keeping the wide trace and using proper layer stacking to minimize the stray inductance. 04 Semtech Corp. 8

9 POWER MNGEMENT Outline Drawing - TSSOP- 2X ccc C 2X N/2 TIPS aaa E/2 PIN 1 INDICTOR SETING PLNE C C N D e D E1 E e/2 B 2 1 bxn bbb C -B D DIMENSIONS DIM INCHES MILLIMETERS MIN NOM MX MIN NOM MX b c D E E e.22 BSC.026 BSC 6.40 BSC 0.6 BSC L L1 (.039) (1.0) N aaa bbb ccc GGE PLNE H c SIDE IEW SEE DETIL 0.2 DETIL L (L1) 01 NOTES: 1. CONTROLLING DIMENSIONS RE IN MILLIMETERS (NGLES IN DEGREES). 2. D TUM S -- N D -B- TO B E DE TE RM IN ED T DTUM PLNE -H DIMENSIONS "E1" ND "D" DO NOT INCLUDE MOLD FLSH, PROTRUSIONS OR GTE BURRS. REFERENCE JEDEC STD MO-13, RITION C. Land Pattern - TSSOP- X DIMENSIONS DIM C IN C H E S (.222) MILLIMETERS (.6) (C ) G Z G P X Y Y Z.283. P NOTES: 1. THIS LND PTTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MNUFCTURING GROUP TO ENSURE YOUR COMPNY'S MNUFCTURING GUIDELINES RE MET. Contact Information Semtech Corporation Power Management Products Division 0 Flynn Road, Camarillo, C Phone: (80) FX (80) Semtech Corp. 9