MD3880DB1: Ultrasound Low Noise Amplifier Demoboard

Transcription

1 MD388DB1: Ultrasound Low Noise Amplifier Demoboard MD388DB1 General Description The MD388DB1 demoboard is a platform for testing and evaluating the MD388 4-channel low-noise amplifi er (LNA) with a variable gain amplifi er (VGA). There are three 2.V input supplies so that it can test each supply s performance individually. The input supplies are: LNA power supply (AV DD ); control interface power supply (AV DD _CNTRL); and VGA power supply (AV DD _AMP). The MD388DB1 schematic is shown on the following page. The input impedance of the LNA is confi gured for Ω, to match the output impedances of the equipment. This input impedance can be changed according to the datasheet. Ferrite beads and capacitors are installed at the LNA for fi ltering the high frequency components for a more stable operation. All channel outputs are connected to resistor dividers in order to have approximately 2Ω loading to ground and Ω impedance matching for measurement purposes. In addition, for measurement simplicity, a transformer with a 1:1 turns ratio is needed to convert the differential outputs to single-ended output. Note that there is -19.8dB attenuation from the divider, which needs to be taken into account when using these outputs. Different loads can also be connected via the SMA connectors for direct measuring if the two 28Ω resistors are removed. In this condition, the VGA output is in series with 237Ω resistors only and the output impedance becomes higher. Therefore, one needs to compensate for the attenuation if low impedances are connected to the output SMA when performing direct measurement. The A and A1 pins are reversed and connected to V DD. PG and PG1 are used for setting the VGA gain. Each gain step is approximately.db. GSC is the reference voltage of the Voltage Control Attenuator (VCA) for programming the slope of the linear-in-db curve. TGC is to vary the VCA gain from db to -47dB. PDC is to power down the MD388 or to adjust the current consumption. The EBC pin is connected to a known value resistor or variable resistor for programming the current consumption. Connections Name Signals Voltage AV DD AV DD +2.V AV DD _AMP V DD +2.V AV DD _CNTRL V DD +2.V GND GND V AGND AGND V TGC TGC to +2.V EBC EBC 1k VR to GND PDC PDC Hi / Lo A A Reserved, +2.V A1 A1 Reserved, +2.V PG PG Hi / Lo PG1 PG1 Hi / Lo GSC GSC 2.V / External INPUT_A~D INPUT +/-21mV P-P OUTPUT_A~D OUTPUT w/ -19.dB atten. Actual Dimensions: 1mm x 113mm

2 MD388DB1 Demo Board Schematic 2

3 MD388DB1 MD388 Performance Test Report 1. Electrical Parameters Measurement All typical values are under the following conditions, unless otherwise noted: T A = + 2 C, V DD = 2.V, Load resistance = Ω across the differential outputs, C LOAD = 1pF, f IN = 1MHz, PG = V, PG1 = V, PDC =, V GSC = 2.V, V CM = 1.2V, amp gain = 18.dB, single-ended input: R S = R IN = Ω. R IN is formed by active termination with R FB = 237Ω and C FB, differential signal output, V IN is the voltage at the non-inverting node of the amplifi er Low Noise Amplifier Sym Parameter Specification Min TEST Max Units Notes G LNA Pre-amplifi er gain db --- R IN Input resistance kω Without active termination C IN Input capacitance pf Without active termination I BIAS Input bias current na From ESD leakage CMRR Com. mode rejection ratio db PG = PG1 = V DD, V TGC = 2.V, f = 1MHz V IN Input voltage - ±21 - mv --- V IN-NOISE Input voltage noise, MHz nv/ Hz Without active termination I IN-NOISE Input current noise pa/ Hz Without active termination db f =.MHz, without active termination NF Noise fi gure R db S = R IN = Ω, f =.MHz with active termination BW Bandwidth MHz Small signal bandwidth 1.2. Overall Channels Sym Parameter Specification Min TEST Max Units Notes Gain Whole channel gain db Without active termination, max. gain BW VGA -3dB bandwidth MHz Small signal bandwidth at max. gain SR VGA Slew rate - - V/µs --- VO VGA Output signal range V PP R L > 1.kΩ differentially R OUT Output impedance Ω f =.MHz, single ended I OUTS Output short-circuit current ma --- V IN-NOISE Input voltage noise nv/ Hz At Max. gain and MHz IMD Intermodulation distortion, two-tone Third harmonic distortion Second harmonic distortion db 1MHz, V OUT = 1.V PP, 3dB gain db 1MHz, V OUT = 1.V PP, 3dB gain db V OUT = 1.V PP, 1MHz, 3dB gain db V OUT = 1.V PP, 1MHz, 3dB gain db V OUT = 1.V PP, 1MHz, 1dB gain db V OUT = 1.V PP, 1MHz, 1dB gain db V OUT = 1.V PP, 1MHz, 3dB gain db V OUT = 1.V PP, 1MHz, 3dB gain db V OUT = 1.V PP, 1MHz, 1dB gain db V OUT = 1.V PP, 1MHz, 1dB gain 3

4 MD388DB Overall Channels (cont.) Sym Parameter Specification Min TEST Max Units Notes A OUT1dB 1dB compression point dbm V OUT = 1.V PP, f = 1MHz, 8dB gain CSTK Crosstalk db PG = PG1 = 1, 3dB gain, 1MHz, 1.V PP at adjacent channel Δtgd Group delay variation - ±2 - ns 2 MHz < f < MHz, full gain range t OLR Overload recovery time - - ns 8dB gain, V IN = mv PP to 1V PP change, f = 1MHz V DC-OUT DC output Level, V IN = V --- Note: V IN is the voltage at the non-inverting node of the amplifi er Accuracy Sym Parameter Specification Min TEST Max Units Notes G SLOPE Gain slope db/v V GSC = 2.V G MAT Ch. to ch. gain matching - ±.1 - db V TGC = V or 2.V E GAIN Gain error - ±.8 - db Referenced to best fi t db-linear curve V GSC Slope control voltage 2-2. V --- V OS-OUT Output offset voltage - ±2 - mv Reference to 1.2V 1.4. Gain Control Interface Sym Parameter Specification Min TEST Max Units Notes V TGC Gain control voltage - 2 V Linear in db, see Gain Scaling Diagram V GSC Gain slope voltage V About 41dB/V at 2.V and 33dB/V at 2.V R GSC Input resistance of GSC kω --- I TGC Input current of V TGC µa V TGC = 2V I GSC Input current of V GSC µa V GSC = 2.V td TGC Response time µs 9% full gain change 1.. Power Supply Sym Parameter Specification Min TEST Max Units Notes V DD Power supply V T A = -4 to +8 C I DDQ V DD supply current PDC = ma Power down status, total of all channels I DD V DD supply current ma Per channel PWR Power dissipation mw Total of all channels mw Per channel 4

5 MD388DB1 2. Measuring the MD Low Noise Amplifier The amplifi er gain is designed at 18.dB for optimized noise performance and maximum input voltage. The 6kΩ input bias resistor is selected to give the user a higher degree of freedom to program the active termination input impedance for matching the source impedance, as shown in the LNA input impedance vs. frequency (Figure 12). The input capacitance is about 17.pF. The LNA input-referred voltage noise is calculated based on the whole channel output-referred voltage noise. As the gain of LNA is not high, the output noise of the LNA cannot be measured directly. Thus, it needs the following stages to amplify the noise such that the spectrum analyzer can read the output noise spectrum greater than the noise fl oor. The input-referred current noise is not measured and is estimated by the fact that the LNA input stage is constructed by a MOS transistor, of which the input current is assumed to very small Gain Control Interface Input resistance of the slope control has less than 1% variation. The gain control pin draws very small current. to 9% gain transient response time is about 1ns. 2.. Power Supply Current consumption is about 3mA on these engineering samples. The amplifi er PSRR at 1kHz is around -6dB when PG = PG1 = Hi. The PSRR will not vary much no matter what the values of V TGC and the gain setting are. 3. Typical Characteristic Curves All measured typical values are under the following conditions unless otherwise noted: T A = + 2 C, V DD = 2.V, R LOAD = Ω at the differential outputs, C LOAD = 1pF, f IN = 1MHz, PG = V, PG1 = V, V GSC = 2.V, V CM = 1.2V, amp gain = 18.dB, single-ended input: R S = R IN = Ω. (The R IN is formed by active termination with R FB = 237Ω and C FB ) differential signal output Gain vs. TGC Voltage at Different PG & PG1 settings and GSC = 2.V 8 Gain v s. V GAIN The noise fi gure is calculated from the input-referred noise results. The LNA bandwidth is measured at about 14MHz. The common-mode rejection ratio of the amplifi er is -6dB. GAIN (db) PG1=High, PG=High PG1=Low, PG=High PG1=High, PG=Low 2.2. Overall Channel The whole channel s input voltage referred-input voltage noise is.8nv/ Hz. The channel crosstalk is measured to be better than -7dB when the signal frequency is below 1MHz. Group delay variation is ±2ns, from 2MHz to MHz. The overload recovery time is about ns when the gain is set at 8dB, V IN = mv P-P to 1.V P-P step-change and the frequency is 1MHz Accuracy The gain slope of the VCA linear-in-db control curve is measured to be 33.2dB/V. The channel-to-channel gain matching is ±.1dB at voltage control equals V or 2V. Other than the conditions of minimum and maximum VCA gain settings, the channel-to-channel gain matching of the MD388 can be up to ±.3dB including the VCA interpolating effect. Gain slope control voltage is tested at the gain slope control voltage from 2V to 2.V. The slope of the linear-in-db curve will be changed accordingly. The differential output offset is about ±2mV. 2 1 PG1=Low, PG=Low VGAIN (V) Figure 1 Figure 1 shows that the gain vs. TGC control voltage with slope control voltage GSC equals 2.V with different PG and PG1 settings. The gain spacing between settings is approximately.db. A 1MHz signal is applied at the input with ohm active termination. With settings at PG and PG1, the control voltage is varied with.1v step. The differential output is measured at a no-clipping condition and throughout the whole channel Gain vs. TGC Voltage at Different GSC Voltages Figure 2 shows the gain vs. TGC control voltage with different GSC slope control voltages. Only one case where PG and PG1 are both low is charted. Other cases have the similar effect. The measurement method is the above measurement. The advantage of having the gain slope control voltage GSC pin is to let the user apply a programmable

6 MD388DB1 stable reference voltage among all the receiver channels in order to have the same gain throughout the whole system and varying the gain together. 6 Frequency Response for Various Values of V GAIN PG1 = Low, PG = Low V GA IN = 2V 6 Gain vs. VGAIN at Different Vslope PG1 = Lo w, PG = Low 4 V GAIN = 1.6V V GAIN = 1.2V GAIN (db) Vslope=2.2V 4 3 V slope=2v Vslope=2.V GAIN (db) V GAIN =.8V V GAIN =.4V V GAIN =.V -2 1.E+ 1.E+6 1.E+7 1.E+8 1.E+9 Figure 4 Figure Absolute Gain Error vs. TGC at Various Frequencies Figure 3 shows the absolute gain error vs. TGC at 1MHz, 1MHz and 3MHz Absolute Gain Error vs. V GAIN at Various Frequencies GAIN (db) Frequency Response for Various Values of V GAIN PG1 = Low, PG = High V GA IN = 2V V GAIN = 1.6V V GAIN = 1.2V V GAIN =.8V V GAIN =.4V V GAIN =.V GAIN ERROR (db) MHz 3MHz 1MHz Figure Frequency Response Various with TGC Figures 4 through 7 show the frequency response of the MD388. All of the curves are measured with a network analyzer with frequencies up to 2MHz. Note that there is a high-pass corner frequency existing at 1kHz and it is not displayed in the fi gures. GAIN (db) -2 1.E+ 1.E+6 1.E+7 1.E+8 1.E Figure Frequency Response for Various Values of V GAIN PG1 = High, PG = Low V GA IN = 2V V GAIN = 1.6V V GAIN = 1.2V V GAIN =.8V V GAIN =.4V V GAIN =.V -2 1.E+ 1.E+6 1.E+7 1.E+8 1.E+9 Figure 6 6

7 MD388DB1 8 Frequency Response for Various Values of V GAIN PG1 = High, PG = High V GA IN = 2V Channel-to-Channel Crosstalk PG1 = Low, PG = Low 7-1 V OUT = 1Vpp GAIN (db) V GAIN = 1.6V V GAIN = 1.2V V GAIN =.8V V GAIN =.4V V GAIN =.V -2 1.E+ 1.E+6 1.E+7 1.E+8 1.E+9 Figure Frequency Response, Un-terminated Figure 8 shows the whole channel frequency response without active termination, source resistance is Ω and GSC is at 1.V V GAIN = 1V RFB = Frequency Response, Unterminated, R s = ohm PG1 = Low, PG = Low Crosstalk (db) E+ 1.E+6 1.E+7 1.E+8 Figure Group Delay vs. Frequency Figure 1 shows the group delay vs. frequency. Due to the internal 44pF and 1MΩ high-pass fi lter, the fairly constant group delay only can be achieved at frequency 2. to 2MHz. The group delay variation is ±2ns up to 6MHz. 1 V GAIN =.7V V GAIN = 1.2V V GAIN = 2V Group Delay vs. Frequency PG1 = High, PG = High, V GAIN = V GAIN (db) E+ 1.E+6 1.E+7 1.E+8 GROUP DELAY (ns) Figure Channel-to-Channel Crosstalk vs. Frequency for Various Values of TGC Figure 9 shows the channel-to-channel crosstalk vs. frequency for various voltages of TGC. Although there are four channels in a single chip, only one adjacent channel crosstalk is charted in this measurement. There is better than 7dB crosstalk when the frequency is below 1MHz. 1 1.E+ 1.E+6 1.E+7 1.E+8 Figure 1 7

8 MD388DB Output Impedance vs. Frequency Figure 11 shows the single-ended output impedance vs. frequency. 1 Output Impedance vs. Frequency SINGLE ENDED, R L = OUTPUT IMPEDANCE (ohm) E+ 1.E+6 1.E+7 1.E+8 Figure 11 Figure LNA Frequency Response, Single Ended Figure 14 shows the LNA frequency response, inverting output, for values of R IN Ω and 1Ω. The R IN is formed same as in Figure 12 measurement LNA Input Impedance vs. Frequency Figure 12 shows the LNA active termination input impedance vs. frequency. The input impedance with R FB =, R FB = 237Ω and R FB = 47Ω is shown. Based on the active termination equation, R IN = R FB /(1+A), a smaller R FB will be better for implementing Ω or 1Ω termination in this version. Note that the parasitic leads inductance and coupling capacitor in series with the input. GAIN (db) 1 1 LNA Frequency Response, Single Ended R IN ~ 1Ω R IN ~ Ω 1 LNA Input Impedance vs. Frequency 1.E+ 1.E+6 1.E+ 7 1.E+8 INPU T IMPEDA NCE (o hm) R FB = 47, C SH = 8.2pF R FB = 237, C SH = 22pF R FB = Inf inity, C SH = pf Figure Frequency Response for Un-terminated LNA, Single Ended Figure 1 shows the un-terminated LNA frequency response, inverting output, for Values of R IN. 1 1.E+ 1.E+6 1.E+7 1.E+8 Fre que ncy (H z) Figure Smith Chart, S11 vs. Frequency Figure 13 shows the Smith chart, S11 vs. frequency with the same settings as in Figure 12 measurement. (.1MHz to 8MHz for Values of R FB = 237Ω and 47Ω) GAIN (db) LNA Frequency Response, Unterminated, Single-Ended E+ 1.E+6 1.E+7 1.E+8 Figure 1 8

9 MD388DB Output-Referred Noise vs.tgc Figure 16 shows the output-referred noise vs. TGC with different PG and PG1 settings. The data is measured directly from the output with a transformer for converting the differential signal to a single ended signal Short-Circuit, Input-Referred Noise vs. TGC Figure 18 shows the input-referred voltage noise vs. TGC voltage, when PG = PG1 = High. The data is obtained by calculating the output-referred output over the whole channel gain. OUTPUT REFERRE D NOISE (nv/root Hz) f = 1MHz Outp ut R ef erre d No ise v s. VGAIN PG1=High, PG=High PG1=High, PG=Low PG1=Low, PG=High PG1=Low, PG=Low INPUT NOISE (nv/root Hz) Short-Circuit, Input-Referred Noise vs. V GAIN R S =, R FB = PG1=High, PG=High, f = 1MHz Figure Short-Circuit, Input-Referred Voltage Noise vs. Frequency Figure 17 shows the input-referred voltage noise from 1kHz to 6MHz. As the input stage of the amplifi er is formed by MOS transistors, it has 1/f noise and the noise corner is about 1.MHz as shown in the fi gure. At MHz, the input-referred noise is approximately.8nv/ Hz Figure Input-Referred Voltage Noise vs. R S Figure 19 shows the input-referred voltage noise vs. R S the signal source resistance. 2. Short-Circuit, input-referred Noise vs. Frequency PG1=High, PG=High 1. f = MHz, R FB =, V GAIN = 2V Input-Referred Noise vs. R s INPUT NOISE (nv/ Hz) INPUT NOISE (nv/root Hz) 1. R S THERMAL NOISE ALONE. 1.E+ 1.E+6 1.E+7 1.E+8 FREQUENCY (Hz) Figure E+ 1.E+1 1.E+2 1.E+3 SOURCE RESISTANCE (ohm) Figure 19 9

10 MD388DB Noise Figure vs. R S for Various Values of R IN NOISE FIGURE (db) f = 1MHz Noise Figure vs. R s for Various Values of R IN R IN = Ω R IN = 7Ω R IN = 1Ω R IN = 2Ω R IN = SOURCE RESISTANCE (Ohm) Figure 2 Figure 2 is the noise fi gure vs. source resistance for various values of input resistance Noise Figure vs. TGC Voltage Figure 21 shows the noise fi gure vs. TGC. It is calculated by the input-referred noise measurement results and noise fi gure equation. NOISE FIGURE(dB) Noise Figure vs. VGAIN R S = Ω PG1=High, PG=High, f = 1MHz R IN = R IN = Ω VGAIN (V ) Figure Noise Figure vs. Gain NOISE FIGURE (db) PG1 = Low, PG = Low R IN = Ω Noise Figure vs. Gain PG1 = Low, PG = Low R IN = PG1 = High, PG = High R IN = Ω GAIN (db) Figure 22 Figure 22 shows the noise fi gure vs. gain. Only PG = PG1 = High and PG = PG1 = Low measurement results are charted. The data is calculated from the 1MHz input-referred noise measurement result Harmonic Distortion vs. Frequency Figures 23 through 26 show the harmonic distortion vs. frequency with different PG and PG1 settings. HARMONIC DISTORTION (dbc) G = 3dB V OUT = 1Vpp Harmonic Distortion vs. Frequency PG = High, PG1 = High Figure 23 R S = Ω, f = 1MHz PG1 = High, PG = High R IN = FREQUENCY (MHz) 1

11 MD388DB1 HARMONIC DISTORTION (dbc) G = 3dB V OUT = 1Vpp Harmonic Distortion vs. Frequency PG1 = High, PG = Low FREQUENCY (MHz) Figure Harmonic Distortion vs. Differential Output Voltage Figures 27 through 3 show the harmonic distortion vs. differential output voltage. Note that the maximum differential output is 4V. HARMONIC DISTORTION (dbc) Harmonic Distortion vs. Differential Output Voltage PG1 = High, PG = High G = 3dB f = 1MHz HARMONIC DISTORTION (dbc) G = 3dB V OUT = 1V PP Harmonic Distortion vs. Frequency PG1 = Low, PG = High FREQUENCY (MHz) Figure 2 HARMONIC DISTORTION (dbc) V OUT (V PP ) Figure 27 Harmonic Distortion vs. Differential Output Voltage PG1 = High, PG = Low G = 3dB f = 1MHz VOUT (V PP ) Harmonic Distortion vs. Frequency PG1 = Low, PG = Low Figure 28 HARMONIC DISTORTION (dbc) G = 3dB V OUT = 1V PP FREQUENCY (MHz) HARMONIC DISTORTION (dbc) Harmonic Distortion vs. Differential Output Voltage PG1 = Low, PG = High G = 3dB f = 1MHz Figure V OUT (Vpp) Figure 29 11

12 MD388DB1-4 Harmonic Distortion vs. Differential Output Voltage PG1 = Low, PG = Low G = 3dB f = 1MHz -1 V OUT = 1Vpp Harmonic Distortion vs. V GAIN, f = 1MHz PG1 = Low, PG = High HARMONIC DISTORTION (dbc) DISTORTION (dbc) V OUT (Vpp) Figure Harmonic Distortion vs. TGC Figures 31 through 34 show the harmonic distortion vs. TGC at 1MHz. DISTORTION (dbc) DISTORTION (dbc) V OUT = 1Vpp Harmonic Distortion vs. V GAIN, f = 1MHz PG1 = High, PG = High V OUT = 1Vpp Figure 31 Harmonic Distortion vs. V GAIN, f = 1MHz PG1 = High, PG = Low Figure DISTORTION (dbc) Figure 33 Harmonic Distortion vs. V GAIN, f = 1MHz PG1 = Low, PG = Low Figure Harmonic Distortion vs. TGC Figures 3 through 38 show the harmonic distortion vs. TGC at 1MHz. DISTORTION (dbc) V OUT = 1Vpp V GAIN (V) V OUT = 1Vpp Harmonic Distortion vs. VGAIN, f = 1MHz PG1 = High, PG = High Figure 3 12

13 MD388DB1-1 V OUT = 1Vpp Harmonic Distortion vs. V GAIN, f = 1MHz PG1 = High, PG = Low Gain Amplifi er and Differential Gain Amplifi er when TGC is lower than.4v. Otherwise, it is limited by the amplifi er at maximum -1dBm. DISTORTION (dbc) Figure 36 INPUT POWER (dbm) PG1=High, PG=High Input 1dB Compression vs. VGAIN PG1=High, PG=Low PG1=Low, PG=High PG1=Low, PG=Low DISTORTION (dbc) V OUT = 1Vpp Harmonic Distortion vs. V GAIN, f = 1MHz PG1 = Low, PG = High Figure IMD3 vs. Frequency Figures 4 through 43 show the IMD3 vs. frequency. -1 IMD3 vs. Frequency PG1 = High, PG = High G = 3dB V OUT = 1Vpp COMPOSITE (f 1 1+f 2 2) ) Figure 37 IMD3 (dbc) V OUT = 1Vpp Harmonic Distortion vs. VGAIN, f = 1MHz PG1 = Low, PG = Low FREQUENCY (MHz) Figure 4 DISTORTION (dbc) V GAIN (V) Figure dB Compression vs. TGC Figure 39 shows the 1dB compression point measurement vs. TGC at 1MHz with PG = PG1 = High. The 1dB compression point is limited by the total gain of the internal Fixed IMD3 (dbc) G = 3dB V OUT = 1Vpp COMPOSITE (f 1 1+f 2 2) ) IMD3 vs. Frequency PG1 = High, PG = Low FREQUENCY (MHz) Figure 41 13

14 MD388DB1 IMD3 (dbc) IMD3 vs. Frequency PG1 = Low, PG = High G = 3dB V OUT = 1Vpp COMPOSITE (f1+f2) 1 2 ) FREQUENCY (MHz) Figure 42 OUTPUT IP3 (dbm) MHz Output Third-Order Intercept vs. VGAIN PG1 = High, PG = Low 1MHz V OUT = 1V PP CO MPOSITE ( f 1+f 2) Figure 4 IMD3 vs. Frequency PG1 = Low, PG = Low 4 3 Output Third-Order Intercept vs. VGAIN PG1 = Low, PG = High IMD3 (dbc) G = 3dB V OUT = 1Vpp COMPOSITE (f 1 1+f 2 2) ) OUTPUT IP3 (dbm) 3 1MHz 2 1MHz V OUT = 1V PP CO MPOSITE ( f 1 +f 2 ) VGAIN (V) FREQUENCY (MHz) Figure Output Third-Order Intercept vs. TGC Figures 44 through 47 show the OIP3 vs. TGC at different PG and PG1 settings. OUTPUT IP3 (dbm) Output Third-Order Intercept vs. VGAIN PG1 = High, PG = High 1MHz 1MHz OUTPUT IP3 (dbm) Figure 46 Output Third-Order Intercept vs. VGAIN PG1 = Low, PG = Low 1MHz V OUT = 1V PP CO MPOSITE ( f 1 +f 2 ) 1MHz Figure 47 1 V OUT = 1V PP CO MPOSITE ( f 1+f 2) VGAIN (V) Figure 44 14

15 MD388DB Small Signal Pulse Response Figure 48 shows the small signal pulse response with 1pF loading. (gain = 3dB, 1pF load, Top: input, bottom: output voltage with attenuation of 1) Large Signal Pulse Response Figure shows the large signal pulse response with 47pF loading. (gain = 3dB, 47pF load, top: the input signal, bottom: the output voltage with attenuation of 1) 1mV/div mv/div 2mV/div 1mV/div 2ns/div Figure 48 2ns/div Figure Large Signal Pulse Response Figure 49 shows the large signal pulse response with 1pF loading. (gain = 3dB, 1pF load, Top: input, bottom: output voltage with attenuation of 1) 3.3. TGC Gain Control Transient Response Time at PG = PG1 = Low. Figure 1 shows TGC transient response. Top: TGC control voltage, Bottom: signal output voltage with attenuation of 1. The result showed that the TGC response time is less than 2ns. mv/div 2.V/div 1mV/div 1mV/div 2ns/div Figure 49 2ns/div Figure 1 1

16 MD388DB LNA Overload Recovery Time Figure 2 shows LNA overdrive recovery (V INPUT = mv P-P to 1V P-P burst, gain = 23dB, top: the input signal, bottom: the channel output with attenuation of 2.) 1mV/div mv/div 1mV/div 8ns/div Figure 2 1mV/div VGA Overload Recovery Time Figure 3 shows VGA overdrive recovery (V INPUT = 2.mV P-P to 7mV P-P burst, gain = 43dB, top: input, bottom: channel output with attenuation of 2.) mv/div 8ns/div Figure PSRR vs. Frequency Figures and 6 show both the amplifi er and VGA PSRR measurement results. The PSRR is plotted based on the equation: [ 2log(GainOPEN / (V OUT / ΔV DD ))]. The Gain- OPEN, open loop gain of VGA PG = PG1 = Low, V GAIN = V, the measurement result is -26dB. Since the gain of the fi xedgain amplifi er and PGA is 3dB, the VGA PSRR becomes - 26dB -3dB = -61dB and it is irrelevant to VCA and amplifi er. The reason for setting the V GAIN to zero is to make the input of the VGA as small as possible. The measurement of the amplifi er is as the same as VGA PSRR measurement. The V OUT is the channel output. For example, at 1kHz, the output is recorded to be -41dB. Since the whole channel gain is 23dB, the amplifi er PSRR becomes -41dB-23dB = -64dB. The reason for setting PG = PG1 = High is to maximize the gain of the fi xed-gain amplifi er for simplifying the measurement. 1mV/div VGA PSRR vs. Frequency (No Bypass Capacitor) PG1 = Low, PG= Low, V GAIN = V PG1 = Low, PG= High, V GAIN = V 8ns/div Figure VGA Overload Recovery Time Figure 4 shows VGA overdrive recovery (V INPUT = 1mV P-P to 28mV P-P burst, gain = 43dB, top: input, bottom: channel output with attenuation of 2.) PSRR (db) PG1 = High, PG= High, V GAIN = V PG1 = High, PG= Low, V GAIN = V -9 1.E+ 1.E+6 1.E+7 1.E+8 Figure 16

17 MD388DB Preamplifier PSRR vs. Frequency (No Bypass Capacitor) PG1 = High, PG= High, V GAI N = V -4-4 PSRR (db) E+ 1.E+6 1.E+7 1.E+8 Figure 6 4. Measurement Considerations and Setups 4.1. Gain and Bandwidth and Group Delay Measurements A 2.V, 4mA (minimum) power supply is required, and a low noise voltage reference supply is required for V TGC. Figures 7 through 6 show typical testing confi gurations and appropriate interface values for measurements with Ω conditions. As the maximum whole channel gain is 7dB, when measuring high gain settings, the output signal power of the network analyzer should be small enough (i.e. -6dBm) such that the channel output will not be clipped. LNA Figure 7 17

18 MD388DB Frequency Response for Unterminated Single Ended LNA Since the output impedance of the LNA is not confi gured to Ω, a high impedance active probe is used in the measurement. The calibration of the frequency response for the whole setup should take the high impedance active probe effect into account. LNA Figure LNA Input Impedance vs. Frequency in Standard and Smith Chart (S11) formats The measurement results will include the ferrite bead inductor and fi ltering capacitor and the parasitic effect from the PCB. Simply short the ferrite bead inductor and remove the fi ltering capacitor if needed. Suitable calibrations should be executed for eliminating the PCB effect. LNA Figure 9 18

19 MD388DB Shot-Circuit, Input-Referred Noise and Noise Figure The input-referred noise level is found by dividing the output noise by the channel gain and accounting for the noise fl oor of the spectrum analyzer. As the VGA drives the Ω load directly, the gain should be measured at each interested frequency with signal generator. The signal generator is removed when measuring output noise. LNA Figure Harmonic Distortion Measurements The harmonic distortion can only be accurately measured with a low harmonic distortion signal generator. If the signal generator cannot provide such a low harmonic distortion signal, a low-pass fi lter is usually used to ensure the measured harmonic is absolutely from the device. LNA Figure 61 19

20 MD388DB IMD3 and OIP3 vs. Frequency Measurements Two signal generators are used in the IMD3 and OIP3 measurements. Their signal power can be combined by a Ω matching power combiner. LNA Figure Pulse Response Measurement A pulse generator is used in the pulse response measurement. Different pulse magnitudes are applied to the input of LNA and an oscilloscope is used to capture the output waveform. The whole channel gain is properly set so as not to clip the output waveform. LNA Figure GAIN Transient Response Measurement In the transient response measurement, a differential probe is used to measure the output waveform directly without magnitude attenuation. The signal applied to the TGC pin should be properly shielded to avoid any signal coupling to the system. LNA Figure 64 2

21 MD388DB PSRR vs. Frequency Measurement The output signal of the network analyzer is applied to either LNA or VGA supply for measuring the individual PSRR. All the decoupling capacitors mounted to the V DD pins are removed during the measurement. Also, the frequency response of the whole channel should be taken into account. LNA Figure