Combinational Logic. Prof.Manoj Kavedia ( )

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1 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) ` 3 Combinational Logic Chapter-3(ours : 6 Marks:32 )( 269 Principle of Digital Technology) Combinational Logic Circuits 3. Introduction to combinational logic circuit. 3.2 Standard representation of Canonical forms (SOP & POS, Minterm, Maxterm) Conversion between SOP & POS,Numericals based on above topic, Don t care conditions. 3.3 K map reduction techniques and realization (only for SOP 2, 3, 4 variables), Realization using K map techniques of alf adder, full adder, alf subtractor, full subtractor, gray to binary, binary to gray converter, BCD to 7 segment decoder using K-map. 3.4 Multiplexer - Necessity of multiplexer, Types of multiplexers 2:, 4:, 8:, 6: with realization, Multiplexer Tree, Study of MUX ICs 745, 745, 7452, 7453, 7457, Applications of multiplexer. 3.5 Demultiplexer - Necessity and Principle of Demultiplexer, Types and realization of De Mux :2, :4, :8, :6, Demux Tree, Application of Demux as decoder, Study of ICs 7438, 7439, 7454, Combinational Logic Circuit Combination Logic circuits are made up from basic logic AND, OR or NOT gates that are "combined" or connected together to produce more complicated switching circuits. As combination logic circuits are made up from individual logic gates they can also be considered as "decision making circuits" and combinational logic is about combining logic gates together to process two or more signals in order to produce at least one output signal according to the logical function of each logic gate. Common combinational circuits made up from individual logic gates include Multiplexers, Decoders and De-multiplexers, Full and alf Adders etc. Classification of Combinational Logic One of the most common uses of combination logic is in Multiplexer and De-multiplexer type circuits. ere, multiple inputs or outputs are connected to a common signal line and logic gates are used to decode an address to select a single data input or output switch. A multiplexer consist of two separate components, a logic decoder and some solid state switches, but before we can discuss multiplexers, decoders and de-multiplexers in more detail we first need to understand how these devices use these "solid state switches" in their design.

2 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Standard Representation For Logical Function Q.What is Variable and list the standard from of the Boolean Function Ans.A Variable in complemented or uncomplemented form is known as Literal. Thus Boolean functions or equation are expressed in terms of literal. The values assumed by literal are in binary form. Any Boolean function can be expressed in two standard or canonical forms ) Sum of product (SOP) 2) Product of sum (POS) If each term in SOP and POS form contain all the literal (variables) then these are known as standard SOP or standard POS form. Q2.What SOP and ow SOP Equations are represented? Ans.Standard SOP form Each individual term in standard SOP form is called as minterm. Y = PQR + PQR + PQR + PQR + PQR This contain all the independent variable in SOP form which is obtained by first ANDing and then ORing them i.e. minterm or each term. ence above equation has 5 minterm's PQR,PQR,PQR,PQR,PQR. The possible number of minterm is equal to 2 to the power of number of variable i.e. if 3 variables are present in equation then there are 2 3 = 8 minterm's. Minterm with normal complemented variables is taken as and uncomplemented is taken as. 2

3 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 3

4 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Fig. Shows the truth able for 3 variables Boolean expressions. A B A Decimal equivalent Using these notation we can write equation as Y = m7 +m6+m5+m4+m3+m2+m+m Y = m Σ (,,2,3,4,5,6,7) Minterm(mi) CBA CBA CBA CBA CBA CBA CBA CBA Notation m m m2 m3 m4 m5 m6 m7 ence it is easy to used notation instead of minterm. The symbol Σ represent ORing of minterm. Q3. Write truth table and equation in SOP form for following minterm. Y = m(,3,6,7) Ans : Minterm are M,M2,M3,M4,M5,M6,M7. And equation has 3 variables. ence the truth table is M table for minterm available in function write. A B C Minterm ABC ABC ABC ABC ABC ABC ABC ABC Notations M M M2 M3 M4 M5 M6 M7 Y Y = ABC +ABC+ABC+ABC. In general each row of truth table has functional value described by minterm. The minterm is product of literal. The complement variable has value logic and uncomplemented variable has value logic. Combining all the products term (minterm) constructed for the variable having value= i.e. minterm value = by Boolean OR operation results in minterm canonical form. 4

5 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q4.What POS and ow POS Equations are represented? Ans.Product of Sum( POS ) Product of sum method is also called as maxterm canonical form. Consider the equation Y = (A+B+C)(A+B+C)(A+B+C) In this approach independent variables are ORing is followed by ANDing of individual term. Each individual is called as maxterm. Number of maxterm depends on number of literal or variables i.e. if equation has three variables then there will be 23 = 8 maxterm. Each maxterm is represented by M i where subscript i is decimal equivalent of natural binary number. The maxterm with complemented variable is taken as and uncomplemented variable is taken as. Table shows possible maxterm for 3 variables equation. A B C Decimal equivalent Maxterm Mi M M 2 M2 3 M3 4 M4 5 M5 6 M6 7 M7 Notation A+B+C A+B+C A+B+C A+B+C A+B+C A+B+C A+B+C A+B+C Using this notation above equation can be written as Y= M2.M3.M4 = πm( i=2,3,6) = πm(2,3,6) Where π is represented ANDing of maxterm Y = (A+B+C)(A+B+C)(A+B+C) Q5. Write truth table and equation in POS form for following minterm. Y = ( A+B+C)(A+B+C)(A+B+C) Y = πm(2,3,6) A B C Decimal equivalent 2 3 Maxterm Mi M M M2 M3 Notation A+B+C A+B+C A+B+C A+B+C Y 5

6 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) M4 M5 M6 M7 A+B+C A+B+C A+B+C A+B+C In general each row of truth table represent that has functional (i.e. output) of logical. It is described by maxterm. Maxterm is sum of all the term. In maxterm representation complemented variable has value and uncomplemented variable has value. Combining all the sum term(maxterm) constructed for variable having value logic by Boolean AND operation results in maxterm canonical form. Q6. Write truth table and equation in SOP form for following minterm. Y= πm(2,3,6,7) Solution: A B C Decimal Maxterm Mi Notation Y equivalent M A+B+C M A+B+C 2 M2 A+B+C 3 M3 A+B+C 4 M4 A+B+C 5 M5 A+B+C 6 M6 A+B+C 7 M7 A+B+C Substitute for all values represented in equation and then AND all maxterm from truth table Y= (A+B+C) (A+B+C) (A+B+C) (A+B+C) Q7.Describe Conversion of SOP to standard SOP form Ans.The SOP form can be converted to standard SOP form by ANDing the term in the expression with term form by ORing the variable and its complement which are not present in that term. Y= AB+AB+BC In first term C is missing, AND it with(c+c) In second term B is missing, AND it with(b+b) In third term A missing, AND it with (A+A) Y = AB(C+C)+AC(B+B)+BC(A+A) = ABC+ABC+ABC+ABC+ABC+ABC Y = ABC+ABC+ABC+ABC+ABC ence above equation is standard SOP equation. Q8.Describe the step Conversion of standard SOP to POS 6

7 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Ans.The Boolean expression in standard SOP form can be converted to standard POS as follows: ) Complement the Boolean expression in standard SOP form which will contain missing minterm. 2) Complement the individual missing minterm to get maxterm and by using demorgan law change OR(sum) to AND (product). Q9.Describe the Conversion of POS to standard POS Ans.The POS form can be converted to standard POS form by ORing the terms in the expression with terms formed by ANDing the variable and its complement which are not present in that term. Y = (A+B)(A+C)(B+C) to standard POS form. st term A+B, C is missing, OR with it C.C 2nd term A+C, B is missing, OR it with B.B 3rd term B+C, A is missing, Or it with A.A Y = (A+B+C.C)(A+C+B.B)(B+C+A.A) = (A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C)(A+B+C) Y = (A+B+C)(A+B+C)(A+B+C)(A+B+C) ence above equation is in standard POS form. Q. Convert Y = ABC+ABC+ABC+ABC+ABC in standard SOP form to standard POS form. Terms in the minterm are m, m3, m4, m5, m7 ) Step:Missing minterm are M,M2,M6. Y = Σ(m,m2,m6) Y = Σ(m,m2,m6) 2) Step2: Complement equation using DMT. Y = π(m,m2,m6) Y = (A+B+C)(A+B+C)(A+B+C) Q.Describe the Conversion of standard POS to Standard SOP form The Boolean expression in standard POS form can be converted to standard SOP form by following, following procedure ) Complement the Boolean expression in standard POS form which will contain missing maxterm. 2) Complement the individual missing maxterm to get the minterm and by using demorgan(dmt) law change AND(product) to OR(sum). Q2. Convert the Boolean expression SPOS to SSOP Y= (A+B+C) (A+B+C) (A+B+C) = (M,M3,M4) Solution 7

8 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) ) Step: Missing maxterm are M,M2,M5,M6,M7. Y = πm,m2,m5,m6,m7. 2) Step2 : Complement expression by DMT. Y = πm.m2.m5.m6.m7 = ABC+ ABC+ ABC+ ABC+ ABC Q3.List the different Boolean expression simplification technique Ans.The SSOP or SPOS equation that has more than just a few products are difficult to reduce by algebraic method. Karnaugh map or K-map method is used for simplification of Boolean expression. It is graphical method of representation. But if number of variables are more than 4 or exceeds 4 than it is difficult to solve using K-map than other following techniques are used. ) Variable entered mapping 2) Quine MC cluskey method ence to solve any Boolean expression there are four methods out of Which two are listed above and other two are ) Algebraic method 2) K-map method. Q4.What is Karnaugh or K-map?Describe Ans. The Karnaugh map, like Boolean algebra, is a simplification tool applicable to digital logic. Maurice Karnaugh, a telecommunications engineer, developed the Karnaugh map at Bell Labs in 953. Karnaugh map or K-map method is used for simplification of Boolean expression. It is graphical method of representation k-map for two, three and four variable is shown in fig. In an n-variable Kmap there are 2n cells. Each cell corresponds to one of the combination of nvariables. In k-map one cell represent one minterm or maxterm. In k-map the variables and all possible values of the variable are indicated to identify cell. GRAY code is used for identification of cell. Sample Two, Three and Four Variable KMaps 232 variable k-map (n=2) F(AB) k-map (n=3) F(ABC) variable 2644-Variable K-Map (n=4) 8

9 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q5.Describe Two Variable K Maps? Ans.2-variable k-map: Table shows truth table for 2 variable equation In 2 variable A & B has four combination corresponds to 4-minterm (or maxterm) and needs four location in k-map. These four locations corresponds to 4 rows of truth table. A is placed in those boxes where minterm are included (Y=) and is included where the minterm are absent or excluded (Y=). ence for above truth table the k-map is K- Map Entry Truth Table A B Y Minterms AB AB AB AB Q6.Describe Three Variable K Maps? Ans. 3 variable k-map : Truth table for three variable k-map is as shown. For three variable equation k-map will have 8 cells as shown(2 3 = 8). A is placed in those boxes where minterm are included (Y=) and is included where the minterm are absent or excluded (Y=). ence for above truth table the k-map is K Map For 3 Variable ABC ABC ABC ABC ABC ABC ABC ABC In this case also enter for minterm's whose Y= and for the maxterm's Truth Table A B C Y 9

10 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q7.Describe Three Variable K Maps? Ans. 4 variable k-map : Table shows truth table for 4-variable Boolean expression. For 4 variable equation k-map has 6 cells i.e. 24 = 6 A is placed in those boxes where minterm are included (Y=) and is included where the minterm are absent or excluded (Y=). ence for above truth table the k-map is Truth Table ABCDY K-Map for 4-Variable is as shown ABCDABCDABCDABCDABCDABC DABCDABCDABCDABCDABCDABC DABCDABCDABCDABCD K Map Q8.Describe the terms Minterm and Maxterm Ans.Minterm A product in as SSOP is called as Minterm. A minterm is a Boolean expression resulting in for the output of a single cell, and s for all other cells in a Karnaugh map, or truth table. If a minterm has a single and the remaining cells as s, it would appear to cover a minimum area of s.

11 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) The example above left shows the minterm ABC, a single product term, as a single in a map that is otherwise s. Another minterm A'BC' is shown above right. The point to noted is that the address of the cell corresponds directly to the minterm being mapped. That is, the cell corresponds to the minterm ABC above left. Above right we see that the minterm A'BC' corresponds directly to the cell. A Boolean expression or map may have multiple minterms. Maxterm A product in as SPOS is called as Maxterm. A maxterm is a Boolean expression resulting in a for the output of a single cell expression, and s for all other cells in the Karnaugh map, or truth table. The illustration above left shows the maxterm (A+B+C), a single sum term, as a single in a map that is otherwise s. If a maxterm has a single and the remaining cells as s, it would appear to cover a maximum area of s. The maxterm is a, not a in the Karnaugh map. A maxterm is a sum term, (A+B+C) in our example, not a product term. Therefore (A+B+C) is mapped into the cell. For the equation Out=(A+B+C)=, all three variables (A, B, C) must individually be equal to. Only (++)= will equal. Thus we place our sole for minterm (A+B+C) in cell A,B,C= in the K-map, where the inputs are all. This is the only case which will give us a for our maxterm. All other cells contain s because any input values other than ((,,) for (A+B+C) yields s upon evaluation. Q9.List the Procedure for placing a minterm in a K-map Ans. Following are the steps to Place Minterm in KMAP identify the minterm (product term) term to be mapped. Write the corresponding binary numeric value. Use binary value as an address to place a in the K-map Repeat steps for other minterms (P-terms within a Sum-Of-Products).

12 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q2.List the Procedure for placing a maxterm in a K-map Ans. Following are the steps to Place Maxterm in KMAP Identify the Sum term to be mapped. Write corresponding binary numeric value. Form the complement Use the complement as an address to place a in the K-map Repeat for other maxterms (Sum terms within Product-of-Sums expression). Q2.List the procedure for writing the Sum-Of-Products reduced Boolean equation from a K-map: Ans : The procedure for writing the Sum-Of-Products reduced Boolean equation from a K-map: Form largest groups of s possible covering all minterms. Groups must be a power of 2. Write binary numeric value for groups. Convert binary value to a product term. Repeat steps for other groups. Each group yields a p-terms within a Sum-OfProducts. Q22.List the the procedure for writing the Product-Of-Sums Boolean reduction for a K-map: Ans.The procedure for writing the Product-Of-Sums Boolean reduction for a K-map: Form largest groups of s possible, covering all maxterms. Groups must be a power of 2. Write binary numeric value for group. Complement binary numeric value for group. Convert complement value to a sum-term. Repeat steps for other groups. Each group yields a sum-term within a Product-OfSums result. Q23.Describe KMAPS the terms PAIR, QUAD and OCTECTS related to Ans.Simplification of logical function with k-map is based on the principle of combining terms in adjacent cells. Two cells are said to be adjacent if they differ in only one variable. Also left two cells and right two cells are adjacent Similarly simplification of logical function is achieved by grouping adjacent s or s in group of 2 i where i=,,2,3 i.e. up to the number of variables. PAIR : Grouping two adjacent ones: If there are two adjacent ones in kmap these can be grouped together and the resulting term will have one literal less than original two terms (minterm) i.e. Pairs. 2

13 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Y= AB+AB Y=AC Other possibilities Y = BC Other possibilities QUAD : Grouping adjacent 4 one s: A quad is group of four s that are ) orizontally or vertically adjacent. 2) s may be end to end. 3) s in form of a square. In quad group two variable and their complement are eliminated. Y = C Y = AB Y= CD Y = Y = Y= 3

14 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) OCTECT: Grouping of adjacent 8 one s: Other than pair there is one more group of adjacent s i.e. the octet. This is a group of 8- s as shown in fig. An oct4et group eliminates three variables and its complement. Y= Y= Y= Overlapping Groups: When there are pairs, quads, octet in a k-map. There is possibility that these group overlap i.e. it is possible to combine a particular in k-map in more than one way. Y= Y= Y= Q24.Describe the term ROLLING, Redundant Group, Corner related to KMAP Ans. Rolling the map :Rolling of map is also possible as shown in fig. In k-map rolling is done so that the left side touches the right side. If you see carefully it is two pair forming quad. Y= Y= Y= Y= Other possibilities Y= Y= Y= Y= 4

15 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Eliminate redundant group After you finished encircling groups, eliminate any redundant group. This is a group whose s are already grouped. In fig. All pairs are grouped, then if you form quad, already all s of quad are grouped in pair. Therefore quad is redundant it should be eliminated. Corner Fold up the corners of the map below like it is a napkin to make the four cells physically adjacent. The four cells above are a group of four because they all have the Boolean variables B' and D' in common. In other words, B= for the four cells, and D= for the four cells. The other variables (A, B) are in some cases, in other cases with respect to the four corner cells. Thus, these variables (A, B) are not involved with this group of four. This single group comes out of the map as one product term for the simplified result: Out=B'C' Q25. Find grouping for following k-map? 5

16 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q26.List the Rules for simplification of k-maps Ans.Rules for Simplification of KMAP 2 variables k-maps ) Any two in adjacent is one then k-map may be k-map combined to represent single variable. 2) Any single on map represent the AND function (product) of two variables. 3) The total expression corresponding to s of map the ORed function(sum) of various variable term which covers all s in the map 3 variable k-maps ) A group of 4-adjacent s can be combined to represent a single variable. 2) A group of 2-adjacent s can be combined to represent 2 variable. 3) Any single on map represent three variable. 4 variable k-map ) Grouping of 8- s represent a single variable term. 2) Group of 4- s represent two variables term. 3) Group of 2- s represent 3 variable term. 4) Individual s represent 4-variable terms. Notes ) Top row is considered to be adjacent to bottom row. 2) Extreme left hand row is adjacent to the extreme right hand row. 3) Always try to overlap group of possible i.e. try to make largest group. 4) Sometimes take care that all the s should not overlap. Q27.Simplify the Following Ans. 6

17 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Circuit Diagram for the Solution obtained Q28. Simplify the following Boolean expression: ) f(a,b,c) = πm(,2,4,6,7) Solution: A B C Y AB Y= 2. f(a,b,c,d) = πm(,,5,7,8,9,2,3,5) Solution: A B C D Y Y= 7

18 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 2. f(a,b,c,d) = πm(,,2,4,5,8,9,) Implementation using NAND and OR gate after simplification. Solution: A B C D Y A B C D Y Y= Q29. Simplify ) f(a,b,c,d) = πm(,3,4,5,6,7,8,9,3,5) Implement using NOR gate Solution: AB f= 2) f(a,b,c,d) = πm(4,5,6,7,8,2) Solution: AB Example Based on KMAPS Realizations Using KMAP Arithmetic Circuits 8

19 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q3.Design alf Adder? Draw Circuit Using Basic Gates Ans. A combinational logic which performs two bit addition is called as ALF ADDER. Rules for addition are ) + = 2) + = 3) + = 4) + = Block Diagram Truth Table 9

20 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Sum Carry KMAP Solving KMAP For Sum and Carry Sum= AB + AB = A+B Carry = AB ence half adder adds two bit at a time. The half adder can be constructed using a AND gate and XOR gate. The output of EX-OR gate gives the sum and the output of And gate gives the carry. The circuit of half adder is as shown we can analyze this circuit for four inputs condition and result are tabulated into truth table as shown. Realization alf Adder using gates alf Adder Using Basic Gates alf Adder Circuit 2

21 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q3.Draw alf Adder Circuit using NAND Gate Ans. alf Adder Using NAND Gate Q32. Design FULL Adder? Draw it circuit diagram suing Basic Gates Ans. A combinational logic circuit that performs arithmetic sum of three input bit is called as Full adder. Full adder has three input A, B, Cin where Cin is carry from previous stage and TWO outputs sum(s) and carry (Co) where Co is output carry for next stage. Fig. Shows truth table and block diagram of full adder. Block Diagram Truth Table 2

22 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) KMAPS For Sum and Carry Sum Expression for Sum Carry Expression For Carry When adding two binary numbers (bits) we may get a carry from one column to the next. To add binary number electronically we need a circuit that can handle 3 bits at a time. This can be done by using a connecting two half adders and an OR gate as shown. For instance suppose A=, B= and C=first half adder gives a carry of and a sum of. The second half adder gives a carry of and sum of. This results in final output of carry = and sum=. Implementation Using Gates Circuits of Full Adder 22

23 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q33.Draw Circuit Diagram of Full adder Using two alf Adders Ans. Block Diagram of Full Adder using alf Adder Circuit Diagram of Full Adder using alf Adder Q34. Design alf Subtractor? Draw Circuit Using Basic Gates Ans. A Combinational logic circuit for the subtraction of two bit is known as half Subtractor. This combinational logic circuit subtracts two bits and produce their difference and borrow. Fig. Shows truth table and block diagram of half Subtractor. 23

24 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com).s.s. Difference (D) (D) Borrow(B) (D) (b) Truth Table KMAPS for alf Subtractor Difference Equation for difference Diff = AB+AB Borrow Equation for borrow Borrow = AB Form truth table it is clear that the difference output is zero whenever input A & B are same and difference output is whenever A and B are different. ence we can use EX-OR gate to produce difference output. The borrow is one only when A= and B= we can get the borrow output by ANDing A and B. Fig. Shows circuit diagram for half subtractor Disadvantages of half Subtractor is that it does not take into account borrow from previous stage. 24

25 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Realization of alf Subtractor Basic Gates Circuit Diagram Q35.Draw alf Subtractor using alf Subtractor Ans. Fig.alf Subtractor using NAND Gate Q36.Design FULL Adder? Draw its circuit diagram using basic Gates Ans. A combinational logic circuit that performs subtraction between two bit number and taking into account the borrow by lower significant stage. The three inputs are A, B, Bin where Bin is borrow by lower stage and two outputs D and Bout. Bout is last stage borrow. Fig. Shows truth table and block of full subtraction. 25

26 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Difference(D) F.S. Borrow(B) Bin Block Diagram Truth Table KMAPS for Difference and Borrow Difference Equation for Difference 26

27 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Borrow Equation for Borrow Equation for borrow Bo = ABBin + ABBin + ABBin + ABBin Bo= ABin +BA + BBin Equation for difference Diff = ABBin + ABBin + ABBin + ABBin Diff = A B Bin A full Subtractor is a circuit that performs the subtraction between two bits taking into accounts that a has been borrowed for the subtraction of previous column. The full Subtractor circuit can be constructed using 2 half Subtractor and a OR gate as shown below. This circuit has 3 inputs and 2 outputs. Input A & B represent the bit to be subtracted and Bin represents borrow required for the subtraction of lower column. Realization Using Gates 27

28 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q37.Draw logical Circuit diagram of FULL adder using alf Adder Ans. Code Convertor Q38.Design Binary to Gray Code Convertor? Ans.Fig.Shows truth table for Binary to gray code converter Truth table 28

29 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Kmaps For G3 output For G2 Output For G output For G output Boolean Expressions are G3 = B3 G2 = B3B2 + B3B2 G = B2B + B2B G = BB + BB Implementation of Binary to gray code converter 29

30 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q39.Design Gray to Binary Code Convertor? Ans.Input is G3G2GG as 4 bit Gray input and B3B2BB as Output.FigShows truth table of 4 Bit Gray to Binary code converter KMAPS Gray to Binary Code Converter Kmap for B3 Expression for B3 B3 = G3 Kmap for B2 Expression for B2 3

31 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Kmap for B Expression for B Kmap for B 3

32 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Expression for B There fore the Expression are B3 = G3 B2 = G2 + G3 B = G + G2 + G3 B = G + G + G2 + G3 Realization Using Gates 32

33 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q4.Design Binary to BCD Code Convertor? Ans. In this design B3B2BB are the input and D4D3D2DD are the output Fig shows the truth table for the same Kmaps for Binary to BD code converter Kmap and Expression for D4 Kmap and Expression for D3 33

34 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Kmap and Expression for D2 Kmap and Expression for D Kmap for D Realization of Binary to BCD converter 34

35 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q4.Design BCD to Excess-3 Code Convertor? Ans.Input for BCD to excess-3 are D3D2DD and output is E3E2EE.Fig Shows the truth table for BCD to Excess-3 Code Converter Kmaps and Boolean Expression for BCD to Excess-3 Code Converter KMap and Expression for E3 Kmap and Expression for E2 KMap and Expression for E Kmap and Expression for E 35

36 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Realization of BCD to Excess-3 Code Converter Multiplexers Q42.Define Multiplexer Ans.Multiplexer ( Data Selector) Multiplex means many into one. A multiplexer is a logic circuit that accepts several data inputs and allows only one of them at a time to get through to the output. The selection of the desired data input depends on the control inputs. The data input selected is controlled by the set of the select inputs. Basically it acts as digitally controlled multiposition switch. ence we can say that a multiplexer (MUX) is a digital switch which connects data from one of N sources to the output. A number of select inputs determine which data source is connected to the output. Total number input for N select are 2 N.ie if a Mux has 2 select Lines then 22 = 4 data input are there for the mux. 36

37 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Do S2 D Y D2 D3 S S2 S Y Do D D2 D3 Truth Table Block Diagram Q43.State the Necessity of Using Multiplexer Ans. Multiplexer is used in the electronic systems, where the digital data is available on more than one lines, to route this data over a single line.ence we require a circuit which select one of the many inputs at a time. Such circuit should have many inputs, One output and some select inputs.multiplexer improves the reliability of the digital system because it reduces the number of external wired connections. Q44.Draw 4: Mux? and Describe its operation Ans.Fig Shows Block Diagram of 4: Mux.. It has 4 input D3D2DD, 2. Two select lines(ss) and 3. One data out put Line Y Do D D2 Y D3 S S2 37

38 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Expression for 4:Mux Y = SoSDo + SoSD + SoSD2 + SoSD3 38

39 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Fig. 4: Multiplexer Operation : When data is applied to data input depending upon select signal data is switched to output Y.When S=,S= data on Y output is from data line D ie Y = D 2.When S=,S= data on Y output is from data line D ie Y = D 3.When S=,S= data on Y output is from data line D2 ie Y = D2 4.When S=,S= data on Y output is from data line D3 ie Y = D3 Q45.Draw the Logical circuit diagram of 8: Mux with Control Signal? Describe its operation. Ans. Fig Shows Block Diagram of 8: Mux It has 8 input D7--D Three select lines(s3ss) and One data out put Line Y E is the Strobe or Select or Control line. 39

40 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Block Diagram Truth Table Operation. When the Strobe Signal or Control signal is made Low(), the multiplexer get disabled and output becomes logic (Y = ) even if data is connected to any input. 2. For Enabling the MUX the control or Strobe input is to be made igh. 3. When data is applied to data input depending upon select signal data is switched to output Y 4. When S2 =,S=,S= data on Y output is from data line D ie Y = D 5. When S2 =, S=,S= data on Y output is from data line D ie Y = D 6. Similarly When S2= S=,S= data on Y output is from data line D7 ie Y = D7 Expression for 8: Mux Y = E.(S2SS.D + S2SS.D + S2SS.D2 + S2SS.D3 + S2SS.D4 + S2SS.D5 + S2SS.D6 + S2SS.D7 ) Logical Circuit Diagram of 8: Mux 4

41 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q.DraQ46.Draw Block Diagram, Logical Diagram of 6: MUx, Also write its Boolean expression Ans. Fig Shows Block Diagram of 6: Mux It has 6 input D5--D Three select lines(s4s3ss) and One data out put Line Y E is the Strobe or Select or Control line. Block Diagram Truth table Operation. When the Strobe Signal or Control signal is made Low(), the multiplexer get disabled and output becomes logic (Y = ) even if data is connected to any input. 2. For Enabling the MUX the control or Strobe input is to be made igh. 3. When data is applied to data input depending upon select signal data is switched to output Y 4. When S3=, S2 =,S=,S= data on Y output is from data line D ie Y = D 5. When S3=,S2 =, S=,S= data on Y output is from data line D ie Y = D 6. When S3=,S2 =, S=,S= data on Y output is from data line D8 ie Y = D8 4

42 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 7. Similarly When S3=,S2= S=,S= data on Y output is from data line D5 ie Y = D5 Boolean Expression for 6: Mux Y = E.(S3S2SS.D + S3S2SS.D + S3S2SS.D2 + S3S2SS.D3 + S3S2SS.D4 + S3S2SS.D5 + S3S2SS.D6 + S3S2SS.D7 + S3S2SS.D8 + S3S2SS.D9 + S3S2SS.D + S3S2SS.D + S3S2SS.D2 + S3S2SS.D3 + S3S2SS.D4 + S3S2SS.D5 ) Logical Circuit Diagram of 6: Mux 42

43 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q47.List IC for Multiplexer Ans Sr.No IC. No Description Output Quad 2: Mux Quad 2: Mux Dual 4: Mux Dual 4: Mux 8: Mux 6: Mux Same as Input Inverted Output Same as Input Inverted as Input Complementary Outputs Inverted Outputs Q48.Draw the Pin diagram of IC 7453 and Describe Ans. IC 7453 is a Dual 4: MUX.. It has two four line inputs IA,IA,I2A,I3A and IB,IB,I2B,I3B 2. There are two outputs ZA & ZB. 3. Two strobes EA & EB for section and section respectively 4. Two Select lines S & S are common for both the sections. 5. To enable the particular section the strobe input of that section must be held active low Pin diagram Truth Table 43

44 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Internal Logical Diagram Q49.Draw the Pin diagram of IC 745 and Describe Ans. IC 745 is a 6: MUX.. It has 6 data inputs E-E5 and four select lines A,B,C,D. 2. The output W of this circuit is the inversion of the data input selected. 3. An input line Dn. is selected corresponding to decimal number N representing D,C,B,A. 4. G is the strobe signal which is to be maintained LOW Pin diagram 44

45 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Truth Table Logical Symbol Q5.Draw the Pin diagram of IC 745 and Describe Ans.IC 745A - 8: Mux. It has 8 data input D7 to D 2. Three (3) select inputs C,B,A 3. Two (2) outputs Y & W ( Complementary outputs) 4. To enable the MUX the strobe must be held active low. Pin Diagram Logical Diagram Truth Table 45

46 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q5.What is Multiplexer Tree? State its Necessity Ans.Maximum input mux IC available is 6 input to output i.e. 6: Mux is available. Some time it is required to have multiplexer more than 6 input for example 32: or 64: or 256:. This requirement is meet by forming a tree like connection of 6: mux or 8: or 4: mux i.e. available. This is achieved with help of enable/strobe (G) input of mux. Following example shows some of such examples. Q52. Design of mux tree 32: mux using 6: Ans.Truth Table of 32: Mux Truth table: MUX selected MUX 2 selected S4 S3 S S S Y D D D2 D3 -D5 D6 D7 D9 -D3 Fig.32: Mux Tree Using 6: 46

47 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) For S4 = Lower multiplexer is enable which transfer any of 6 input to output Y depends on DCBA select input. At this time S4 for MUX2 is high it is inactive ( S4 = ). When S4 = or made high upper mux or mux is inactive disabled whereas lower operates(d2) operates as 6: mux and transfer any of 6 inputs to one output Y depending on select input. Output of both mux are ORed to get output hence 32: mux can be implemented. Q53.Design 6: Mux using 8: Mux Ans. S3 S2 S MUX selected MUX 2 selected S Y D D D2 D3 -D7 D8 D9 D -D5 47

48 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Fig. Mux 6: using 8: For S3 = right multiplexer is enable which transfer any of 8 input to output Y depends on DCBA select input. At this time S3 for MUX2 is high it is inactive ( S3 = ). When S3 = or made right mux or mux is inactive disabled whereas left operates(m2) operates as 8: mux and transfer any of 8 inputs to one output Y2 depending on select input. Output of both mux are ORed to get output hence 6: mux can be implemented. Q54. Design 6: Mux Tree using 4: Mux Ans. Truth table 6: Mux Select MUX D input Select MUX D input Select MUX D2 input Select MUX D3 input S S S S D st 4 output D2 2nd 4 output D2 3rd 4 output D3 4th 4 output 48

49 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) When S3S2SS is then Do input of the First Mux is selected since S3S2SS= and Since S3S2= the Do input of the MUX5 is select to transfer at the output Similarly when S3S2 = then D input of the MUX D5 is selected for the output when S3S2= then D2input of the MUX D5 is selected for the output when S3S2= then D3 input of the MUX D5 is selected for the output But for all S3S2 input the range for the S2S= - to. Therefore 6 input of the input multiplexer are transferred to the output through 4 input of the output multiplexer(mux5) Q55. Design 8: Mux Tree using 4: Mux Ans. The cascading of two 4: multiplexer results in 8 : multiplexer as shown in Fig.. There are in all eight data inputs (D7 through D), 2. The select lines S and S of both 4: multiplexers are connected in parallel whereas a third select input s2 is used for enabling one multiplexer at a time. 3. S2 is connected directly to the enable (E) terminal of MUX- whereas S2 is connected to the enable terminal of MUX-2. 8: Mux Tree using 4: Mux Truth Table Q56. Implementation of Boolean Expression Using Multiplexer. F(d,c,b,a) = Σm(2,4,5,7,,4) 2. F(c,b,a) = Σm(,2,4,6) Ans.General step for Implementation. Depending on the function see the variable required i.e. in above equation there are 4 variables 49

50 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 2. In truth table write s for all minterm the equation 3. Connect all the input whose output are s to logic igh i.e. +5v supply 4. Remaining input are connected to logic i.e. grounded. 5. Then verify the truth table. Equation : F(d,c,b,a) = Σm(2,4,5,7,,4) for the above equation Circuit diagram : Mux needed is of 4 select inputs Truth Table D C B A Y D D D2 D3 D4 D5 D6 D7 D8 D9 D D D2 D3 D4 D5 O/P ( refer Diagram on Page A /Ch3) Equation 2 : F(c,b,a) = Σm(,2,4,6) Truth Table Circuit diagram : Mux needed is of Three select input D C A Y D D D2 D3 D4 D5 D6 D7 ( refer Diagram on Page A /Ch3) Fig: Mux diagram for Boolean expression 5 O/P

51 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q57.State Advantages and application of the Multiplexer Ans. Following are the Advantages of Multiplexer. Simplification of the logic expression is not required 2. It minimize the IC package count 3. Logic design is simplified For using mux as a logic element, either the truth table or one of the standard form of the logic expression must be available. The design procedure is given below. Identify the decimal number corresponding to each minterm in the expression 2. The input lines corresponding to these numbers are to be connected to logic 3. All other input lines are connected to logic 4. The inputs are applied to the select input Application of Multiplexer. Data Routing 2. Logic Function generator 3. Control Sequencer 4. Parallel-to-serial convertor 5. Boolean Expression Implementation 6. Used in ADC /DAC 7. In designing of Combinational Logic Circuits 8. Used in data logger and Dataacquition System.Data routing: Multiplexers can be used to route data from one of several sources to one destination. 2.Logic function generator: It can also be used to implement logic functions in sum-of-products form directly from a truth table without the need for simplification. The logic variables are used as the select inputs and each data input is connected permanently IG or LOW. 3.Control sequencer: A multiplexer can also be used as a part of control sequencer. 4.Parallel-to-serial converter: Digital systems that process data in parallel form take very less time. In order to transmit the information over long distances, the parallel arrangement is undesirable as it requires a large number of transmission lines. 5.Boolean Expression Implementation : Multiplexer can be used for implementation of Boolean Expression since it reduces hardware and number of connection which makes debugging easy. 5

52 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 6.Used in ADC/DAC : For increasing number of input and Outpuy. Example is ADC88, 89 Therefore data in parallel form is converted to serial for using multiplexers. Demultiplexer Q59.What is Demultiplexer?Explain :4 Demultiplexer? Ans.Demultiplexer ( Data Distributor ) : Demux Demultiplexer is exactly reverse to that of MUX. Demultiplexer means into many. A demultiplexer is a logic circuit with one input and many outputs. It accepts a single input and distributes it over several output depending upon the control inputs. It performs Function opposite to Multiplexer. Types of Demultiplexer are. line - to - 4 line (:4 ) Demultiplexer 2. line - to - 8 line (:8 ) Demultiplexer 3. line - to - 6 line (:6 ) Demultiplexer Block Diagram Truth Table Operation. Din is 2. Din is 3. Din is 4. Din is connected to Y when Connected to Y when connected to Y2 when Connected to Y3 when Boolean Expression Y Y Y2 Y3 = = = = SS=, SS=, SS=, SS= Logical Diagram SSDin SSDin SSDin SSDin 52

53 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q6.Draw and Explain :8 DEMux? Ans.Fig Shows the Block diagram and Truth table of :8 demux. It has One data input Din 2. One Strobe Signal for Enabling the DEMUX, it should be igh for normal operation 3. Three Select Signals S2SS for Selecting the output to get connected with input Block Diagram Truth Table 53

54 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Logical expression Y7 Y6 Y5 Y4 Y3 Y2 Y Y = = = = = = = = Logical Diagram E.S2SS.Din E.S2SS.Din E.S2SS.Din E.S2SS.Din E.S2SS.Din E.S2SS.Din E.S2SS.Din E.S2SS.Din Operation : When E =, all the AND gate has there one input as Logic O make all output of the AND gate as LOW. ence DEMUX is disabled For Normal Operation E =.Operation is as follows. Din is connected to Y when S3SS=, 2. Din is Connected to Y when S3SS=, 3. Din is connected to Y2 when S3SS=, 4. Din is Connected to Y3 when S3SS= 5. Din is Connected to Y4 when S3SS= 6. Din is Connected to Y5 when S3SS= 7. Din is Connected to Y6 when S3SS= 8. Din is Connected to Y7 when S3SS= Q6.Draw and Explain :6 DEMux? Ans. Fig Shows the Block diagram and Truth table of :8 demux. It has One data input Din 2. One Strobe Signal for Enabling the DEMUX, it should be igh for normal operation 3. Four Select Signals S3S2SS for Selecting the output to get connected with input 54

55 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Truth Table: Truth Table 55

56 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Logical Expressions Logical Diagram 56

57 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Yo = ABCDDIn Y = ABCDDIn Y2 = ABCDDIn Y3 = ABCDDIn Y4 = ABCDDIn Y5 = ABCDDIn Y6 = ABCDDIn Y7 = ABCDDIn Y8 = ABCDDIn Y9 = ABCDDIn Y = ABCDDIn Y = ABCDDIn Y2 = ABCDDIn Y3 = ABCDDIn Y4 = ABCDDIn Y5 = ABCDDIn Q62.List Some IC of Demultiplexer Ans.Demultiplexer IC's 57

58 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Ic No Description :8 Demux (3 line to 8 line Decoder) Dual :4 Demux (2 line to 4 line Decoder) Dual :4 Demux ( Dual 2:4 Line Decoder ) Dual :4 Demux ( Dual 2:4 Line Decoder ) :6 Demux (4 Line to 6 Line Decoder) :6 Demux (4 line to 6 Line Decoder) Output Inverted Output Inverted Output Y - Inverted Inputs 2Y - Same as Input Open Collector Y - Inverted Inputs 2Y - Same as Input same as Input Open Collector Same as Input 58

59 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q63.Describe the demultiplexer IC 7455 ie :4 Demux Ans. Truth Table 59

60 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q64.Describe IC 7454 :6 demux Ans. The pin configuration of this IC is as shown in Fig..A, B, C, D are the four input lines, G and G2 are the active low strobe lines. 2.Q-Q5 are the 6-active low output 3.This is a TTL IC hence needs a unipolar power supply of + 5 Volts. 4.These ICs can be used as : 6 demultiplexer. To do so, one of the strobe inputs (G or G2) is used as data input (Din line and the input lines A, B, C, D act as select lines. The other strobe input should be connected to logic low level. 5.If G or G2 or both are high then all the outputs will be high (inactive). 6.74LS54 are ideally suitable for implementing high performance memory decoders. 7.All the inputs are buffered and input clamping diodes are provided. 6

61 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Truth Table 6

62 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Logical Diagram Q65.Describe what is Demultiplexer Tree and state its necessity Ans. Since :6 is maximum available demux (4:6)/decoder to meet the larger input needs there should be provision for expansion. This is made possible by using enable input terminal.ence when such demux are cascaded they are called as Demux Tree. IT is Needed for Expansion of Demux for higher number of output then the commercial available. Q66.Design :8 demux using :4 demux Ans.Fig.Shows truth table of :8 using :4 Demux. Two :4 demux are needed. 62

63 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Design. The select lines S and S of the two : 4 deniultiplexers are connected in parallel with each other and S2 is used for selecting one of the two :4 demultiplexers. 2. S2 is connected directly to Enable (E) input of Demux 2 whereas inverted S2 is connected to the enable input of Demux. Logical Diagram of :4 using :8Demux 63

64 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q67.Design :32 demux using :8 demux Ans.Fig.Shows Truth table of :32 using :8 Demux.It requires total 5 select Line out of which three(s2ss) of :8 are used to select the output of individual demux and two select(s4s3) line of input demux is used to select the Demux ie any one out of four as shown in truth table Truth table Demux Tree Q68.Compare Mux and Demux Ans. SrNo Parameter Logic Circuit Data Input Output Select Input Relation Between Select Input and Output Operation 7 Application MUX Combinational Logic Many ie N Input One output M select Lines N=2M DEMUX Combinational Logic One Input Many output ie N M Select Lines N=2M Many into ie One into Many ie Data DataSelector Distributor. Boolean. Boolean Expression Expression implementatio implementation 64

65 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) n.one Equtaion per MUX 2. In time division multiplexing at the sending end..many Equaton can be implemented using one DEMUX and Some gates. 2. In time division multiplexing at the receiving end Q69.Implement Following Boolean Expression using DEMUX F = Σm(,,3,5,6) F2 = Σm(,,2,4,6) F3 = Σm(,2,3,6) Ans.When Boolean expression are to be implemented using demux additional logic gates are need and also more than Boolean expression can be implemented using single Demux. General steps :. Since output are not more then 7 we can use :8 demux. 2. Take the minterm output from the input of the OR gate so that output will come for the minterm specified in the equation. 3. ence to implement above three equation three OR gates are needed. 4. Fig shows the circuit diagram. // Logical Diagram are needed (Refer page B / Ch3) Encoder Q7.What is Encoders? Describe its Operation Ans.The opposite of the decoding process is called Encoding and is performed by a combinational logic circuit called an Encoder. In other words Encoders is a logic circuit that provide appropriate code (Binary or BCD etc) as the output for each input signal applied. The process is reverse of decoding. When more then one input are applied at a time, internal hardware will check this condition and the highest priority input will be taken into account and converted in format at the output.it has N Input and M output. 65

66 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q7.List Different types of Encoders Ans. Types of encoders. Priority encoders. 2. Decimal to BCD encoder. 3. Octal to binary encoder, 4. exadecimal to binary encoder. Q72.What is Priority Encoder?Describe it Operation Ans.Fig.Shows Block Diagram of 4:2 Priority Encoder Operation. What will happen if all input are made simultaneously igh.ere priority comes into picture that output will be corresponding to highest priority input. 2. Priorities are given to the input lines. If two or more input lines are at the same time, then the input line with highest priority will be considered. 3. The block diagram of a priority encoder is shown in Fig and its truth table is shown in Fig. 4. There are four inputs D through D3 and two outputs Y and Y Out of the four inputs D3 has the highest priority and D has the lowest priority. 5. That means if D3= then Y Y = irrespective of the other inputs. Similarly if D3 = and D2= then YY = irrespective of the other inputs. 6. Complete operation can be Understood from truth table. Q73.Describe the operation of 8:3 encoder 7448 Ans :3 A A A2 Figure shows 8:3 encoder which has 8 active low input and 3 output lines.when input line goes low, output is.when input line 5 goes low, output is.owever this encoder is Unable to provide appropriate code if two or more input lines are activated simultaneously. The encoder which resolves this problem of simultaneous input is called 66 as priority encoder. Figure shows logic symbol of 74LS48,8:3 priority encoder.

67 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 67

68 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Input Gnd Vcc A A A2 74LS48 Eo E G E L L L L L L L L L X X X X X X X L L X X X X X X L X X X X X L X X X X L X L X X X L X X L A 2 L L L L Output Enable A A Eo L L L L L L L L L L L L L L L GS L Q74.Describe the operation of decimal to BCD Encoder Ans. Decimal to BCD encoders Decimal A BCD B C (Refer Page C hapter3) Fig : Decimal to BCD Encoder Fig : Truth Table Figure shows a decimal to BCD encoder when push button 3 is pressed the C & D OR gates have high inputs therefore output ABCD=. Similarly when push button 9 is pressed A & D OR gates will have high inputs therefore we get ABCD=. IC 7447 is a decimal to BCD encoder and is also called priority encoder. 68 D

69 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q75.Describe IC 7447 Priority Encoder Ans.Fig. Shows IC 7447 Decimal to BCD Encoder.It is also called as :4 Encoder. Functional Diagram Pin Diagram Truth Table Operation. A9 to A are the inputs with A having the lowest priority and A9 having the highest priority. 2. From truth table we conclude that all nine inputs are ACTIVE LOW representing decimal digit from to 9. In response to input, chip produces inverted BCD code corresponding to highest numbered ACTIVE INPUT. 69

70 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 3. When all inputs are held high, output D C B A i.e. DCBA () (). Thus a decimal is represented. 4. The truth table also shows the normal BCD output which is actually the inversion of the output of IC 5. As A9, is the highest priority input, if A9 = then the remaining input lines are treated as don t care and the inverted BCD output is produced as DCBA =. The Same logic is applicable to the other inputs. Q76.Describe IC 7448 Octal to Binary Encoder Ans.Figure shows octal to Binary Encoder Truth table and Pin diagram Pin Diagram Pin Description Truth Table Description. I7 to I are the eight active low inputs. 7

71 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 2. A2 to A, are the three active low outputs. 3. El is the active low enable input terminal. If El is at logic then it will force all the output to become high i.e. inactive, This feature can be used to allow some time for the new input data to settle down. 4. GS is the group signal output. It is used for indication that one of the inputs is low i.e. active. 5. If all the inputs are inactive (high) the enable output (EO) goes to logic. Decoder Q77.What is Decoder?Describe with block diagram. Ans. A decoder is digital logic circuit that convert N-bit binary input code in to M lines. ere each output lines will be activated for only one of the possible combination. It is combinational Logic Circuit. Decoder is identical to a demultiplexer without any data input. It performs operations which are exactly opposite to those of an encoder.for N input of the decoder there will be M = 2 N output. Fig.Shows Block Diagram of 2:4 Decoder. It has 2 input A,B and Four output D,D,D2,D3. Fig shows the generalized block diagram. Boolean Expression Logical Diagram DO = AB D = AB D2 = AB D3 = AB 7

72 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q78.List different ways a decoder can be referred Ans.Decoder can be referred in several other ways Example 3:8 decoder it accepts three lines and gives output eight lines.. it is also called as of the 8 decoder 2. it may also be called as Binary to octal decoder 3. if it is 4:8 decoder then it is called as binary to hexadecimal decoder. Q79.Describe the 3:8 decoder with its logical Diagram Ans.Fig. Shows truth table and Logical diagram of the 3:8 Decoder Truth Table Block Diagram Design : 3:8 decoder has. 3 input CBA 2. 8 output D7 to D 72

73 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Logical Diagram Q8.Describe IC :8 decoder Ans. Pin Diagram Truth Table Description. The pin configuration of the 3:8 decoder IC 7438 is shown in Fig 2. A2 A A are the three the three input lines. To this we apply the 3-bit binary data to these inputs. 3. Oo-O7 are the 8-output active low lines(output is Low). 4. There are three enable inputs out of which E, E2 are the active low enable inputs whereas E3, is an active high enable input. 5. For Normal operation or for IC to selected for Operation E=E2 = (LOW) and E3 = (igh) 6. It can be used as demux by making either E or E2 or E3 as Data input. If E and E2 are made as data input then it will be active Low and If E3 is made as data input then it is Active igh. 73

74 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) 7. Truth table as shown in Fig. Q8.Describe IC 7439 Dual :4 decoder Ans.Fig Shows Pin diagram and Functional Diagram of It has. Two Enable Signal En and 2EN 2. 4 Input signal, Two for each section. (A,B and 2A,2B) 3. 8 active LOW output Four for each section.(yo,y,y2,y3 and 2YO,2Y,2Y2,2Y3) Pin Diagram Functional Diagram 74

75 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Truth Table Q82. Implement the Following Boolean Expression using Decoder F(A,B,C) = (,4,7) +D(2,3) F2(A,B,C) = (,5,6) F3(A,B,C) = (,2,4,6) Ans. 75

76 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q83.ow Demux can be used as Decoder Ans. Q84.What is 7 Segment display? List its type with diagram Ans. 76

77 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q85.Describe the Operation of BCD to 7 Segment Decoder Ans. For Common Anode Seven Segment Display. The display used is common anode type. 2. The decoder accepts a four bit BCD and converts it to a seven bit code suitable for the seven segment display (a to g) and drives the display. 3. For segment to glow the corresponding decoder output goes low, and sinks current (for common anode display). 4. A current limiting resistance is connected in series with each segment. For Common Cathode Seven Segment Display. Fig. shows the circuit arrangement to drive a common cathode display using a BCD to seven segment decoder / driver. 2. The outputs of this decoder are active high. Therefore whenever a segment is to be turned on. The corresponding output of the decoder goes high. 77

78 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com). The decoder has to source the current in this case the common anode point is connected to Vcc ie positive supply voltage. 2. A Current limiting resistor is externally connected in series with each segment 3. The cathode of segment to be turned on are connected to ground. For example for displaying 7 the cathode of each segment a,b,c should be connected to ground. Q86.List IC used as Decoder/Drive for Driving 7 segment Displays Ans.Following are the IC used for BCD to Decimal conversion Q87.Describe the BCD to Decimal Decoder IC 7445 Ans.IC 7445 (BCD to Decimal decoder) These BCD-to-decimal decoders/drivers consist of eight inverters and ten, four-input NAND gates. The inverters are connected in pairs to make BCD input data available for decoding by the NAND gates. Full decoding of BCD input logic ensures that all outputs remain OFF for all invalid ( 5) binary 78

79 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) input conditions. These decoders feature high-performance, NPN output transistors designed for use as indicator/relay drivers, or as open-collector logic-circuit drivers. The high-breakdown output transistors are compatible for interfacing with most MOS integrated circuits. Features. Full decoding of input logic 2. 8 ma sink-current capability 3. All outputs are off for invalid BCD input conditions Fig.Shows BCD -to- Decimal decoder/driver Fig.Truth Table 79

80 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) It is also called 4: decoder and is similar 4:6 decoder but with only output lines. Since BCD numbers are from to. When ABCD= the Y AND gate has all its input high producing a high output. Similarly when ABCD= the Y9 AND gate will produce high output. IC 7445 is a BCD to DECIMAL decoder here all the outputs are active low. For forbidden numbers all the output goes high. Depending upon the ABCD inputs representing the decimal number corresponding output will go low. Q88.List IC which are used to convert BCD to 7 segment and Driver 7 segment display Ans.BCD to 7 segment Decoder and Driver ICs. Q89.Describe the IC 7447 BCD-7Segment Decoder/Driver used to interface common Anode 7 Segment Display Ans. Features of Open collector output drive the indicator directly 2. Lamp test Provision 3. Leading and Trailing zero Suppression The output are active low therefore these IC is used for common Anode type of displays. 8

81 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) The functions of other pin in the IC are as below: LT: This is called lamp test terminal and is used for segment testing. If it is connected to logic level. All segments of display connected to the decoder will be ON. For normal decoding operation this terminal must be connected to logic level. RBI: For normal decoding operation this is connected to logic level. If it is connected to logic level, the segment outputs will generate the data for normal 7 segment decoding for all BCD inputs except whenever the BCD inputs corresponds to the seven segment display switches OFF. This is used for zero blanking in multi digit displays. BI: If it is connected to logic level the display is switched OFF irrespective of BCD inputs. This is used for conserving the power in multiplexed displays. RBO: This output is used for cascading purpose and is connected to RBI terminal of the succeeding stage. Truth Table Q9.What is ALU? Describe ALU IC 748? Ans. A very popular and widely used combinational circuit is ALU which is capable of performing arithmetic as well as logical operations. This is the heart of any micro processor. Figure shows the block diagram of 748 ALU. 8

82 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Fig : Arithmetic and Logic Unit Description of ALU The block diagram of 74LS8 ALU is as shown. This circuit can be used for both positive as well as negative logic. The functions of various input and output control lines are as follows: Inputs: a) A-A3 and B-B3 are four bit binary data inputs. b) Cn-carry input. This is active low i.e. if carry input is to be given it should be at logic. Outputs a) F-F3 are 4 bit binary data output. b) Cn+4 is Carry output-for the addition operation a logic on this line indicates a carry output. For the subtraction operation it indicates sign of output logic on this line indicates positive result and logic indicates a negative result in 2's complement form. c) A=B is Equality output. Logic on this line indicates A=B. It is used for comparator operation. d) G - Carry generate output. e) P - Carry propagate output. These outputs are used when a number 748 circuits are used in cascade. The 748 can be cascaded by connecting the carry-out of a stage to the carry-in of the succeeding stage. Control Lines 82

83 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) a) Select line: It has four function select lines, S3,S2,S,S, so to select any one of the operations. b) Mode Control -M : If M= Arithmetic operations are performed & if M= logical operations are performed. Fig.Show Truth table of ALU Q9.What is Digital Comparator? Describe Digital Comparator IC 7485? Ans.Comparator is a circuit which compares two inputs. Figure shows which compares two bit a digital comparator digital signals. 83

84 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com). Whenever A >B then output marked A>B will be while other outputs are zero. 2. Whenever A=B ( or ) then output marked A=B will be one 3. Whenever A<B then output marked A<B will be one while other outputs are zero. 4. IC 7485 is a 4 bit digital comparator. 5. A and B are 4 bit binary inputs while A>B,A=B and A<B are its outputs. 6. This IC is provided cascading facility with another digital comparator. Fig.Functional Diagram of IC

85 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Truth table 85

86 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) Q92.Draw 5 bit comparator using IC 7485 Ans.Fig. Shows 5 bit comparator Q93.what is Parity? Describe even and Odd parity Ans. In mathematics, parity refers to the evenness or oddness of an integer, which for a binary number is determined only by the least significant bit. In telecommunications and computing, parity refers to the evenness or oddness of the number of bits with value one within a given set of bits, and is thus determined by the value of all the bits. It can be calculated via an XOR sum of the bits, yielding for even parity and for odd parity. This property of being dependent upon all the bits and changing value if any one bit changes allows for its use in error detection schemes. In quantum mechanics, parity corresponds to the behavior of the wave function under reflection. In computers, parity (from the Latin paritas: equal or equivalent) refers to a technique of checking whether data has been lost or written over when it's moved from one place in storage to another or when transmitted between computers Start Data Data Data Data Data Data Data Data Parity Stop A parity bit is a bit that is added to ensure that the number of bits with the value one in a set of bits is even or odd. Parity bits are used as the simplest form of error detecting code. The parity bit, unlike the start and stop bits, is an optional parameter, used in serial communications to determine if the data character being transmitted is correctly received by the remote device. 86

87 Prof.Manoj Kavedia ( ) (urallalone@yahoo.com) There are two variants of parity bits. even parity bit and 2. odd parity bit. When using even parity, the parity bit is set to if the number of ones in a given set of bits (not including the parity bit) is odd, making the entire set of bits (including the parity bit) even. When using odd parity, the parity bit is set to if the number of ones in a given set of bits (not including the parity bit) is even, making the entire set of bits (including the parity bit) odd. In other words, an even parity bit will be set to "" if the number of 's + is even, and an odd parity bit will be set to "" if the number of 's + is odd Q94.Describe the IC 748 parity Generator Ans.Fig Shows functional and Pin diagram of IC 748 Functional Diagram Pin Diagram Figuregives the block diagram of 748 in which there are. Eight parity inputs A through and 2. Two cascading inputs. 3. There are two outputs EVEN and ODD. Its function table is given in Table Q95.Design 9 bit ODD parity generator using