Philips Semiconductors Programmable Logic Devices

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1 L, R, R, R PLUSRD/- SERIES FEATURES Ultra high-speed t PD =.ns and f MAX = MHz for the PLUSR- Series t PD = 0ns and f MAX = 0 MHz for the PLUSRD Series 00% functionally and pin-for-pin compatible with industry standard 20-pin PAL ICs Power-up reset function to enhance state machine design and testability Design support provided via SNAP and other CAD tools for Series 20 Field-programmable on industry standard programmers Security fuse Individual 3-State control of all outputs DESCRIPTION The Philips Semiconductors PLUSXX family consists of ultra high-speed.ns and 0ns versions of Series 20. The PLUSXX family is 00% functional and pin-compatible with the L, R, R, and R Series devices. The sum of products (-) architecture is comprised of programmable gates and fixed gates. Multiple bidirectional pins provide variable input/output pin ratios. Individual 3-State control of all outputs and registers with feedback (R, R, R) is also provided. Proprietary designs can be protected by programming the security fuse. The PLUSR, R, and R have D-type flip-flops which are loaded on the Low-to-High transition of the clock input. In order to facilitate state machine design and testing, a power-up reset function has been incorporated into these devices to reset all internal registers to Active-Low after a specific period of time. The Philips Semiconductors State-of-the-Art oxide isolation Bipolar fabrication process is employed to achieve high-performance operation. The PLUSXX family of devices are field programmable, enabling the user to quickly generate custom patterns using standard programming equipment. See the programmer chart for qualified programmers. The SNAP software package from Philips Semiconductors supports easy design entry for the PLUSXX series as well as other PLD devices from Philips Semiconductors. The PLUSXX series are also supported by other standard CAD tools for PAL-type devices. Order codes are listed in the Ordering Information table. DEVICE NUMBER DEDICATED INPUTS COMBINATIAL OUTPUTS REGISTERED OUTPUTS PLUSL 0 ( I/O) 0 PLUSR 0 PLUSR 2 I/O PLUSR I/O DERING INFMATION DESCRIPTION DER CODE DRAWING NUMBER 20-Pin Plastic Dual-In-Line 300mil-wide PLUSRDN PLUSRDN PLUSRDN PLUSLDN PLUSR N PLUSR N PLUSR N PLUSL N 00B 20-Pin Plastic Leaded Chip Carrier (PLCC) PLUSRDA PLUSRDA PLUSRDA PLUSLDA PLUSR A PLUSR A PLUSR A PLUSL A NOTE: The PLUSXX series of devices are also processed to military requirements for operation over the military temperature range. For specifications and ordering information, consult the Philips Semiconductors Military Data Book. 000E PAL is a registered trademark of Advanced Micro Devices, Inc. September 0,

2 L, R, R, R PLUSRD/- SERIES PIN CONFIGURATIONS PLUSL PLUSR I I 2 9 O I 0 2 D 9 3 B I 3 D B D ARRAY B B 3 ARRAY D D 3 I B 2 D 2 I 3 B I D 3 I 9 2 O 0 I 9 D I 9 0 PLUSL PLUSR I I 0 O I I B I ARRAY OUTPUTS B B B 3 ARRAY OUTPUTS 3 I B 2 I I I 9 O 0 B I 0 SYMBOL I O B DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground SYMBOL I O B DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground September 0, 993 3

3 L, R, R, R PLUSRD/- SERIES PIN CONFIGURATIONS PLUSR PLUSR I B I B I 3 D I 3 B D D ARRAY D D 3 ARRAY D D 3 D 2 D 2 I D 3 I 3 B I 9 2 B 0 I 9 2 B PLUSR PLUSR I I 0 B I I 0 B B ARRAY OUTPUTS 3 ARRAY OUTPUTS 3 I 2 I I B 0 I B 0 B SYMBOL I O B DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground SYMBOL I O B DESCRIPTION Dedicated Input Dedicated combinatorial Output Registered output Bidirectional (input/output) Clock input Output Enable Supply Voltage Ground September 0, 993 3

4 L, R, R, R PLUSRD/- SERIES LOGIC DIAGRAM PLUSL I O I 2 B 3 B 23 2 PRODUCT TERMS (0 3) 3 32 B B B 2 I 3 B I 2 O 0 3 I 9 I INPUTS (0 3) NOTES:. All unprogrammed or virgin gate locations are pulled to logic Programmable connections. September 0,

5 L, R, R, R PLUSRD/- SERIES LOGIC DIAGRAM PLUSR 0 D 9 I 0 2 D I 3 D 23 2 PRODUCT TERMS (0 3) 3 32 D D D 2 D 3 I D I INPUTS (0 3) NOTES:. All unprogrammed or virgin gate locations are pulled to logic Programmable connections. September 0, 993 0

6 L, R, R, R PLUSRD/- SERIES LOGIC DIAGRAM PLUSR 0 9 B I 0 2 D I 3 D 23 2 PRODUCT TERMS (0 3) 3 32 D D D 2 D 3 I 2 B 0 3 I INPUTS (0 3) NOTES:. All unprogrammed or virgin gate locations are pulled to logic Programmable connections. September 0, 993

7 L, R, R, R PLUSRD/- SERIES LOGIC DIAGRAM PLUSR 0 9 B I 0 2 B I 3 D 23 2 PRODUCT TERMS (0 3) 3 32 D D D 2 3 B I 2 B 0 3 I INPUTS (0 3) NOTES:. All unprogrammed or virgin gate locations are pulled to logic Programmable connections. September 0, 993 2

8 L, R, R, R PLUSRD/- SERIES FUNCTIONAL DESCRIPTIONS The PLUSXX series utilizes the familiar sum-of-products implementation consisting of a programmable array and a fixed array. These devices are capable of replacing an equivalent of four or more SSI/MSI integrated circuits to reduce package count and board area occupancy, consequently improving reliability and design cycle over Standard Cell or gate array options. By programming the security fuse, proprietary designs can be protected from duplication. The PLUSXX series consists of four PAL-type devices. Depending on the particular device type, there are a variable number of combinatorial and registered outputs available to the designer. The PLUSL is a combinatorial part with user configurable outputs ( bidirectional), while the other three devices, PLUSR, PLUSR, PLUSR, have respectively,, and output registers. 3-State Outputs The PLUSXX series devices also feature 3-State output buffers on each output pin which can be programmed for individual control of all outputs. The registered outputs (n) are controlled by an external input (/), and the combinatorial outputs (On, Bn) use a product term to control the enable function. Programmable Bidirectional Pins The PLUSXX products feature variable Input/Output ratios. In addition to dedicated inputs, each combinatorial output pin of the registered devices can be individually programmed as an input or output. The PLUSL provides 0 dedicated inputs and Bidirectional I/O lines that can be individually configured as inputs or outputs. Output Registers The PLUSR has output registers, the R has, and the R has. Each output register is a D-type flip-flop which is loaded on the Low-to-High transition of the clock input. These output registers are capable of feeding the outputs of the registers back into the array to facilitate design of synchronous state machines. Power-up Reset By resetting all flip-flops to a logic Low, as the power is turned on, the PLUSR, R, R enhance state machine design and initialization capability. Software Support Like other Programmable Logic Devices from Philips Semiconductors, the PLUSXX series are supported by SLICE, the PC-based software development tool from Philips Semiconductors. The PLUSXX family of devices are also supported by standard CAD tools for, including ABEL and CUPL. SLICE is available free of charge to qualified users. Logic Programming The PLUSXX series is fully supported by industry standard (JEDEC compatible) PLD CAD tools, including Philips Semiconductors SNAP design software package. ABEL CUPL and PALASM 90 design software packages also support the PLUSXX architecture. All packages allow Boolean and state equation entry formats. SNAP, ABEL and CUPL also accept, as input, schematic capture format. Programming/Software Support Ref to Section 9 (Development Software) and Section 0. (Third-Party Programmer/ Software Support) of the PLD data handbook for additional information. ARRAY () P, D P, D P, D P, D STATE INACTIVE, 2 CODE O STATE CODE STATE CODE STATE H L DON T CARE CODE VIRGIN STATE A factory shipped virgin device contains all fusible links intact, such that:. All outputs are at H polarity. 2. All P n terms are disabled. 3. All P n terms are active on all outputs. ABEL is a trademark of Data I/O Corp. CUPL is a trademark of Logical Devices, Inc. PALASM is a registered trademark of AMD Corp. September 0, 993 3

9 L, R, R, R PLUSRD/- SERIES ABSOLUTE MAXIMUM RATINGS RATINGS SYMBOL PARAMETER MIN MAX UNIT Supply voltage 0. + V DC V IN Input voltage V DC V OUT Output voltage V V DC I IN Input currents ma I OUT Output currents +00 ma T stg Storage temperature range +0 C NOTE:. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other condition above those indicated in the operational and programming specification of the device is not implied. OPERATING RANGES RATINGS SYMBOL PARAMETER MIN MAX UNIT Supply voltage V DC T amb Operating free air temperature 0 + C THERMAL RATINGS Maximum junction Maximum ambient Allowable thermal rise ambient to junction TEMPERATURE 0 C C C September 0, 993

10 L, R, R, R PLUSRD/- SERIES DC ELECTRICAL CHARACTERISTICS 0 C T amb + C,..2V LIMITS SYMBOL PARAMETER TEST CONDITIONS MIN TYP MAX UNIT Input voltage 2 V IL Low = MIN 0. V V IH High = MAX 2.0 V V IC Clamp = MIN, I IN = ma 0.. V Output voltage = MIN, V IN = V IH or V IL V OL Low I OL = 2mA 0. V V OH High I OH = 3.2 ma 2. V Input current = MAX I IL Low 3 V IN = µa I IH High 3 V IN = 2.V 2 µa I I Maximum input current V IN = = MAX 00 µa Output current = MAX I OZH Output leakage V OUT = 2.V 00 µa I OZL Output leakage V OUT = 0.V 00 µa I OS Short circuit, V OUT = ma I CC supply current = MAX 0 0 ma Capacitance C IN Input = V V OUT = 2. pf C B I/O (B) V OUT = 2V, f = MHz pf NOTES:. All typical values are at = V, T amb = +2 C. 2. All voltage values are with respect to network ground terminal. 3. Leakage current for bidirectional pins is the worst case of I IL and I OZL or I IH and I OZH.. Test one at a time.. Duration of short circuit should not exceed second.. These parameters are not 00% tested but periodically sampled. September 0, 993

11 L, R, R, R PLUSRD/- SERIES AC ELECTRICAL CHARACTERISTICS R = 200Ω, R 2 = 390Ω, 0 C T amb + C,..2V LIMITS SYMBOL PARAMETER FROM TO D UNIT Pulse Width MIN TYP MAX MIN MAX t CKH Clock High CK+ CK ns t CKL Clock Low CK CK+ ns t CKP Period CK+ CK+ 0 ns Setup & Hold time t IS Input Input or feedback t IH Input CK+ Propagation delay CK+ 9 ns Input or feedback 0 0 ns t CKO Clock CK± ± ns t CKF Clock 3 CK± 3. ns t PD Output (L, R, R) 2 Output ns t Output enable Output enable ns t 2 Output enable, I Output enable ns t OD Output disable Output disable ns t OD2 Output disable, I Output disable ns t SKW Output ns t PPR Power-Up Reset ns Frequency (R, R, R) No feedback / (t CKL + t CKH ) 00. MHz f MAX Internal feedback / (t IS + t CKF ) 90. MHz External feedback / (t IS + t CKO ) 0. MHz * For definitions of the terms, please refer to the Timing/Frequency Definitions tables. NOTES:. CL = 0pF while measuring minimum output delays. 2. t PD test conditions: CL = 0pF (with jig and scope capacitance), V IH = 3V, V IL =, V OH = V OL =.V. 3. t CKF was calculated from measured Internal f MAX.. For 3-State output; output enable times are tested with C L = 0pF to the.v level, and S is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with C L = pf. High-to-High impedance tests are made to an output voltage of V T = (V OH 0.V) with S open, and Low-to-High impedance tests are made to the V T = (V OL + 0.V) level with S closed.. Same function as t and t OD, with the difference of using product term control.. Not 00% tested, but calculated at initial characterization and at any time a modification in design takes place which may affect the frequency. September 0, 993

12 L, R, R, R PLUSRD/- SERIES TEST LOAD CIRCUIT +V S C C 2 R I 0 B 0 /O 0 B n /O n R 2 C L DUT 0 INPUTS I n n NOTE: C and C 2 are to bypass to. OUTPUT REGISTER SKEW 3V n (REGISTERED OUTPUT) n + (REGISTERED OUTPUT).V.V t SKW 3V 3V CLOCK TO FEEDBACK PATH t IS D t CKF September 0, 993

13 L, R, R, R PLUSRD/- SERIES TIMING DIAGRAMS, 2 (INPUTS) (REGISTERED OUTPUTS) (INPUTS) O, B (COMBINATIAL OUTPUTS) (OUTPUT ENABLE) (REGISTERED OUTPUTS) (INPUTS) ÇÇÇÇÇ t PPR.V.V.V.V.V ÇÇÇÇÇÇÇ.V t IH ÇÇÇÇ t PD ÇÇÇÇÇ +.V.V t IS t IS t CKH t CKL t CKP t CKO t Flip-Flop Outputs t 2.V Gate Outputs.V.V.V NOTES:. Input pulse amplitude is to 3V. 2. Input rise and fall times are 2.ns. t CKO t IH.V V T.V +.V t IS.V ÇÇÇÇ t OD.V t OD2.V.V.V t IS t CKH t CKL Power Up Reset t IS+ t CKF V T +3V +3V V OH V OL +3V +3V V OH V OL +3V V OH V OL +3V +3V TIMING DEFINITIONS SYMBOL t CKH t CKL t CKP t IS t IH t CKF t CKO t t OD t 2 t OD2 t PPR t PD PARAMETER Width of input clock pulse. Interval between clock pulses. Clock period. Required delay between beginning of valid input and positive transition of clock. Required delay between positive transition of clock and end of valid input data. Delay between positive transition of clock and when internal output of flip-flop becomes valid. Delay between positive transition of clock and when outputs become valid (with Low). Delay between beginning of Output Enable Low and when outputs become valid. Delay between beginning of Output Enable High and when outputs are in the Off-State. Delay between predefined Output Enable High, and when combinational outputs become valid. Delay between predefined Output Enable Low and when combinational outputs are in the Off-State. Delay between (after power-on) and when flip-flop outputs become preset at (internal outputs at 0 ). Propagation delay between combinational inputs and outputs. FREUENCY DEFINITIONS f MAX No feedback: Determined by the minimum clock period, /(t CKL + t CKH ). Internal feedback: Determined by the internal delay from flip-flop outputs through the internal feedback and array to the flip-flop inputs, /(t IS + t CKF ). External feedback: Determined by clock-to-output delay and input setup time, /(t IS + t CKO ). September 0, 993

14 L, R, R, R PLUSRD/- SERIES OUTPUT REGISTER PRELOAD The output registers can be preloaded to any desired state during device testing. This permits any state to be tested without having to step through the entire state-machine sequence. Each register is preloaded individually by following the steps given below. Step. With at V and Pin at V IL, raise Pin to V IHH. Step 2. Apply either V IL or V IH to the output corresponding to the register to be preloaded. Step 3. Pulse Pin, clocking in preload data. Step. Remove output voltage, then lower Pin to V IL. Preload can be verified by observing the voltage level at the output pin. PIN V IHH t d t su t w t d V IL V IH PIN CLOCK ÉÉ t d ÇÇ REGISTERED I/O INPUT OUTPUT V IH V IL V IL V OH V OL NOTE: t d = t su = t w = 00ns to 000ns. V IHH = 0.2V to 0.V. Pin number references for DIP package. September 0, 993 9

15 L, R, R, R PLUSRD/- SERIES PROGRAMMING/SOFTWARE Refer to Section 9 (Development Software) and Section 0 (Third-Party Programmer/Software Support) of this data handbook for additional information. SNAP RESOURCE SUMMARY DESIGNATIONS 0 I0 I9 DINPAL NINPAL PROGRAMMABLE ARRAY DINPAL NINPAL NOUTPAL NOUTPAL O0, O B B PLUSL I0 I CKPAL NPAL DINPAL NINPAL PROGRAMMABLE ARRAY DINPAL NINPAL D DFFPAL D DFFPAL NOUTPAL NOUTPAL 0 PLUSR September 0, 993 0

16 L, R, R, R PLUSRD/- SERIES SNAP RESOURCE SUMMARY DESIGNATIONS (Continued) I0 I CKPAL NPAL DINPAL NINPAL PROGRAMMABLE ARRAY DINPAL NINPAL D DFFPAL NOUTPAL NOUTPAL B0, B PLUSR I0 I CKPAL NPAL DINPAL NINPAL PROGRAMMABLE ARRAY DINPAL NINPAL D DFFPAL NOUTPAL NOUTPAL B0, B, B, B 2 PLUSR September 0, 993