Philips Semiconductors Programmable Logic Devices

Transcription

1 DESCRTON The LS100 (3-State) and LS101 (Open Collector) are bipolar, fuse rogrammable Logic Arrays (LAs). Each device utilizes the standard AND/OR/nvert architecture to directly implement custom sum of product equations. Each device consists of 16 dedicated inputs and 8 dedicated outputs. Each output is capable of being actively controlled by any or all of the 48 product terms. The True, Complement, or Don t Care condition of each of the 16 inputs and be ANDed together to comprise one -term. All 48 -terms can be selectively ORed to each output. The LS100 and LS101 are fully TTL compatible, and chip enable control for expansion of input variables and output inhibit. They feature either Open Collector or 3-State outputs for ease of expansion of product terms and application in bus-organized systems. Order codes are listed in the Ordering nformation Table. FEATURES Field-programmable (Ni-Cr link) nput variables: 16 Output functions: 8 roduct terms: 48 /O propagation delay: 50ns (max.) ower dissipation: 600mW (typ.) nput loading: 100µA (max.) Chip Enable input Output option: LS100: 3-State LS101: Open-Collector Output disable function: 3-State: Hi-Z Open-Collector: High ALCATONS CRT display systems Code conversion eripheral controllers Function generators Look-up and decision tables Microprogramming Address mapping Character generators Data security encoders Fault detectors Frequency synthesizers 16-bit to 8-bit bus interface Random logic replacement N CONFGURATONS FE* F7 10 F6 11 F5 12 F4 13 N ackage V CC F0 F1 F2 GND F3 * Fuse Enable in: t is recommended that this pin be left open or connected to ground during normal operation. N = lastic D (600mil-wide) F7 F A ackage 7 FE V CC F5 F4 GND F3 F2 F1 F0 A = lastic Leaded Chip Carrier ORDERNG NFORMATON DESCRTON 3-STATE OEN COLLECTOR DRAWNG NUMBER 28-in lastic Dual n-line 600mil-wide LS100N LS101N 0413D 28-in lastic Leaded Chip Carrier LS100A LS101A 0401F October 22,

2 LOGC DAGRAM (LOGC TERMS ) X 0 X 1 X 2 X 3 X 4 X 5 X 6 X 7 S 0 S 1 S 2 S 3 S 4 S 5 S 6 S 7 18 F0 17 F1 16 F2 15 F3 13 F4 12 F5 11 F6 10 F7 19 NOTES: 1. All AND gate inputs with a blown link float to a logic All OR gate inputs with a blown fuse float to logic rogrammable connection. October 22,

3 FUNCTONAL DAGRAM 0 TYCAL CONNECTON 1 15 TYCAL CONNECTON S 0 F0 S 6 F6 S 7 F ABSOLUTE MAXMUM RATNGS 1 SYMBOL ARAMETER RATNGS UNT V CC Supply voltage +7.0 V DC V N nput voltage +5.5 V DC V O Output voltage +5.5 V DC N nput current ±30 ma OUT Output current +100 ma T amb Operating temperature range 0 to +75 C T stg Storage temperature range 65 to +150 C NOTE: 1. Stresses above those listed may cause malfunction or permanent damage to the device. This is a stress rating only. Functional operation at these or any other conditions above those indicated in the operational and programming specification of the device is not implied. THERMAL RATNGS TEMERATURE Maximum junction 150 C Maximum ambient 75 C Allowable thermal rise ambient to junction 75 C The LS100 device is also processed to military requirements for operation over the military temperature range. For specifications and ordering information consult the hilips Semiconductors Military Data Handbook. October 22,

4 DC ELECTRCAL CHARACTERSTCS 0 C T amb +75 C, 4.75V V CC 5.25V LMTS SYMBOL ARAMETER TEST CONDTONS MN TY 1 MAX UNT nput voltage 2 V H High V CC = MAX 2.0 V V L Low V CC = MN 0.8 V V C Clamp 3 V CC = MN, N = 12mA V Output voltage 2 VCC = MN V OH High (LS100) 4 OH = 2mA 2.4 V V OL Low 5 OL = 9.6mA V nput current H High V N = 5.5V < 1 25 µa L Low V N = 0.45V µa Output current O(OFF) Hi-Z state (LS100) = High, V CC = MAX V OUT = 5.5V 1 40 µa V OUT = 0.45V 1 40 µa OS Short circuit (LS100) 3, 6 = Low, V OUT = 0V ma CC V CC supply current 7 V CC = MAX ma Capacitance = High, V CC = 5.0V C N nput V N = 2.0V 8 pf C OUT Output V OUT = 2.0V 17 pf NOTES: 1. All typical values are at V CC = 5V, T amb = +25 C. 2. All voltage values are with respect to network ground terminal. 3. Test one pin at a time. 4. Measured with V L applied to and a logic high stored. 5. Measured with a programmed logic condition for which the output test is at a low logic level. Output sink current is applied through a resistor to V CC. 6. Duration of short circuit should not exceed 1 second. 7. CC is measured with the Chip Enable input grounded, all other inputs at 4.5V and the outputs open. October 22,

5 AC ELECTRCAL CHARACTERSTCS 0 C < T amb < +75 C, 4.75 < V CC < 5.25V, R 1 = 470Ω, R 2 = 1kΩ LMTS SYMBOL ARAMETER TO FROM MN TY 1 MAX UNT ropagation delay 2 t D nput Output nput ns t Chip Enable 3 Output Chip Enable ns Disable time t CD Chip Disable 3 Output Chip Enable ns NOTES: 1. All typical values are at V CC = 5V. T amb = +25 C. 2. All propagation delays are measured and specified under worst case conditions. 3. For 3-State output; output enable times are tested with C L = 30pF to the 1.5V level, and S 1 is open for high-impedance to High tests and closed for high-impedance to Low tests. Output disable times are tested with C L = 5pF. High-to-High impedance tests are made to an output voltage of V T = (V OH 0.5V) with S 1 open, and Low-to-High impedance tests are made to the V T = (V OL + 0.5V) level with S 1 closed. VOLTAGE WAVEFORMS TEST LOAD CRCUT +3.0V 90% V CC +5V S 1 0V 10% C 1 C 2 R 1 5ns t R t F 5ns 0 F V 90% NUTS 15 DUT R 2 C L 0V 10% 5ns 5ns GND F 7 OUTUTS MEASUREMENTS: All circuit delays are measured at the +1.5V level of inputs and outputs, unless otherwise specified. nput ulses NOTE: C 1 and C 2 are to bypass V CC to GND. TMNG DEFNTONS TMNG DAGRAM SYMBOL t t CD t D ARAMETER Delay between beginning of Chip Enable Low (with nput valid) and when Data Output becomes valid. Delay between when Chip Enable becomes High and Data Output is in off state (Hi-Z or High). Delay between beginning of valid nput (with Chip Enable Low) and when Data Output becomes valid. NUT F0 F7 1.5V 1.5V 1.5V ÉÉÉ t t D Read Cycle t CD 1.5V 1.5V +3.0V 0V +3.0V 0V V OH V OL October 22,

6 LOGC ROGRAMMNG is fully supported by industry standard (JEDEC compatible) LD CAD tools, including hilips Semiconductors SNA, Data /O Corporation s ABEL and Logical Devices nc. s CUL design software packages. All packages allow Boolean and state equation entry formats. SNA, ABEL and CUL also accept, as input, schematic capture format. OUTUT OLARTY (F) logic designs can also be generated using the program table entry format detailed on the following pages. This program table entry format is supported by the hilips Semiconductors SNA LD design software package. To implement the desired logic functions, the state of each logic variable from logic equations (, B, O,, etc.) is assigned a symbol. The sumbols for TRUE, COMLEMENT, NACTVE, RESET, etc., are defined below. ROGRAMMNG AND SOFTWARE SUORT Refer to Section 9 (Development Software) and Section 10 (Third-party rogrammer/ Software Support) of this dat handbook for additional informational. S F S X O, B ACTVE LEVEL LOW (NVERTNG) L ACTVE LEVEL HGH 1 (NON-NVERTNG) H AND ARRAY () STATE NACTVE 1,2 O STATE STATE H L STATE DON T CARE OR ARRAY (F) S S n STATUS ACTVE 1 A n STATUS NACTVE NOTES: 1. This is the initial unprogrammed state of all links. t is normally associated with all unused (inactive) AND gates n. 2. Any gate n will be unconditionally inhibited if any one of its () link pairs is left intact. VRGN STATE The LS100/101 virgin devices are factory shipped in an unprogrammed state, with all fuses intact, such that: 1. All n terms are disabled (inactive) in the AND array. 2. All n terms are active in the OR array. 3. All outputs are Active-High. ABEL is a trademark of Data /O Corp. CUL is a trademark of Logical Devices, nc. October 22,

7 ROGRAM TABLE ROGRAM TABLE ENTRES CUSTOMER NAME NUT VARABLE OUTUT FUNCTON OUTUT ACTVE LEVEL URCHASE ORDER # Active Low Active High rod. Term Not resent in Fp rod. Term resent in Fp m m Don t Care HLS DEV # CF (XXXX) A (period) H L H L (dash) CUSTOMER SYMBOLZED ART # NOTES NOTES NOTE 1. olarity programmed once only. 1. Entries independent of output polarity. Enter ( ) for unused inputs TOTAL NUMBER OF ARTS 2. Enter (H) for all unused outputs. 2. Enter (A) for unused outputs of used -terms. of used -terms. ROGRAM TABLE # REV DATE T E R M N NO. VARABLE NAME AND NUT ( m ) OLARTY OR OUTUT (F ) October 22,

8 SNA RESOUR SUMMARY DESGNATONS 0 DN100 NN AND OR S 0 TOUT100 F0 S 6 F6 S 7 F EXOR100 NOE100 October 22,