GAL16V8/883 High Performance E 2 CMOS PLD Generic Array Logic. Devices have been discontinued. PROGRAMMABLE AND-ARRAY (64 X 32)
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1 GAL16V/3 High Performance E CMOS PLD Generic Array Logic Features Functional Block Diagram HGH PERFORMANCE E CMOS TECHNOLOGY 7.5 ns Maximum Propagation Delay Fmax = 100 MHz 6 ns Maximum from Clock nput to Data Output TTL Compatible 1 ma Outputs UltraMOS Advanced CMOS Technology / /O/Q 50% REDUCTON N POWER FROM BPOLAR 75mA Typ cc ACTVE PULL-UPS ON ALL PNS (GAL16VD-7 and GAL16VD-10 E CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells 100% Tested/100% Yields High Speed Electrical Erasure (<100ms 0 Year Data Retention EGHT OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity Also Emulates 0-pin PAL Devices with Full Function/ Fuse Map/Parametric Compatibility PROGRAMMABLE AND-ARRAY (64 X 3 /O/Q /O/Q /O/Q /O/Q /O/Q PRELOAD AND POWER-ON RESET OF ALL REGSTERS 100% Functional Testability APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade OE /O/Q /O/Q /OE ELECTRONC SGNATURE FOR DENTFCATON Description Pin Configuration The GAL16V/3 is a high performance E CMOS programmable logic device processed in full compliance to ML-STD-3. This military grade device combines a high performance CMOS process with Electrically Erasable (E floating gate technology to provide the highest speed/power performance available in the 3 qualified PLD market. The GAL16VD/3, at 7.5ns maximum propagation delay time, is the world's fastest military qualified CMOS PLD. The generic GAL architecture provides maximum design flexibility by allowing the Output Logic Macrocell ( to be configured by the user. The GAL16V/3 is capable of emulating all standard 0-pin PAL devices with full function/fuse map/parametric compatibility. Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture. Therefore, Lattice Semiconductor delivers 100% field programmability and functionality of all GAL products. n addition, 100 erase/write cycles and data retention in excess of 0 years are specified / Vcc 0 GAL16V Top View /O/Q GND /OE /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q / GND 1 5 CERDP GAL 16V Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE Copyright 010 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTCE SEMCONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 9714, U.S.A. April 010 Tel. ( ; 1-00-LATTCE; FAX ( ; 16vmil_04 1
2 Specifications GAL16VD-7/10/3 Absolute Maximum Ratings (1 Supply voltage V CC to +7V nput voltage applied....5 to V CC +1.0V Off-state output voltage applied....5 to V CC +1.0V Storage Temperature to 150 C Case Temperature with Power Applied to 15 C 1.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications. DC Electrical Characteristics Recommended Operating Conditions Case Temperature (T C to 15 C Supply voltage (V CC with Respect to Ground to +5.50V Over Recommended Operating Conditions (Unless Otherwise Specified SYMBOL PARAMETER CONDTON MN. TYP. 3 MAX. UNTS VL nput Low Voltage Vss V VH nput High Voltage.0 Vcc+1 V L 1 nput or /O Low Leakage Current 0V VN VL (MAX. 100 μa H nput or /O High Leakage Current 3.5V VN VCC 10 μa VOL Output Low Voltage OL = MAX. Vin = VL or VH 0.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH.4 V OL Low Level Output Current 1 ma OH High Level Output Current ma OS Output Short Circuit Current VCC = 5V VOUT = 0.5V T A = 5 C ma CC Operating Power VL = 0.5V VH = 3.0V L-7/ ma Supply Current ftoggle = 15MHz Outputs Open 1 The leakage current is due to the internal pull-up on all pins. See nput Buffer section for more information. One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3 Typical values are at Vcc = 5V and TA = 5 C
3 Specifications GAL16VD-7/10/3 AC Switching Characteristics PARAMETER TEST COND 1. DESCRPTON Over Recommended Operating Conditions -7 MN. MAX. -10 MN. MAX. tpd A nput or /O to Combinational Output ns UNTS tco A Clock to Output Delay ns tcf Clock to Feedback Delay 6 7 ns tsu Setup Time, nput or Feedback before Clock 7 10 ns th Hold Time, nput or Feedback after Clock 0 0 ns A Maximum Clock Frequency with MHz External Feedback, 1/(tsu + tco fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, 1/(tsu + tcf A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 5 ns twl Clock Pulse Duration, Low 5 ns ten B nput or /O to Output Enabled ns B OE to Output Enabled ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled ns 1 Refer to Switching Test Conditions section. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3 Refer to fmax Descriptions section. Capacitance (T A = 5 C, f = 1.0 MHz SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance 10 pf V CC = 5.0V, V =.0V C /O /O Capacitance 10 pf V CC = 5.0V, V /O =.0V *Characterized but not 100% tested. 3
4 Specifications GAL16VD/3 Absolute Maximum Ratings (1 Supply voltage V CC to +7V nput voltage applied....5 to V CC +1.0V Off-state output voltage applied....5 to V CC +1.0V Storage Temperature to 150 C Case Temperature with Power Applied to 15 C 1.Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications. Recommended Operating Conditions Case Temperature (T C to 15 C Supply voltage (V CC with Respect to Ground to +5.50V DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified SYMBOL PARAMETER CONDTON MN. TYP. MAX. UNTS VL nput Low Voltage Vss V VH nput High Voltage.0 Vcc+1 V L nput or /O Low Leakage Current 0V VN VL (MAX. 10 μa H nput or /O High Leakage Current 3.5V VN VCC 10 μa VOL Output Low Voltage OL = MAX. Vin = VL or VH 0.5 V VOH Output High Voltage OH = MAX. Vin = VL or VH.4 V OL Low Level Output Current 1 ma OH High Level Output Current ma OS 1 Output Short Circuit Current VCC = 5V VOUT = 0.5V T A = 5 C ma CC Operating Power VL = 0.5V VH = 3.0V L -15/ -0/ ma Supply Current ftoggle = 15MHz Outputs Open 1 One output at a time for a maximum duration of one second. Vout = 0.5V was selected to avoid test problems caused by tester ground degradation. Characterized but not 100% tested. 3 Typical values are at Vcc = 5V and TA = 5 C 4
5 Specifications GAL16VD/3 AC Switching Characteristics TEST PARAMETER COND 1. Over Recommended Operating Conditions -15 DESCRPTON MN. MAX. -0 MN. MAX. -30 UNTS MN. MAX. tpd A nput or /O to Combinational Output ns tco A Clock to Output Delay ns tcf Clock to Feedback Delay ns tsu Setup Time, nput or Feedback before Clock ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with MHz External Feedback, 1/(tsu + tco fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, 1/(tsu + tcf A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High ns twl Clock Pulse Duration, Low ns ten B nput or /O to Output Enabled ns B OE to Output Enabled ns tdis C nput or /O to Output Disabled ns C OE to Output Disabled ns 1 Refer to Switching Test Conditions section. Calculated from fmax with internal feedback. Refer to fmax Descriptions section. 3 Refer to fmax Descriptions section. Capacitance (T A = 5 C, f = 1.0 MHz SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance 10 pf V CC = 5.0V, V =.0V C /O /O Capacitance 10 pf V CC = 5.0V, V /O =.0V *Characterized but not 100% tested. 5
6 Specifications GAL16V/3 Switching Waveforms NPUT or /O FEEDBACK VALD NPUT tsu th NPUT or /O FEEDBACK COMBNATONAL OUTPUT VALD NPUT tpd REGSTERED OUTPUT tco 1/fmax (external fdbk Combinatorial Output Registered Output NPUT or /O FEEDBACK OE tdis ten tdis ten COMBNATONAL OUTPUT REGSTERED OUTPUT nput or /O to Output Enable/Disable OE to Output Enable/Disable twh twl 1/fmax (w/o fb Clock Width REGSTERED FEEDBACK 1/fmax (internal fdbk tcf tsu fmax with Feedback 6
7 Specifications GAL16V/3 fmax Descriptions LOGC ARRAY REGSTER tsu tco fmax with External Feedback 1/(tsu+tco LOGC ARRAY REGSTER Note: fmax with external feedback is calculated from measured tsu and tco. tcf tpd LOGC ARRAY tsu + th REGSTER fmax with No Feedback Note: fmax with no feedback may be less than 1/(twh + twl. This is to allow for a clock duty cycle of other than 50%. fmax with nternal Feedback 1/(tsu+tcf Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = 1/fmax - tsu. The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback, as shown above. For example, the timing from clock to a combinatorial output is equal to tcf + tpd. Switching Test Conditions nput Pulse Levels GND to 3.0V nput Rise and Fall Times 3ns 10% 90% nput Timing Reference Levels 1.5V Output Timing Reference Levels 1.5V Output Load See Figure 3-state levels are measured 0.5V from steady-state active level. Output Load Conditions (see figure FROM OUTPUT (O/Q UNDER TEST +5V R 1 TEST PONT Test Condition R1 R CL A 390Ω 750Ω 50pF B Active High 750Ω 50pF Active Low 390Ω 750Ω 50pF C Active High 750Ω 5pF Active Low 390Ω 750Ω 5pF R C * L *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE 7
8 Specifications GAL16V/3 GAL16V Ordering nformation (ML-STD-3 and SMD T pd T su T co cc ( ns ( ns ( ns ( (ma ma Ordering # Package M L-STD-3 SMD # Pin CERDP GAL16VD-7LD/ RA 0-Pin 1 GAL16VD-7LR/ A Pin CERDP GAL16VD-10LD/ RA 0-Pin GAL16VD-10LR/ A Pin CERDP GAL16VD-15LD/ RA 0-Pin GAL16VD-15LR/ A Pin CERDP GAL16VD-0LD/ RA 0-Pin GAL16VD-0LR/ A Pin CERDP GAL16VD-30LD/ RA Note: Lattice Semiconductor recognizes the trend in military device procurement towards using SMD compliant devices, as such, ordering by this number is recommended. 1. Discontinued per PCN # Discontinued per PCN #05A-10. Part Number Description XXXXXXXX _ XX X X X GAL16VD Device Name ML Process /3 = 3 Process L = Low Power Speed (ns Power Package D = CERDP R =
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INTEGRATED CIRCUITS 2000 Dec 01 File under Integrated Circuits ICL03 2002 Feb 19 FEATURES Stub-series terminated logic for 2.5 V (SSTL_2) Optimized for stacked DDR (Double Data Rate) SDRAM applications
32K x 8 Power Switched and Reprogrammable PROM
1CY7C271A CY7C271A Features CMOS for optimum speed/power Windowed for reprogrammability High speed 25 ns (Commercial) Low power 275 mw (Commercial) Super low standby power Less than 85 mw when deselected
SN74ALVCH BIT BUS-INTERFACE FLIP-FLOP WITH 3-STATE OUTPUTS
Member of the Texas Instruments Widebus Family EPIC (Enhanced-Performance Implanted CMOS) Submicron Process ESD Protection Exceeds 200 Per MIL-STD-883, Method 3015; Exceeds 20 Using Machine Model (C =
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S
CMOS Static RAM 1 Meg (128K x 8-Bit) IDT71024S Features 128K x 8 advanced high-speed CMOS static RAM Commercial (0 C to +70 C), Industrial ( 40 C to +85 C) Equal access and cycle times Commercial and Industrial:
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
Integrated Device Technology, Inc. HIGH-PERFORMAE CMOS BUS TRANSCEIVERS IDT54/74FCT86A/B IDT54/74FCT863A/B FEATURES: Equivalent to AMD s Am2986-64 bipolar registers in pinout/function, speed and output
FAST CMOS 16-BIT REGISTER (3-STATE)
FAST CMOS 16-BIT REGISTER (3-STATE) IDT54/74FCT16374T/AT/CT/ET IDT54/74FCT162374T/AT/CT/ET Integrated Device Technology, Inc. FEATURES: Common features: 0.5 MICRON CMOS Technology High-speed, low-power
8K x 8 EPROM CY27C64. Features. Functional Description. fax id: 3006
1CY 27C6 4 fax id: 3006 CY27C64 Features CMOS for optimum speed/power Windowed for reprogrammability High speed 0 ns (commercial) Low power 40 mw (commercial) 30 mw (military) Super low standby power Less
ICSSSTV DDR 24-Bit to 48-Bit Registered Buffer. Integrated Circuit Systems, Inc. Pin Configuration. Truth Table 1.
Integrated Circuit Systems, Inc. ICSSSTV32852 DDR 24-Bit to 48-Bit Registered Buffer Recommended Application: DDR Memory Modules Provides complete DDR DIMM logic solution with ICS93V857 or ICS95V857 SSTL_2
14-Bit Registered Buffer PC2700-/PC3200-Compliant
14-Bit Registered Buffer PC2700-/PC3200-Compliant Features Differential Clock Inputs up to 280 MHz Supports LVTTL switching levels on the RESET pin Output drivers have controlled edge rates, so no external
CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM
Integrated Device Technology, Inc. CMOS StaticRAM 16K (4K x 4-BIT) CACHE-TAG RAM IDT6178S FEATURES: High-speed Address to Valid time Military: 12/15/20/25ns Commercial: 10/12/15/20/25ns (max.) High-speed
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and
SN54ACT00, SN74ACT00 QUADRUPLE 2-INPUT POSITIVE-NAND GATES
SCAS AUGUST 99 REVISED MAY 99 Inputs Are TTL-Voltage Compatible EPIC (Enhanced-Performance Implanted CMOS) -µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin
SN54AS825A, SN74AS825A 8-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SDAS020B JUNE 1984 REVISED AUGUST 1995
Functionally Equivalent to AMD s AM2982 Improved I OH Specificatio Multiple Output Enables Allow Multiuser Control of the Interface Outputs Have Undershoot-Protection Circuitry Power-Up High-Impedance
16 x 16 PARALLEL CMOS MULTIPLIER-ACCUMULATOR
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IDT54/74FCT16374AT/CT/ET
FAST CMOS 16-BIT REGISTER (3-STATE) IDT54/74FCT16374AT/CT/ET FEATURES: 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tsk(o) (Output Skew) < 250ps Low input
2K x 8 Reprogrammable PROM
2K x 8 Reprogrammable PROM Features Windowed for reprogrammability CMOS for optimum speed/power High speed 20 ns (Commercial) 35 ns (Military) Low power 660 mw (Commercial and Military) Low standby power
SN54HC377, SN74HC377 OCTAL D-TYPE FLIP-FLOPS WITH CLOCK ENABLE
Eight Flip-Flops With Single-Rail Outputs Clock Enable Latched to Avoid False Clocking Applications Include: Buffer/Storage Registers Shift Registers Pattern Generators Package Options Include Plastic
Single, 3 V, CMOS, LVDS Differential Line Receiver ADN4662
Data Sheet FEATURES ±15 kv ESD protection on input pins 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 2.5 ns maximum propagation delay 3.3 V power supply High impedance outputs
FAST CMOS 16-BIT BIDIRECTIONAL 3.3V TO 5V TRANSLATOR
FAST CMOS 16-BIT BIDIRECTIONAL 3. TO 5V TRANSLATOR FAST CMOS 16-BIT BIDIRECTIONAL 3. TO 5V TRANSLATOR IDT74FCT164245T FEATURES: 0.5 MICRON CMOS Technology Bidirectional interface between 3. and 5V buses
IDT54/74FCT162244T/AT/CT/ET
FAST CMOS 16-BIT BUFFER/LINE DRIVER IDT54/74FCT162244T/AT/CT/ET FEATURES: 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tsk(o) (Output Skew) < 250ps Low input
512 x 8 Registered PROM
512 x 8 Registered PROM Features CMOS for optimum speed/power High speed 25 ns address set-up 12 ns clock to output Low power 495 mw (Commercial) 660 mw (Military) Synchronous and asynchronous output enables
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package
NTE74S188 Integrated Circuit 256 Bit Open Collector PROM 16 Lead DIP Type Package Description: The NTE74S188 Schottky PROM memory is organized in the popular 32 words by 8 bits configuration. A memory
DS Tap High Speed Silicon Delay Line
www.dalsemi.com FEATURES All-silicon timing circuit Five delayed clock phases per input Precise tap-to-tap nominal delay tolerances of ±0.75 and ±1 ns Input-to-tap 1 delay of 5 ns Nominal Delay tolerances
SN54ALS273, SN74ALS273 OCTAL D-TYPE FLIP-FLOPS WITH CLEAR SDAS218A APRIL 1982 REVISED DECEMBER 1994
WITH CLEA SDAS2A APIL 2 EVISED DECEMBE 4 Contain Eight Flip-Flops With Single-ail Outputs Buffered Clock and Direct-Clear Inputs Individual Data Input to Each Flip-Flop Applications Include: Buffer/Storage
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663
Dual, 3 V, CMOS, LVDS High Speed Differential Driver ADN4663 FEATURES ±15 kv ESD protection on output pins 600 Mbps (300 MHz) switching rates Flow-through pinout simplifies PCB layout 300 ps typical differential
FAST CMOS 1-TO-10 CLOCK DRIVER
Integrated Device Technology, Inc. FAST CMOS 1-TO-10 CLOCK DRIVER IDT54/74FCT807BT/CT FEATURES: 0.5 MICRON CMOS Technology Guaranteed low skew < 250ps (max.) Very low duty cycle distortion < 350ps (max.)
SN54HC365, SN74HC365 HEX BUFFERS AND LINE DRIVERS WITH 3-STATE OUTPUTS
High-Current -State s Drive Bus Lines, Buffer Memory Address Registers, or Drive up to LSTTL Loads True s Package Options Include Plastic Small-Outline (D) and Ceramic Flat (W) Packages, Ceramic Chip Carriers
ua9637ac DUAL DIFFERENTIAL LINE RECEIVER
ua967ac Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and EIA/TIA--B and ITU Recommendations V. and V. Operates From Single -V Power Supply Wide Common-Mode Voltage Range High Input Impedance
IDT54/74FCT16240AT/CT/ET
FAST CMOS 16-BIT BUFFER/LINE DRIVER IDT54/74FCT16240AT/CT/ET FEATURES: 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tsk(o) (Output Skew) < 250ps Low input
XC95144XV High-Performance CPLD R JTAG Port 1 3 JTAG Controller In-System Programming Controller Block 1 1 to /GCK /GSR /GTS Blocks FastCONNECT
0 XC95144XV High-Performance CPLD DS051 (v2.2) August 27, 2001 0 1 Advance Product Specification Features 144 macrocells with 3,200 usable gates Available in small footprint packages - 100-pin TQFP (81
PRELIMINARY C106A 1. 7C106A 12 7C106A 15 7C106A 20 7C106A 25 7C106A 35 Maximum Access Time (ns) Maximum Operating
1CY 7C10 6A Features High speed t AA = 12 ns CMOS for optimum speed/power Low active power 910 mw Low standby power 275 mw 2.0V data retention (optional) 100 µw Automatic power-down when deselected TTL-compatible
SN74S ASYNCHRONOUS FIRST-IN, FIRST-OUT MEMORY WITH 3-STATE OUTPUTS
Independent Asychronous Inputs and Outputs 16 Words by 5 Bits DC to 10-MHz Rate 3-State Outputs Packaged in Standard Plastic 300-mil DIPs description This 80-bit active-element memory is a monolithic Schottky-clamped
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family State-of-the-Art Advanced Low-Voltage BiCMOS (ALB) Technology Design for.-v Operation Schottky Diodes on All s to Eliminate Overshoot and Undershoot Industry
UNISONIC TECHNOLOGIES CO., LTD
UNISONIC TECHNOLOGIES CO., LTD 1-OF-2 DECODER/DEMULTIPLEXER DESCRIPTION The U74LVC1G19 is a 1-of-2 decoder / demultiplexer with a common output enable. This device buffers the data on input A and passes
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW POR CMOS STATIC RAM FEATURES Access time: 45, 70 ns Low active power: 200 mw (typical) Low standby power 250 µw (typical) CMOS standby 28 mw (typical) TTL standby Fully static operation: no
UNISONIC TECHNOLOGIES CO., LTD
U74CBT3257 4-BIT 1-OF-2 FET MULTIPLEXER/ DEMULTIPLEXER UNISONIC TECHNOLOGIES CO., LTD CMOS IC DESCRIPTION The U74CBT3257 is a 4-bit 1-of-2 high-speed TTL-compatible FET multiplexer/demultiplexer. The low
SN54HC191, SN74HC191 4-BIT SYNCHRONOUS UP/DOWN BINARY COUNTERS
Single Down/Up Count-Control Line Look-Ahead Circuitry Enhances Speed of Cascaded Counters Fully Synchronous in Count Modes Asynchronously Presettable With Load Control Package Options Include Plastic
KEY FEATURES. Immune to Latch-UP Fast Programming. ESD Protection Exceeds 2000 V Asynchronous Output Enable GENERAL DESCRIPTION TOP VIEW A 10
HIGH-SPEED 2K x 8 REGISTERED CMOS PROM/RPROM KEY FEATURES Ultra-Fast Access Time DESC SMD Nos. 5962-88735/5962-87529 25 ns Setup Pin Compatible with AM27S45 and 12 ns Clock to Output CY7C245 Low Power
ORDERING INFORMATION PACKAGE
Member of Texas Instruments Widebus Family Latch-Up Performance Exceeds 250 ma Per JESD 17 ESD Protection Exceeds JESD 22 2000-V Human-Body Model (A114-A) 200-V Machine Model (A115-A) Bus Hold on Data
FAST CMOS 16-BIT REGISTER (3-STATE)
FAST CMOS 16-BIT REGISTER (3-STATE) IDT74FCT16374AT/CT/ET FEATURES: 0.5 MICRON CMOS Technology High-speed, low-power CMOS replacement for ABT functions Typical tsk(o) (Output Skew) < 250ps Low input and
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
M74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation