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1 The isplsi 8VE is a High Density Programmable Logic Device available in 8 and 64 -pin versions. The device contains 8 Registers, eight Dedicated Input pins, three Dedicated Clock Input pins, two dedicated Global OE input pins and a Global Routing Pool (GRP). The GRP provides complete interconnectivity between all of these elements. The isplsi 8VE features in-system programmability through the Boundary Scan Test Access Port (TAP) and is 00% IEEE 49. Boundary Scan Testable. The isplsi 8VE offers non-volatile reprogrammability of the logic, as well as the interconnect to provide truly reconfigurable systems. The basic unit of logic on the isplsi 8VE device is the Generic Logic Block (GLB). The GLBs are labeled A0, A.. D7 (see Figure ). There are a total of GLBs in the isplsi 8VE device. Each GLB is made up of four macrocells. Each GLB has 8 inputs, a programmable AND/OR/Exclusive OR array, and four outputs which can be configured to be either combinatorial or registered. Inputs to the GLB come from the GRP and dedicated inputs. All of the GLB outputs are brought back into the GRP so that they can be connected to the inputs of any GLB on the device. Lead- Free Package Options Available! isplsi 8VE.V In-System Programmable SuperFAST High Density PLD Features SuperFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC 6000 PLD Gates 8 and 64 Pin Versions, Eight Dedicated Inputs 8 Registers High Speed Global Interconnect Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. Small Logic Block Size for Random Logic 00% Functional, JEDEC and Pinout Compatible with isplsi 8V Devices.V LOW VOLTAGE 8 ARCHITECTURE Interfaces with Standard 5V TTL Devices HIGH PERFORMANCE E CMOS TECHNOLOGY fmax = 50MHz Maximum Operating Frequency tpd = 4.0ns Propagation Delay Electrically Erasable and Reprogrammable Non-Volatile 00% Tested at Time of Manufacture Unused Product Term Shutdown Saves Power IN-SYSTEM PROGRAMMABLE.V In-System Programmability (ISP ) Using Boundary Scan Test Access Port (TAP) Open-Drain Output Option for Flexible Bus Interface Capability, Allowing Easy Implementation of Wired- OR Bus Arbitration Logic Increased Manufacturing Yields, Reduced Time-to- Market and Improved Product Quality Reprogram Soldered Devices for Faster Prototyping 00% IEEE 49. BOUNDARY SCAN TESTABLE THE EASE OF USE AND FAST SYSTEM SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY OF FPGAS Enhanced Pin Locking Capability Three Dedicated Clock Input Pins Synchronous and Asynchronous Clocks Programmable Output Slew Rate Control Flexible Pin Placement Optimized Global Routing Pool Provides Global Interconnectivity LEAD-FREE PACKAGE OPTIONS Functional Block Diagram* A0 A A A A4 A5 A6 A7 *8 Version Shown Description D7 D6 D5 D4 Global Routing Pool (GRP) B0 B B B Logic Array D D D D0 GLB D D D D Q Q Q Q B4 B5 B6 B7 C7 C6 C5 C4 C C C C0 CLK 0 CLK CLK 09A/8VE Copyright 004 Lattice Semiconductor Corp. All brand or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice. LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 974, U.S.A. August 004 Tel. (50) ; -800-LATTICE; FAX (50) ; 8ve_

2 Functional Block Diagram Figure. isplsi 8VE Functional Block Diagram (8- and 64- Versions) IN 7 IN IN 7* IN 6* RESET RESET GOE 0 GOE Megablock Input Bus GOE 0 GOE Megablock Input Bus Generic Logic Blocks (GLBs) D7 D6 D5 D4 D D D D0 IN 5 IN 4 Generic Logic Blocks (GLBs) D7 D6 D5 D4 D D D D0 IN 5* IN 4* Input Bus A0 A A A A4 A5 A6 A7 Global Routing Pool (GRP) C7 C6 C5 C4 C C C C0 Input Bus Input Bus A0 A A A A4 A5 A6 A7 Global Routing Pool (GRP) C7 C6 C5 C4 C C C C0 Input Bus TDI/IN 0 TMS/IN B0 B B B B4 B5 B6 B7 TDI/IN 0 TMS/IN B0 B B B B4 B5 B6 B7 CLK 0 CLK CLK CLK 0 CLK CLK Input Bus Input Bus BSCAN BSCAN TDO/IN TCK/IN Y0 Y Y 09B/8VE TDO/IN TCK/IN Y0 Y Y 09B/8VE.64IO *Not available on 84-PLCC Device The 8-8VE contains 8 cells, while the 64- version contains 64 cells. Each cell is directly connected to an pin and can be individually programmed to be a combinatorial input, output or bi-directional pin with -state control. The signal levels are TTL compatible voltages and the output drivers can source 4mA or sink 8mA. Each output can be programmed independently for fast or slow output slew rate to minimize overall output switching noise. Device pins can be safely driven to 5V signal levels to support mixed-voltage systems. Eight GLBs, or 6 cells, two dedicated inputs and two or one ORPs are connected together to make a Megablock (see Figure ). The outputs of the eight GLBs are connected to a set of or 6 universal cells by the two or one ORPs. Each isplsi 8VE device contains four Megablocks. Y, Y) or an asynchronous clock can be selected on a GLB basis. The asynchronous or Product Term clock can be generated in any GLB for its own clock. Programmable Open-Drain Outputs In addition to the standard output configuration, the outputs of the isplsi 8VE are individually programmable, either as a standard totem-pole output or an open-drain output. The totem-pole output drives the specified Voh and Vol levels, whereas the open-drain output drives only the specified Vol. The Voh level on the open-drain output depends on the external loading and pull-up. This output configuration is controlled by a programmable fuse. The default configuration when the device is in bulk erased state is totem-pole configuration. The open-drain/totem-pole option is selectable through the Lattice software tools. The GRP has as its inputs, the outputs from all of the GLBs and all of the inputs from the bi-directional cells. All of these signals are made available to the inputs of the GLBs. Delays through the GRP have been equalized to minimize timing skew. Clocks in the isplsi 8VE device are selected using the dedicated clock pins. Three dedicated clock pins (Y0,

3 Absolute Maximum Ratings Supply Voltage V cc to +5.4V Input Voltage Applied to +5.6V Off-State Output Voltage Applied to +5.6V Storage Temperature to 50 C Case Temp. with Power Applied to 5 C Max. Junction Temp. (T J ) with Power Applied C. Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. Functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). DC Recommended Operating Condition SYMBOL PARAMETER MIN. MAX. UNITS VIL VIH Supply Voltage Input Low Voltage Input High Voltage Commercial Industrial T A = 0 C to + 70 C T A = -40 C to + 85 C.0.0 V 0.5 SS.0.6 V.6 V 0.8 V 5.5 V Table -0005/8VE Capacitance (T A =5 C, f=.0 MHz) C C SYMBOL PARAMETER TYPICAL UNITS TEST CONDITIONS Dedicated Input Capacitance 8 pf Capacitance 6 pf V =.V, V = 0.0V CC C Clock and Global Output Enable Capacitance 0 pf V =.V, V = 0.0V CC Y Erase Reprogram Specifications V =.V, V = 0.0V CC IN Table -0006/8VE PARAMETER MINIMUM MAXIMUM UNITS Erase/Reprogram Cycles 0,000 Cycles Table -0008/8VE

4 Switching Test Conditions Input Pulse Levels Input Rise and Fall Time to.0v.5ns 0% to 90% Figure. Test Load +.V Input Timing Reference Levels Output Timing Reference Levels.5V.5V R Output Load See Figure -state levels are measured 0.5V from steady-state active level. Table - 000/8VE Output Load Conditions (see Figure ) Device Output R CL* Test Point TEST CONDITION R R CL A 6Ω 48Ω 5pF B C Active High Active Low Active High to Z at V OH-0.5V Active Low to Z at V OL+0.5V 48Ω 5pF 6Ω 48Ω 5pF 48Ω 5pF 6Ω 48Ω 5pF Table -0004/8VE *CL includes Test Fixture and Probe Capacitance. 0A/8VE DC Electrical Characteristics Over Recommended Operating Conditions SYMBOL VOL VOH IIL IIH IIL-isp IIL-PU IOS, 4 ICC PARAMETER Output Low Voltage Output High Voltage Input or Low Leakage Current Input or High Leakage Current BSCAN Input Low Leakage Current Active Pull-Up Current Output Short Circuit Current Operating Power Supply Current CONDITION MIN. TYP. MAX. UNITS I OL = 8 ma I OH = -4 ma 0V V V (Max.) V V µa IN 0V V IN VIL 0V V IN VIL V CC =.V, V OUT = 0.5V V IL = 0.0V, V IH =.0V f = MHz CLOCK. One output at a time for a maximum duration of one second. V OUT = 0.5V was selected to avoid test problems by tester ground degradation. Characterized but not 00% tested.. Measured using eight 6-bit counters.. Typical values are at V CC=.V and T A= 5 C. 4. Maximum I CC varies widely with specific device configuration and operating frequency. Refer to the Power Consumption section of this data sheet and Thermal Management section of the Lattice Semiconductor Data Book or CD-ROM to estimate maximum I. CC IL (V CC - 0.)V V IN V V V 5.5V CC IN CC µa µa µa µa ma ma Table -0007/8VE 4

5 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # DESCRIPTION UNITS COND. MIN. MAX. MIN. MAX. tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd A Data Propagation Delay ns fmax A Clock Frequency with Internal Feedback MHz fmax (Ext.) 4 Clock Frequency with External Feedback( tsu + tco) 58 5 MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass.5.5 ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass.0.5 ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu 9 GLB Reg. Setup Time before Clock. 4.5 ns tco A 0 GLB Reg. Clock to Output Delay ns th GLB Reg. Hold Time after Clock ns tr A Ext. Reset Pin to Output Delay, ORP Bypass ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High.8.5 ns twl 9 External Synchronous Clock Pulse Duration, Low.8.5 ns. Unless noted otherwise, all parameters use a GRP load of four, 0 PTXOR path, ORP and Y0 clock.. Standard 6-bit counter using GRP feedback.. Reference Switching Test Conditions section. USE 8VE-50 FOR NEW DESIGNS Table -000A/8VE v..0 5

6 External Timing Parameters Over Recommended Operating Conditions PARAMETER TEST # DESCRIPTION COND. MIN. MAX. MIN. MAX. UNITS tpd A Data Propagation Delay, 4PT Bypass, ORP Bypass ns tpd A Data Propagation Delay ns fmax A Clock Frequency with Internal Feedback 5 00 MHz fmax (Ext.) 4 Clock Frequency with External Feedback( tsu + tco) MHz fmax (Tog.) 5 Clock Frequency, Max. Toggle 4 00 MHz tsu 6 GLB Reg. Setup Time before Clock, 4 PT Bypass ns tco A 7 GLB Reg. Clock to Output Delay, ORP Bypass ns th 8 GLB Reg. Hold Time after Clock, 4 PT Bypass ns tsu 9 GLB Reg. Setup Time before Clock ns tco A 0 GLB Reg. Clock to Output Delay ns th GLB Reg. Hold Time after Clock ns tr A Ext. Reset Pin to Output Delay, ORP Bypass ns trw Ext. Reset Pulse Duration ns tptoeen B 4 Input to Output Enable ns tptoedis C 5 Input to Output Disable ns tgoeen B 6 Global OE Output Enable ns tgoedis C 7 Global OE Output Disable ns twh 8 External Synchronous Clock Pulse Duration, High ns twl 9 External Synchronous Clock Pulse Duration, Low ns. Unless noted otherwise, all parameters use a GRP load of four, 0 PTXOR path, ORP and Y0 clock.. Standard 6-bit counter using GRP feedback.. Reference Switching Test Conditions section. Table -000B/8VE v..0 6

7 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # DESCRIPTION UNITS MIN. MAX. MIN. MAX. Inputs tio 0 Input Buffer Delay ns tdin Dedicated Input Delay 0.7. ns GRP tgrp GRP Delay ns GLB t4ptbpc 4 Product Term Bypass Path Delay (Combinatorial).5.9 ns t4ptbpr 4 4 Product Term Bypass Path Delay (Registered).0.4 ns tptxor 5 Product Term/XOR Path Delay.8.4 ns t0ptxor 6 0 Product Term/XOR Path Delay.8.4 ns txoradj 7 XOR Adjacent Path Delay.8.4 ns tgbp 8 GLB Register Bypass Delay ns tgsu 9 GLB Register Setup Time before Clock 0.8. ns tgh 0 GLB Register Hold Time after Clock.7. ns tgco GLB Register Clock to Output Delay ns tgro GLB Register Reset to Output Delay ns tptre GLB Product Term Reset to Register Delay.7 4. ns tptoe 4 GLB Product Term Output Enable to Cell Delay ns tptck 5 GLB Product Term Clock Delay ns ORP torp 6 ORP Delay..4 ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay.4.6 ns tsl 9 Output Slew Limited Delay Adder.0.0 ns. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros. USE 8VE-50 FOR NEW DESIGNS toen 40 Cell OE to Output Enabled.4.0 ns todis 4 Cell OE to Output Disabled.4.0 ns tgoe 4 Global Output Enable.6.0 ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/ 44 Clock Delay, Y or Y to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB ns Table -006A/8VE v..0 7

8 Internal Timing Parameters Over Recommended Operating Conditions PARAMETER # DESCRIPTION MIN. MAX. MIN. MAX. UNITS Inputs tio 0 Input Buffer Delay ns tdin Dedicated Input Delay.7.5 ns GRP tgrp GRP Delay..8 ns GLB t4ptbpc 4 Product Term Bypass Path Delay (Combinatorial).7 5. ns t4ptbpr 4 4 Product Term Bypass Path Delay (Registered) ns tptxor 5 Product Term/XOR Path Delay ns t0ptxor 6 0 Product Term/XOR Path Delay ns txoradj 7 XOR Adjacent Path Delay ns tgbp 8 GLB Register Bypass Delay ns tgsu 9 GLB Register Setup Time before Clock..7 ns tgh 0 GLB Register Hold Time after Clock ns tgco GLB Register Clock to Output Delay ns tgro GLB Register Reset to Output Delay.. ns tptre GLB Product Term Reset to Register Delay ns tptoe 4 GLB Product Term Output Enable to Cell Delay ns tptck 5 GLB Product Term Clock Delay ns ORP torp 6 ORP Delay.5.7 ns torpbp 7 ORP Bypass Delay ns Outputs tob 8 Output Buffer Delay.6.6 ns tsl 9 Output Slew Limited Delay Adder.0.0 ns toen 40 Cell OE to Output Enabled.4.4 ns todis 4 Cell OE to Output Disabled.4.4 ns tgoe 4 Global Output Enable ns Clocks tgy0 4 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns tgy/ 44 Clock Delay, Y or Y to Global GLB Clock Line ns Global Reset tgr 45 Global Reset to GLB ns. Internal Timing Parameters are not tested and are for reference only.. Refer to Timing Model in this data sheet for further details.. The XOR adjacent path can only be used by hard macros. Table -006B/8VE v..0 8

9 isplsi 8VE Timing Model Cell GRP GLB ORP Cell Feedback Ded. In Pin (Input) Reset # Delay GRP Reg 4 PT Bypass GLB Reg Bypass ORP Bypass #0 # #4 #8 #45 0 PT XOR Delays #5, 6, 7 Comb 4 PT Bypass # GLB Reg Delay D Q RST #9, 0,, #7 ORP Delay #6 #8, 9 Pin (Output) Control PTs #, 4, 5 RE OE CK #40, 4 Y0,, #4, 44 GOE 0 #4 049/0 Derivations of tsu, th and tco from the Product Term Clock tsu = = = Logic + Reg su - Clock (min) (tio + tgrp + t0ptxor) + (tgsu) - (tio + tgrp + tptck(min)) (#0 + # + #6) + (#9) - (#0 + # + #5).8ns = ( ) + (0.8) - ( ) th tco.5ns 7.0ns = = = = = = = = Clock (max) + Reg h - Logic (tio + tgrp + tptck(max)) + (tgh) - (tio + tgrp + t0ptxor) (#0 + # + #5) + (#0) - (#0 + # + #6) ( ) + (.7) - ( ) Clock (max) + Reg co + Output (tio + tgrp + tptck(max)) + (tgco) + (torp + tob) (#0 + # + #5) + (#) + (#6 + #8) ( ) + (0.) + (. +.4) Note: Calculations are based upon timing specifications for the isplsi 8VE-50L. Table -004/8VE v..0 9

10 Power Consumption Power consumption in the isplsi 8VE device depends on two primary factors: the speed at which the device is operating and the number of Product Terms used. Figure shows the relationship between power and operating speed. Figure. Typical Device Power Consumption vs fmax 50 isplsi 8VE ICC (ma) fmax (MHz) Notes: Configuration of eight 6-bit counters Typical current at.v, 5 C ICC can be estimated for the isplsi 8VE using the following equation: ICC = 8 + (# of PTs * 0.669) + (# of nets * max freq * 0.006) Where: # of PTs = Number of Product Terms used in design # of nets = Number of Signals used in device Max freq = Highest Clock Frequency to the device (in MHz) The ICC estimate is based on typical conditions ( =.V, room temperature) and an assumption of two GLB loads on average exists. These values are for estimates only. Since the value of ICC is sensitive to operating conditions and the program in the device, the actual ICC should be verified. 07/8VE 0

11 Signal Descriptions Signal Name RESET Active Low (0) Reset pin resets all the registers in the device. GOE 0, GOE Global Output Enable input pins. Y0, Y, Y Dedicated Clock Input These clock inputs are connected to one of the clock inputs of all the GLBs in the device. BSCAN Input Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to enable the programming mode. The TMS, TDI, TDO and TCK controls become active. TDI/IN 0 Input This pin performs two functions. When BSCAN is logic low, it functions as a serial data input pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin. TCK/IN Input This pin performs two functions. When BSCAN is logic low, it functions as a clock pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TMS/IN Input This pin performs two functions. When BSCAN is logic low, it functions as a mode control pin for the Boundary Scan state machine. When BSCAN is high, it functions as a dedicated input pin. TDO/IN Output/Input This pin performs two functions. When BSCAN is logic low, it functions as an output pin to read serial shift register data. When BSCAN is high, it functions as a dedicated input pin. IN 4 - IN 7 Dedicated Input Pins to the device. Ground () Vcc NC No Connect Input/Output Pins These are the general purpose pins used by the logic array.. NC pins are not to be connected to any active signals, or. Description

12 Signal Locations Signal 08-Ball f fpbg pbga 76-Pin TQF QFP 60-Pin PQF QFP 00-Ball cabg abga 00-Pin TQF QFP RESET H 9 D GOE 0, GOE J6, H 0, 00, F9, E 6, Y0, Y, Y H, H4, J4 0,, 08 8, 0, 98 E, F6, F8 0, 65, 60 BSCAN J 5 E5 5 TDI/IN 0 J 6 4 F 6 TCK/IN J G0 59 TMS/IN P J5 7 TDO/IN C B6 87 I N 4 - IN 7 H6, A9, T8, 4, 55, 67, 04, 4, 6, E9, A6, K5, D 66, 88, 8, 9 H4 9 7 G ND D4, D, G7, G8, G9, G0, H7, H8, H9, H0, J7, J8, J9, J0, K7, K8, K9, K0, N4, N V CC D5, D6, D, E4, E, F4, F, L4, L, M4, M, N5, N, N NC A, A, A5, A6, B, B, B, B4, B5, B6, C, C, C4, C5, D4, P, P, P, P, P4, P5, R, R, R, R4, R5, R6, T, T, T5, T6. NC pins are not to be connected 4, 46, 68, 87, 09, 4, 5, 75,, 4, 65, 90,,, 56 9, 8, 7, 6, 55, 64, 69, 78, 97, 06,, 5, 4, 4, 5, 57, 66, 4, 6, 79, 99,, 9, 59, 0, 9, 59, 8, 0, 9, 4 to any active signals, or. B7, F, G9, K6 4, 9, 6, 86 A5, E, F0, J4, 6, 6, 89 0 A8, C, C4, D6, D8, E7, E0, F4, G, G5, H7, H8, K 4,, 5,, 44, 50, 54, 64, 7, 75, 8, 94, 00

13 Locations Signal fpbga TQFP PQFP cabga TQFP 0 J 8 5 G 7 J4 9 6 F 8 K 0 7 E4 9 K 8 H 0 4 K 9 G 5 K4 0 J 6 L 4 H 4 7 L 5 K 6 8 L 7 J 7 9 M 8 4 K 8 0 M 9 5 H 9 M 40 6 J 0 N 4 7 G4 N 4 8 H4 4 N K4 4 5 P H5 5 6 T 47 4 F R J6 4 8 T K7 4 9 P H6 4 0 R K8 45 N G6 46 T J7 47 R K P J T K0 5 6 N J9 5 7 R J0 5 8 P H T H N G7 57 R G8 58 T D0 67 P E R F N C T D9 7 7 P B0 7 8 R C N A T 79 7 B P 80 7 A R 8 7 C T 8 74 B P 8 75 D R C T A R C T E N B P6 9 8 A4 9 5 N C5 9 5 N A 95 5 M D M B M A L B L A 58 L B 59 K 0 9 B 60 K5 0 9 C 5 6 K C 6 6 K D4 7 6 J D Signal fpbga TQFP PQFP cabga TQFP 64 H H G G G G 0 70 F6 7 F4 7 F5 5 7 E E E D C D A4 80 C 5 8 B A C B D A C B D A 46 9 B C D A B A C B D A C B D A C B A C B A B C A 4 C 5 D D D E E E 0 9 F 0 F F 4 G4 4 5 G G G 7 6

14 Signal Configuration isplsi 8VE 08-Ball fpbga Signal Diagram A NC NC IN NC NC A B NC NC NC NC NC NC B C 77 NC NC TDO/ IN NC NC 4 C D NC D E E F F G G H IN 4 64 Y 65 IN 7 RESET Y0 GOE H J GOE 0 TCK/ IN Y 6 TDI/ IN 0 0 BSCAN J K K L M isplsi 8VE Bottom View L M N N P TMS/ 50 NC NC NC IN NC NC NC P R NC NC NC NC NC NC R T NC NC IN NC NC T BGA/8VE. NCs are not to be connected to any active signals, Vcc or. Note: Ball A indicator dot on top side of package. 4

15 Pin Configuration isplsi 8VE 76-Pin TQFP Pinout Diagram isplsi 8VE Top View NC NC IN 5 TDO/IN NC NC NC NC IN 7 Y0 RESET GOE BSCAN TDI/IN 0 NC NC NC NC IN 4 Y NC GOE 0 Y TCK/IN NC NC NC NC TMS/IN IN 6 NC NC NC pins are not to be connected to any active signals, or. 76-TQFP/8VE 5

16 Pin Configuration isplsi 8VE 60-Pin PQFP Pinout Diagram isplsi 8VE Top View IN 5 TDO/IN IN 7 Y0 RESET GOE BSCAN TDI/IN IN 4 Y NC GOE 0 Y TCK/IN TMS/IN IN NC pins are not to be connected to any active signal, or. 60-PQFP/8VE 6

17 Signal Configuration isplsi 8VE 00-Ball cabga Signal Diagram A 9 4 NC IN A B TDO/ IN B C NC NC 60 6 C D 6 NC NC 44 RESET IN 7 D E NC IN 4 NC BSCAN 48 Y0 GOE E F GOE Y Y NC TDI/ IN 0 F G TCK/ IN NC 0 NC 4 0 G H 9 8 NC NC H J TMS/ IN 8 5 J K IN 6 NC 4 isplsi 8VE Bottom View K 00-BGA/8VE NCs are not to be connected to any active signals, or. Note: Ball A indicator dot on top side of package. 7

18 Pin Configuration isplsi 8VE 00-Pin TQFP Pinout Diagram NC NC IN 5 TDO/IN NC NC IN 7 Y0 RESET GOE BSCAN TDI/IN 0 0 NC NC isplsi 8VE Top View NC NC 5 4 IN 4 Y NC GOE 0 Y TCK/IN NC NC 4 5 TMS/IN IN NC 0 4 NC 00-TQFP/8VE. NC pins are not to be connected to any active signals, or. 8

19 Part Number Description isplsi 8VE XXX X XXXXX X Device Family Device Number Speed 50 = 50 MHz fmax 80 = 80 MHz fmax* 5 = 5 MHz fmax 00 = 00 MHz fmax *Use isplsi 8VE-50 for new designs Grade Blank = Commercial I = Industrial Package Q60 = 60-Pin PQFP T76 = 76-Pin TQFP TN76 = Lead-Free 76-Pin TQFP B08 = 08-Ball fpbga BN08 = Lead-Free 08-Ball fpbga T00 = 00-Pin TQFP TN00 = Lead-Free 00-Pin TQFP B00 = 00-Ball cabga Power L = Low 0/8VE isplsi 8VE Ordering Information Conventional Packaging COMMERCIAL FAMILY fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi *Use isplsi 8VE-50 for new designs isplsi 8VE-50LT76 76-Pin TQFP isplsi 8VE-50LQ60 60-Pin PQFP isplsi 8VE-50LB08 08-Ball fpbga isplsi 8VE-50LT00 00-Pin TQFP isplsi 8VE-50LB00 00-Ball cabga isplsi 8VE-80LT76* 76-Pin TQFP isplsi 8VE-80LQ60* 60-Pin PQFP isplsi 8VE-80LB08* 08-Ball fpbga isplsi 8VE-80LT00* 00-Pin TQFP isplsi 8VE-80LB00* 00-Ball cabga isplsi 8VE-5LT76 76-Pin TQFP isplsi 8VE-5LQ60 60-Pin PQFP isplsi 8VE-5LB08 08-Ball fpbga isplsi 8VE-5LT00 00-Pin TQFP isplsi 8VE-5LB00 00-Ball cabga isplsi 8VE-00LT76 76-Pin TQFP isplsi 8VE-00LQ60 60-Pin PQFP isplsi 8VE-00LB08 08-Ball fpbga isplsi 8VE-00LT00 00-Pin TQFP isplsi 8VE-00LB00 00-Ball cabga Table -004A/8VE 9

20 isplsi 8VE Ordering Information (Cont.) Conventional Packaging (Cont.) INDUSTRIAL FAMILY fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi Lead-Free Packaging isplsi 8VE-5LT00I 00-Pin TQFP isplsi 8VE-5LT76I 76-Pin TQFP COMMERCIAL FAMILY fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi Table -004B/8VE isplsi 8VE-50LTN76 Lead-Free 76-Pin TQFP isplsi 8VE-50LBN08 Lead-Free 08-Ball fpbga isplsi 8VE-50LTN00 Lead-Free 00-Pin TQFP isplsi 8VE-5LTN76 Lead-Free 76-Pin TQFP isplsi 8VE-5LBN08 Lead-Free 08-Ball fpbga isplsi 8VE-5LTN00 Lead-Free 00-Pin TQFP isplsi 8VE-00LTN76 Lead-Free 76-Pin TQFP isplsi 8VE-00LBN08 Lead-Free 08-Ball fpbga isplsi 8VE-00LTN00 Lead-Free 00-Pin TQFP INDUSTRIAL FAMILY fmax (MHz) tpd (ns) s ORDERING NUMBER PACKAGE isplsi isplsi 8VE-5LTN76I Lead-Free 76-Pin TQFP isplsi 8VE-5LTN00I Lead-Free 00-Pin TQFP 0

All Devices Discontinued!

isplsi 3320 Device Datasheet June 200 All Devices Discontinued! Product Change Notification (PCN) #09-0 has been issued to discontinue all devices in this data sheet. The original datasheet pages have