XC2C256 CoolRunner-II CPLD
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1 0 XC2C256 Coolunner-II CPLD DS094 (v1.2) November 20, Advance Product Specification Features Optimized for 1.8V systems - As fast as 5.0 ns pin-to-pin delays - As low as 25 µa quiescent current Industry s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis - Multi-voltage operation 1.5V to 3.3V Available in multiple package options pin VQFP with 80 user pin TQFP with 118 user ball CP (0.5mm) BGA with 106 user pin PQFP with 173 user ball FT (1.0mm) BGA with 184 user Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management - Two separate output banks - Fast Zero Power (FZP) 100% CMOS product term generation - DataGATE enable (DGE) signal control - Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide by 2,4,6,8,10,12,14,16) CoolCLOCK - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Advanced design security - Open-drain output option for Wired-O and LED drive - Optional bus-hold, 3-state or weak pull-up on selected pins - Optional configurable grounds on unused s - Mixed voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels SSTL2-1, SSTL3-1, and HSTL-1 compatibility - Hot pluggable efer to the Coolunner -II family data sheet for architecture description. Description The Coolunner-II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS094 (v1.2) November 20, Advance Product Specification
2 XC2C256 Coolunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is output banking. Two output banks are available on the Coolunner-II 256 macrocell device that permits easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The Coolunner-II 256 macrocell CPLD is compatible with various standards (see Table 1). This device is also 1.5V compatible with the use of Schmitt-trigger inputs. Fast Zero Power Design Technology Xilinx Coolunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. Coolunner-II CPLDs employ Fast Zero Power (FZP), a design technique that makes use of CMOS technology in both the fabrication and design methodology. FZP design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx Coolunner-II CPLDs achieve both high-performance and low power operation. Supported Standards The Coolunner-II 256 macrocell features LVCMOS, LVTTL, SSTL and HSTL implementations. See Table 1 for standard voltages. The LVTTL standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL standards make use of a V EF pin for JEDEC compliance. Coolunner-II CPLDs are also 1.5V compatible with the use of Schmitt-trigger inputs Table 1: Standards for XC2C256 Types Output V CCIO Input V CCIO Input V EF Board Termination Voltage V TT LVTTL N/A N/A LVCMOS N/A N/A LVCMOS N/A N/A LVCMOS N/A N/A 1.5V N/A N/A HSTL SSTL SSTL ICC (ma) Frequency (MHz) DS094_01_ Figure 1: I CC vs Frequency Table 2: I CC vs Frequency (LVCMOS 1.8V T A = 25 C) (1) Frequency (MHz) Typical -6, -7.5 I CC (ma) Typical -5 I CC (ma) Notes: bit up/down, resettable binary counter (one counter per function block). 2 DS094 (v1.2) November 20, Advance Product Specification
3 XC2C256 Coolunner-II CPLD Absolute Maximum atings Symbol Description Value Units V CC Supply voltage relative to ground 0.5 to 2.0 V V CCIO Supply voltage for output drivers 0.5 to 4.0 V V JTAG JTAG input voltage limits 0.5 to 4.0 V V AUX JTAG input supply voltage 0.5 to 4.0 V V IN Input voltage relative to ground (1) 0.5 to 4.0 V V TS Voltage applied to 3-state output (1) 0.5 to 4.0 V T STG Storage Temperature (ambient) 65 to +150 C T SOL Maximum Soldering temperature 1/16in. = 1.5mm) +260 C T J Junction Temperature +150 C Notes: 1. Maximum DC undershoot below must be limited to either 0.5V or 10 ma, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. ecommended Operating Conditions Symbol Parameter Min Max Units V CC Supply voltage for internal logic Commercial T A = 0 C to +70 C V and input buffers Industrial T A = 40 C to +85 C V V CCIO Supply voltage for output 3.3V operation V Supply voltage for output 2.5V operation V Supply voltage for output 1.8V operation V Supply voltage for output 1.5V operation V V AUX JTAG programming V DC Electrical Characteristics (Over ecommended Operating Conditions) Symbol Parameter Test Conditions Max. Units I CCSB Standby current (-6, -7) V CC = 1.9V, V CCIO = 3.6V 100 µa I CCSB Standby current (-5) V CC = 1.9V, V CCIO = 3.6V ma I CC Dynamic current (-6, -7) f = 1 MHz ma f = 50 MHz ma I CC Dynamic current (-5) f = 1 MHz ma f = 50 MHz ma C JTAG JTAG input capacitance f = 1 MHz 10 pf C CLK Global clock input capacitance f = 1 MHz 12 pf C IO capacitance f = 1 MHz 10 pf Notes: bit up/down, resettable binary counter (one counter per function block) tested at V CC =V CCIO = 1.9V DS094 (v1.2) November 20, Advance Product Specification
4 XC2C256 Coolunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage I OH = 8 ma, V CCIO = 3V V CCIO 0.4V - V I OH = 0.1 ma, V CCIO = 3V V CCIO 0.2V - V V OL Low level output voltage I OL = 8 ma, V CCIO = 3V V I OL = 0.1 ma, V CCIO = 3V V I IL Input leakage current V IN = 0V or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0V or V CCIO to 3.9V 1 1 µa LVCMOS 2.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage I OH = 8 ma, V CCIO = 2.3V V CCIO 0.4V - V I OH = 0.1 ma, V CCIO = 2.3V V CCIO 0.2V - V V OL Low level output voltage I OL = 8 ma, V CCIO = 2.3V V I OL = 0.1mA, V CCIO = 2.3V V I IL Input leakage current V IN = 0V or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0V or V CCIO to 3.9V 1 1 µa LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage 0.65 x V CCIO 3.9 V V IL Low level input voltage x V CCIO V V OH High level output voltage I OH = 8 ma, V CCIO = 1.7V V CCIO V I OH = 0.1 ma, V CCIO = 1.7V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.7V V I OL = 0.1 ma, V CCIO = 1.7V V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1 1 µa 4 DS094 (v1.2) November 20, Advance Product Specification
5 XC2C256 Coolunner-II CPLD 1.5V DC Voltage Specifications (1) Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V T+ Input hysteresis threshold voltage 0.5 x V CCIO 0.8 x V CCIO V V T 0.2 x V CCIO 0.5 x V CCIO V V OH High level output voltage I OH = 8 ma, V CCIO = 1.4V V CCIO V I OH = 0.1 ma, V CCIO = 1.4V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.4V V I OL = 0.1 ma, V CCIO = 1.4V V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1 1 µa Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V T+ Input hysteresis threshold voltage 0.5 x V CCIO 0.8 x V CCIO V V T 0.2 x V CCIO 0.5 x V CCIO V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1 1 µa SSTL2-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V CCIO Input source voltage V V (1) EF Input reference voltage V V (2) TT Termination voltage V EF V EF V V IH High level input voltage V EF V V IL Low level input voltage V EF 0.18 V V OH High level output voltage I OH = 8 ma, V CCIO = 2.3V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 2.3V V I IL Input leakage current V IN = 0V or V CCIO to 3.9V 1-1 µa I IH High-Z leakage V IN = 0V or V CCIO to 3.9V 1-1 µa Notes: 1. V EF should track the variations in V CCIO, also peak to peak ac noise win V EF may not exceed ±2% V EF 2. V TT of transmitting device must track V EF of receiving devices DS094 (v1.2) November 20, Advance Product Specification
6 XC2C256 Coolunner-II CPLD SSTL3-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V CCIO Input source voltage V V (1) EF Input reference voltage V V (2) TT Termination voltage V EF V EF V V IH High level input voltage V EF V CCIO V V IL Low level input voltage V EF 0.2 V V OH High level output voltage I OH = 8 ma, V CCIO = 3V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 3V V I IL Input leakage current V IN = 0V or V CCIO to 3.9V 1-1 µa I IH High-Z leakage V IN = 0V or V CCIO to 3.9V 1-1 µa Notes: 1. V EF should track the variations in V CCIO, also peak to peak ac noise win V EF may not exceed ±2% V EF 2. V TT of transmitting device must track V EF of receiving devices HSTL1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V CCIO Input source voltage V V (1) EF Input reference voltage V V (2) TT Termination voltage - V CCIO * V V IH High level input voltage V EF V V IL Low level input voltage V EF 0.1 V V OH High level output voltage I OH = 8 ma, V CCIO = 1.7V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.7V V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1-1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1-1 µa Notes: 1. V EF should track the variations in V CCIO, also peak to peak ac noise win V EF may not exceed ±2% V EF 2. V TT of transmitting device must track V EF of receiving devices 6 DS094 (v1.2) November 20, Advance Product Specification
7 XC2C256 Coolunner-II CPLD AC Electrical Characteristics Over ecommended Operating Conditions Unit Symbol Parameter Min. Max. Min. Max. Min. Max. s T PD1 Propagation delay single p-term ns T PD2 Propagation delay O array ns T SUF Fast input register p-term clock setup time ns T SU1 Setup time fast (single p-term) ns T SU2 Setup time (O array) ns T HF Fast input register hold time ns T H P-term hold time ns T CO Clock to output ns F (1) TOGGLE Internal toggle rate MHz F (2) SYSTEM1 Maximum system frequency MHz F (2) SYSTEM2 Maximum system frequency MHz F (3) EXT1 Maximum external frequency MHz F (3) EXT2 Maximum external frequency MHz T PSUF Fast input register p-term clock setup time ns T PSU1 P-term clock setup time (single p-term) ns T PSU2 P-term clock setup time (O array) ns T PHF Fast input register p-term clock hold time ns T PH P-term clock hold ns T PCO P-term clock to output ns T OE /T OD Global OE to output enable/disable ns T POE /T POD P-term OE to output enable/disable ns T MOE /T MOD Macrocell driven OE to output enable/disable ns T PAO P-term set/reset to output valid ns T AO Global set/reset to output valid ns T SUEC egister clock enable setup time ns T HEC egister clock enable hold time ns T CW Global clock pulse width High or Low ns T PCW P-term pulse width High or Low ns T DGSU Set-up before DataGATE latch assertion ns T DGHO Hold to DataGATE latch assertion ns T DG DataGATE recovery to new data ns T DGW DataGATE high pulse width ns T CDSU CDST setup time before falling edge GCLK ns T CDHO Hold time CDST after falling edge GCLK ns T CONFIG Configuration time µs Notes: 1. F TOGGLE (1/2*T CW ) is the maximum frequency of a dual edge triggered T flip-flop with output enabled. 2. F SYSTEM1 (1/T CYCLE ) is the internal operating frequency for a device fully populated with 16-bit resettable binary counter through one p-term per macrocell while F SYSTEM2 is through the O array (one counter per function block). 3. F EXT1 (1/T SU2 +T CO ) is the maximum external frequency using one p-term while F EXT2 is through the O array. DS094 (v1.2) November 20, Advance Product Specification
8 XC2C256 Coolunner-II CPLD Internal Timing Parameters Symbol Parameter (1) Min. Max. Min. Max. Min. Max. Units Buffer Delays T IN Input buffer delay ns T FIN Fast data register input delay ns T GCK Global Clock buffer delay ns T GS Global set/reset buffer delay ns T GTS Global 3-state buffer delay ns T OUT Output buffer delay ns T EN Output buffer enable/disable delay ns P-term Delays T CT Control term delay ns T LOGI1 Single P-term delay adder ns T LOGI2 Multiple P-term delay adder ns Macrocell Delay T PDI Input to output valid ns T SUI Setup before clock ns T HI Hold after clock ns T ECSU Enable clock setup time ns T ECHO Enable clock hold time ns T COI Clock to output valid ns T AOI Set/reset to output valid ns T CDBL Clock doubler delay ns Feedback Delays T F Feedback delay ns T OEM Macrocell to global OE delay ns Standard Time Adder Delays 1.5V T IN15 Standard input adder ns T HYS15 Hysteresis input adder ns T OUT15 Output adder ns T SLEW15 Output slew rate adder ns Standard Time Adder Delays 1.8V CMOS T IN18 Standard input adder ns T HYS18 Hysteresis input adder ns T OUT18 Output adder ns T SLEW Output slew rate adder ns 8 DS094 (v1.2) November 20, Advance Product Specification
9 XC2C256 Coolunner-II CPLD Internal Timing Parameters (Continued) Symbol Parameter (1) Min. Max. Min. Max. Min. Max. Standard Time Adder Delays 2.5V CMOS T IN25 Standard input adder ns T HYS25 Hysteresis input adder ns T OUT25 Output adder ns T SLEW25 Output slew rate adder ns Standard Time Adder Delays 3.3V CMOS/TTL T IN33 Standard input adder ns T HYS33 Hysteresis input adder ns T OUT33 Output adder ns T SLEW33 Output slew rate adder ns Standard Time Adder Delays HSTL, SSTL SSTL2-1 Input adder to TIN, TFIN, TGCK, ns TGS,TGTS Output adder to TOUT ns SSTL3-1 Input adder to TIN, TFIN, TGCK, ns TGS,TGTS Output adder to TOUT ns HSTL-1 Input adder to TIN, TFIN, TGCK, ns TGS,TGTS Output adder to TOUT ns Notes: ns input pin signal rise/fall. Switching Characteristics Units 5.5 VCC = VCCIO = 25 o C 5.0 TPD_PAL (ns) Number of Outputs Switching DS094_02_ DS094 (v1.2) November 20, Advance Product Specification
10 XC2C256 Coolunner-II CPLD 11 Pin Descriptions Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank B B4 2 1(GS) 3 99 A C A A B A B A A E B C5-197 C7 2 2(GTS2) 1 1 A1 2 3 D C3 2 2(GTS3) 3 2 B2 3 5 E B1 4 6 B2 2 2(GTS0) 5 3 C3 5 7 D D (GTS1) 12 4 C2 6 9 E C B D E C D1 - - E2 2 Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank A B D B A5-193 E A C6 191 D B B6-188 C A A C7-186 E B E E F F E G E G F F F G F H G1-22 H H H H DS094 (v1.2) November 20, Advance Product Specification
11 XC2C256 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank L N N2 1 5(GCK1) 4 23 L M L P1 1 5(GCK0) 6 22 K M L N L M K1-38 L M N3 1 6 (CDST) 2 24 M P P4 1 6(GCK2) 4 27 N P T (DGE) P T M N N P M M Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank K L K L J K J K H J H K H J G J G J J N N M T P M T N P P T M6-74 N N M7 1 DS094 (v1.2) November 20, Advance Product Specification
12 XC2C256 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank C B B B C A A C C B D B A E A A C C A A A B B C C C G D B D D E D C F E F E E G13 2 Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank B B D A A D C B E A F B B C C C A D F G E H F F F H F G G H G G H H J DS094 (v1.2) November 20, Advance Product Specification
13 XC2C256 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank N N T M N M N M M M P L N L L M P P P P P M N N P T P N M P N10 1 Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank L L L M M K L K K K L J K J J H J H J P M8-88 T N N M P T M P N T N P T6 1 Notes: 1. GTS = global output enable, GS = global reset/set, GCK = global clock, CDST = clock divide reset, DGE = DataGATE enable. DS094 (v1.2) November 20, Advance Product Specification
14 XC2C256 Coolunner-II CPLD XC2C256 JTAG, Power/Ground, No Connect Pins and Total User Pin Type VQ100 CP132 TQ144 PQ208 FT256 TCK 48 M P12 TDI 45 M TDO 83 B A10 TMS 47 N N12 V AUX (JTAG supply voltage) 5 D F4 Power internal (V CC ) 26, 57 P1, K12, A2 1, 37, 84 1, 53, 124 P3, K13, D12, D5 Power Bank 1 (V CCIO1 ) 20, 38, 51 J3, P7, G14, P13 27, 55, 73, 93 33, 59, 79, 92, 105, 132 Power Bank 2 (V CCIO2 ) 88, 98 A14, C4, A7 109, 127, , 133, 157, 172, 181, 204 Ground 21, 25, 31, 62, 69, 75, 84, 100 K2, N1, P4, N9, N12, J14, H14, E14, B14, A9, B3 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, , 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 J6, K6, L7, L8, J11, K11, L10, L9 F7, F8, G6, H6, F10, F9, H11 F11, F6, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, L11, L6 No connects A1, C2, E6, D1, E1, G2, F1, G1, M4, T9, P9, M9, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14, D6, C6, E7, C5 Total user DS094 (v1.2) November 20, Advance Product Specification
15 XC2C256 Coolunner-II CPLD Ordering Information Part Number Pin/Ball Spacing θ JA (C/Watt) θ JC (C/Watt) Package Type Package Body Dimensions Commercial (C) Industrial (I) XC2C256-5VQ mm Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-6VQ mm Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-7VQ mm Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-5CP mm Chip Scale Package 8mm x 8mm 106 C XC2C256-6CP mm Chip Scale Package 8mm x 8mm 106 C XC2C256-7CP mm Chip Scale Package 8mm x 8mm 106 C XC2C256-5TQ mm Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-6TQ mm Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-7TQ mm Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-5PQ mm Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-6PQ mm Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-7PQ mm Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-5FT mm Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-6FT mm Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-7FT mm Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-7VQ mm Very Thin Quad Flat 14mm x 14mm 80 I Pack XC2C256-7CP mm Chip Scale Package 8mm x 8mm 106 I XC2C256-7TQ mm Thin Quad Flat Pack 20mm x 20mm 118 I XC2C256-7PQ mm Plastic Quad Flat 28mm x 28mm 173 I Pack XC2C256-7FT mm Fine Pitch Thin BGA 17mm x 17mm 184 I DS094 (v1.2) November 20, Advance Product Specification
16 XC2C256 Coolunner-II CPLD (3) TDO (1) (1) (1) (1) VAUX (2) (2) (4) VQ100 Top View VCC VCC (2) (5) TDI TMS TCK Figure 2: VQ100 Very Thin Quad Flat Pack (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - Data Gate 16 DS094 (v1.2) November 20, Advance Product Specification
17 XC2C256 Coolunner-II CPLD P N M VCC (5) (2) TMS (4) TDI TCK L (2) K (2) VCC J H G CP132 Bottom View F E D VAUX C B A (1) (1) (1) TDO (1) VCC (3) (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable Figure 3: CP132 Chip Scale Package DS094 (v1.2) November 20, Advance Product Specification
18 XC2C256 Coolunner-II CPLD VCC (1) (1) (1) (1) VAUX (2) (2) (4) TQ144 Top View VCC (2) (5) TDI TMS TCK (3) TDO VCC Figure 4: TQ144 Thin Quad Flat Pack (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable 18 DS094 (v1.2) November 20, Advance Product Specification
19 XC2C256 Coolunner-II CPLD DS094 (v1.2) November 20, Advance Product Specification Figure 5: PQ208 Quad Flat Package VCC (1) (1) (1) (1) VAUX (2) (2) (4) PQ208 Top View VCC (2) (5) TDI TMS TCK (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable VCC (3) TDO
20 XC2C256 Coolunner-II CPLD A B C D E F G H J K L M N P T TDO NC NC NC NC (3) NC NC NC VCC NC VCC (1) (1) NC NC NC (1) (1) NC VAUX NC NC NC NC NC VCC NC NC NC NC (2) (2) TMS TCK NC NC (2) VCC (4) TDI NC NC NC NC NC (5) FT256 Bottom View Figure 6: FT256 Fine Pitch Thin BGA (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable evision History The following table shows the revision history for this document. Date Version evision 05/09/ Initial Xilinx release. 05/13/ Updated AC Electrical Characteristics and added new parameters. 11/20/ Corrected package user, added Voltage eferenced DC tables DS094 (v1.2) November 20, Advance Product Specification
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