XC9572 In-System Programmable CPLD. Power Management. Features. Description. December 4, 1998 (Version 3.0) 1 1* Product Specification

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1 1 XC9572 In-System Programmable CPLD December 4, 1998 (Version 3.0) 1 1* Product Specification Features 7.5 ns pin-to-pin logic delays on all pins f CNT to 125 MHz 72 macrocells with 1,600 usable gates Up to 72 user pins 5 V in-system programmable (ISP) - Endurance of 10,000 program/erase cycles - Program/erase over full commercial voltage and temperature range Enhanced pin-locking architecture Flexible 36V18 Block - 90 product terms drive any or all of 18 macrocells within Block - Global and product term clocks, output enables, set and reset signals Extensive IEEE Std boundary-scan (JTAG) support Programmable power reduction mode in each macrocell Slew rate control on individual outputs User programmable ground pin capability Extended pattern security features for design protection High-drive 24 ma outputs 3.3 V or 5 V capability Advanced CMOS 5V FastFLASH technology Supports parallel programming of more than one XC9500 concurrently Available in 44-pin PLCC, 84-pin PLCC, -pin PQFP and -pin TQFP packages Description The XC9572 is a high-performance CPLD providing advanced in-system programming and test capabilities for general purpose logic integration. It is comprised of four 36V18 Blocks, providing 1,600 usable gates with propagation delays of 7.5 ns. See Figure 2 for the architecture overview. Power Management Power dissipation can be reduced in the XC9572 by configuring macrocells to standard or low-power modes of operation. Unused macrocells are turned off to minimize power dissipation. Operating current for each design can be approximated for specific operating conditions using the following equation: I CC (ma) = MC HP (1.7) + MC LP (0.9) + MC (0.006 ma/mhz) f Where: MC HP = Macrocells in high-performance mode MC LP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) Figure 1 shows a typical calculation for the XC9572 device. Typical I cc (ma) 200 (125) (65) 0 High Performance Low Power 50 Clock Frequency (MHz) (160) () Figure 1: Typical I CC vs. Frequency for XC9572 December 4, 1998 (Version 3.0) 1

2 JTAG Port 1 3 JTAG Controller In-System Programming Controller Block 1 Macrocells 1 to 18 /GCK /GSR /GTS Blocks FastCONNECT Switch Matrix Block 2 Macrocells 1 to 18 Block 3 Macrocells 1 to 18 Block 4 Macrocells 1 to 18 Figure 2: XC9572 Architecture X5921 Note: Block outputs (indicated by the bold line) drive the Blocks directly 2 December 4, 1998 (Version 3.0)

3 Absolute Maximum Ratings Symbol Parameter Value Units V CC Supply voltage relative to GND -0.5 to 7.0 V V IN DC input voltage relative to GND -0.5 to V CC V V TS Voltage applied to 3-state output with respect to GND -0.5 to V CC V T STG Storage temperature -65 to +150 C T SOL Max soldering temperature (10 1/16 in = 1.5 mm) +260 C Warning:Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Rating conditions for extended periods of time may affect device reliability. Recommended Operation Conditions 1 Symbol Parameter Min Max Units V CCINT Supply voltage for internal logic and input buffer V (4.5) (5.5) V CCIO Supply voltage for output drivers for 5 V operation 4.75 (4.5) 5.25 (5.5) V Supply voltage for output drivers for 3.3 V operation V V IL Low-level input voltage V V IH High-level input voltage 2.0 V CCINT +0.5 V V O Output voltage 0 V CCIO V Note: 1. Numbers in parenthesis are for industrial temperature range versions. Endurance Characteristics Symbol Parameter Min Max Units t DR Data Retention 20 - Years N PE Program/Erase Cycles 10,000 - Cycles December 4, 1998 (Version 3.0) 3

4 DC Characteristics Over Recommended Operating Conditions Symbol Parameter Test Conditions Min Max Units V OH Output high voltage for 5 V operation I OH = -4.0 ma 2.4 V V CC = Min Output high voltage for 3.3 V operation I OH = -3.2 ma V CC = Min 2.4 V V OL Output low voltage for 5 V operation I OL = 24 ma 0.5 V V CC = Min Output low voltage for 3.3 V operation I OL = 10 ma 0.4 V V CC = Min I IL Input leakage current V CC = Max ±10.0 µa V IN = GND or V CC I IH high-z leakage current V CC = Max ±10.0 µa V IN = GND or V CC C IN capacitance V IN = GND 10.0 pf f = 1.0 MHz I CC Operating Supply Current (low power mode, active) V I = GND, No load f = 1.0 MHz 65 (Typ) ma AC Characteristics Symbol Parameter XC XC XC Min Max Min Max Min Max Note: 1. f CNT is the fastest 16-bit counter frequency available, using the local feedback when applicable. f CNT is also the Export Control Maximum flip-flop toggle rate, f TOG. 2. f SYSTEM is the internal operating frequency for general purpose system designs spanning multiple FBs. Units t PD to output valid ns t SU setup time before GCK ns t H hold time after GCK ns t CO GCK to output valid ns f 1 CNT 16-bit counter frequency MHz 2 f SYSTEM Multiple FB internal operating frequency MHz t PSU setup time before p-term clock input ns t PH hold time after p-term clock input ns t PCO P-term clock to output valid ns t OE GTS to output valid ns t OD GTS to output disable ns t POE Product term OE to output enabled ns t POD Product term OE to output disabled ns t WLH GCK pulse width (High or Low) ns V TEST Device Output R 1 R 2 C L Output Type V CCIO 5.0 V 3.3 V V TEST 5.0 V 3.3 V R Ω 260 Ω R Ω 360 Ω C L 35 pf 35 pf X5906 Figure 3: AC Load Circuit 4 December 4, 1998 (Version 3.0)

5 Internal Timing Parameters Symbol Parameter XC XC XC Min Max Min Max Min Max Units Buffer Delays t IN Input buffer delay ns t GCK GCK buffer delay ns t GSR GSR buffer delay ns t GTS GTS buffer delay ns t OUT Output buffer delay ns t EN Output buffer enable/disable delay ns Product Term Control Delays t PTCK Product term clock delay ns t PTSR Product term set/reset delay ns t PTTS Product term 3-state delay ns Internal Register and Combinatorial delays t PDI Combinatorial logic propagation delay ns t SUI Register setup time ns t HI Register hold time ns t COI Register clock to output valid time ns t AOI Register async. S/R to output delay ns t RAI Register async. S/R recovery before clock ns t LOGI Internal logic delay ns t LOGILP Internal low power logic delay ns Feedback Delays t F FastCONNECT matrix feedback delay ns t LF Block local feeback delay ns Time Adders t 3 PTA Incremental Product Term Allocator delay ns t SLEW Slew-rate limited delay ns Note: 3. t PTA is multiplied by the span of the function as defined in the family data sheet. December 4, 1998 (Version 3.0) 5

6 XC9572 Pins Block Macrocell PC 44 PC 84 PQ TQ BScan Order Notes Block Macrocell PC 44 PC 84 PQ TQ BScan Order [1] [1] [1] [2] [1] [1] [3] Notes Notes: [1] Global control pin [2] Global control pin GTS1 for PC84, PQ, and TQ [3] Global control pin GTS1 for PC44 6 December 4, 1998 (Version 3.0)

7 XC9572 Global, JTAG and Power Pins Pin Type PC44 PC84 PQ TQ /GCK /GCK /GCK /GTS /GTS /GSR TCK TDI TDO TMS V CCINT 5 V 21,41 38,73,78 7,59, 5,57,98 V CCIO 3.3 V/5 V 32 22,64 28,40,53,90 26,38,51,88 GND 10,23,31 8,16,27,42, 49,60 2,23,33,46,64,71, 77,86,21,31,44,62,69, 75, 84 No Connects 4,9,21,26,36,45,48, 75, 82 2,7,19,24,34,43,46, 73, 80 December 4, 1998 (Version 3.0) 7

8 Ordering Information XC PQ C Device Type Speed Temperature Range Number of Pins Package Type Speed Options ns pin-to-pin delay ns pin-to-pin delay ns pin-to-pin delay Packaging Options PC44 44-Pin Plastic Leaded Chip Carrier (PLCC) PC84 84-Pin Plastic Leaded Chip Carrier (PLCC) PQ -Pin Plastic Quad Flat Pack (PQFP) TQ -Pin Very Thin Quad Flat Pack (TQFP) Temperature Options C I Commercial0 C to +70 C Industrial 40 C to +85 C Component Availability Pins Type Plastic PLCC C = Commercial = 0 to +70 C I = Industrial = 40 to +85 C Revision Control Plastic PLCC Plastic PQFP Plastic TQFP Code PC44 PC84 PQ TQ 15 C(I) C(I) C(I) C(I) XC C(I) C(I) C(I) C(I) 7 C C C C Date Revision 12/04/98 Update AC Characteristics and Internal Parameters 8 December 4, 1998 (Version 3.0)

XC9572 In-System Programmable CPLD

0 XC9572 In-System Programmable CPLD October 28, 1997 (Version 2.0) 0 3* Product Specification Features 7.5 ns pin-to-pin logic delays on all pins f CNT to 125 MHz 72 macrocells with 1,600 usable gates