XC9572XV High-performance CPLD R JTAG Port 1 3 JTAG Controller In-System Programming Controller Block 1 Macrocells 1 to 18 /GCK /GSR /GTS

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1 R 0 XC9572XV High-performance CPLD DS052 (v2.2) August 27, Advance Product Specification Features 72 macrocells with 1,600 usable gates Available in small footprint packages - 44-pin PLCC (34 user pins) - 44-pin VQFP (34 user pins) - 48-pin CSP (38 user pins) pin TQFP (72-user pins) Optimized for high-performance 2.5V systems - Low power operation - Multi-voltage operation Advanced system features - In-system programmable - Two separate output banks - Superior pin-locking and routability with FastCONNECT II switch matrix - Extra wide 54-input Blocks - Up to 90 product-terms per macrocell with individual product-term allocation - Local clock inversion with three global and one product-term clocks - Individual output enable per output pin - Input hysteresis on all user and boundary-scan pin inputs - Bus-hold ciruitry on all user pin inputs - Full IEEE Standard boundary-scan (JTAG) Fast concurrent programming Slew rate control on individual outputs Enhanced data security features Excellent quality and reliability - Endurance exceeding 10,000 program/erase cycles - 20 year data retention - ESD protection exceeding 2,000V Description The XC9572XV is a 2.5V CPLD targeted for high-performance, low-voltage applications in leading-edge communications and computing systems. It is comprised of four 54V18 Blocks, providing 1,600 usable gates with propagation delays of 4 ns. Power Estimation Power dissipation in CPLDs can vary substantially depending on the system frequency, design application and output loading. To help reduce power dissipation, each macrocell in a XC9500XV device may be configured for low-power mode (from the default high-performance mode). In addition, unused product-terms and macrocells are automatically deactivated by the software to further conserve power. For a general estimate of I CC, the following equation may be used: I CC (ma) = MC HP (0.36) + MC LP (0.23) + MC(0.005 ma/mhz) f Where: MC HP = Macrocells in high-performance (default) mode MC LP = Macrocells in low-power mode MC = Total number of macrocells used f = Clock frequency (MHz) This calculation is based on typical operating conditions using a pattern of 16-bit up/down counters in each Block with no output loading. The actual I CC value varies with the design application and should be verified during normal system operation. Figure 1 shows the above estimation in a graphical form. Typical I CC (ma) High Performance Low Power Clock Frequency (MHz) DS052_01_ Figure 1: Typical I CC vs. Frequency for XC9572XV 2001 Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS052 (v2.2) August 27, Advance Product Specification

2 XC9572XV High-performance CPLD R JTAG Port 1 3 JTAG Controller In-System Programming Controller Block 1 Macrocells 1 to 18 /GCK /GSR /GTS Blocks FastCONNECT II Switch Matrix Block 2 Macrocells 1 to 18 Block 3 Macrocells 1 to 18 Block 4 Macrocells 1 to 18 DS052_02_ Figure 2: XC9572XV Architecture Block outputs (indicated by the bold line) drive the Blocks directly. 2 DS052 (v2.2) August 27, Advance Product Specification

3 R XC9572XV High-performance CPLD Absolute Maximum Ratings Symbol Description Value Units V CC Supply voltage relative to GND 0.5 to 2.7 V V CCIO Supply voltage for output drivers 0.5 to 3.6 V V IN Input voltage relative to GND (1) 0.5 to 3.6 V V TS Voltage applied to 3-state output (1) 0.5 to 3.6 V T STG Storage temperature (ambient) 65 to +150 o C T SOL Maximum soldering temperature 1/16 in. = 1.5 mm) +260 o C T J Junction temperature +150 o C 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 ma, whichever is easier to achieve. During transitions, the device pins may undershoot to 2.0V or overshoot to +3.6V, provided this over- or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. 2. Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Recommended Operation Conditions Symbol Parameter Min Max Units V CCINT Supply voltage for internal logic and input buffers Quality and Reliability Characteristics Commercial T A = 0 o C to +70 o C V Industrial T A = 40 o C to +85 o C V CCIO Supply voltage for output drivers for 3.3V operation V Supply voltage for output drivers for 2.5V operation V Supply voltage for output drivers for 1.8V operation V V IL Low-level input voltage V V IH High-level input voltage V V O Output voltage 0 V CCIO V Symbol Parameter Min Max Units T DR Data retention 20 - Years N PE Program/Erase cycles (endurance) 10,000 - Cycles V ESD Electrostatic Discharge (ESD) 2,000 - Volts DS052 (v2.2) August 27, Advance Product Specification

4 XC9572XV High-performance CPLD R DC Characteristics (Over Recommended Operating Conditions) Symbol Parameter Test Conditions Min Max Units V OH Output high voltage for 3.3V outputs I OH = 4.0 ma V AC Characteristics Output high voltage for 2.5V outputs I OH = 1.0 ma V Output high voltage for 1.8V outputs I OH = 100 µa 90% V CCIO - V V OL Output low voltage for 3.3V outputs I OL = 8.0 ma V Output low voltage for 2.5V outputs I OL = 1.0 ma V Output low voltage for 1.8V outputs I OL = 100 µa V I IL Input leakage low current V CC = 2.62V V CCIO = 3.6V V IN = GND or 3.6V I IH Input leakagehigh current V CC = 2.62V V CCIO = 3.6V V IN = GND or 3.6V C IN capacitance V IN = GND f = 1.0 MHz I CC Operating Supply Current (low power mode, active) V I = GND, No load f = 1.0 MHz - 10 µa - 10 µa - 10 pf 14 ma XC9572XV-4 XC9572XV-5 XC9572XV-7 Symbol Parameter Min Max Min Max Min Max Units T PD to output valid ns T SU setup time before GCK ns T H hold time after GCK ns T CO GCK to output valid ns f SYSTEM Multiple FB internal operating MHz frequency T PSU setup time before p-term clock ns input T PH hold time after p-term clock input ns T PCO P-term clock output valid ns T OE GTS to output valid ns T OD GTS to output disable ns T POE Product term OE to output enabled ns T POD Product term OE to output disabled ns T AO GSR to output valid ns T PAO P-term S/R to output valid ns T WLH GCK pulse width (High or Low) ns T PLH P-term clock pulse width (High or Low) ns Advance Information Preliminary Information 1. Please contact Xilinx for up-to-date information on advance specifications. 4 DS052 (v2.2) August 27, Advance Product Specification

5 R XC9572XV High-performance CPLD V TEST Device Output R 1 R 2 C L Output Type V CCIO 3.3V 2.5V 1.8V V TEST 3.3V 2.5V 1.8V R 1 320Ω 250Ω 10KΩ R 2 360Ω 660Ω 14KΩ C L 35 pf 35 pf 35 pf DS051_03_ Internal Timing Parameters Figure 3: AC Load Circuit XC9572XV-4 XC9572XV-5 XC9572XV-7 Symbol Parameter Min Max Min Max Min Max Units Buffer Delays T IN Input buffer delay ns T GCK GCK buffer delay ns T GSR GSR buffer delay ns T GTS GTS buffer delay ns T OUT Output buffer delay ns T EN Output buffer enable/disable delay ns Product Term Control Delays T PTCK Product term clock delay ns T PTSR Product term set/reset delay ns T PTTS Product term 3-state delay ns Internal Register and Combinatorial Delays T PDI Combinatorial logic propagation delay ns T SUI Register setup time ns T HI Register hold time ns T ECSU Register clock enable setup time ns T ECHO Register clock enable hold time ns T COI Register clock to output valid time ns T AOI Register async. S/R to output delay ns T RAI Register async. S/R recover before clock ns T LOGI Internal logic delay ns T LOGILP Internal low power logic delay ns Feedback Delays T F FastCONNECT II feedback delay ns Time Adders T PTA Incremental product term allocator delay ns T PTA2 Adjacent macrocell p-term allocator delay ns T SLEW Slew-rate limited delay ns Advance Information Preliminary Information 1. Please contact Xilinx for up-to-date information on advance specifications. DS052 (v2.2) August 27, Advance Product Specification

6 XC9572XV High-performance CPLD R XC9572XV Pins Block Macrocell PC44 VQ44 CS48 TQ100 BScan Order Block Macrocell PC44 VQ44 CS48 TQ D B D C D A C C B (1) 43 (1) B7 (1) 22 (1) A D (1) 44 (1) B6 (1) 23 (1) B (1) 1 (1) A7 (1) 27 (1) B A C D C C F E G E F E (2) G F (1) 33 (1) G7 (1) 99 (1) (1) 34 (1) F6 (1) 4 (1) G (3) 36 (3) E6 (3) 9 (3) F E E E G Global control pin. 2. GTS1 for TQ GTS1 for PC44, CS48, VQ44 BScan Order 6 DS052 (v2.2) August 27, Advance Product Specification

7 R XC9572XV High-performance CPLD XC9572XV Global, JTAG and Power Pins Pin Type PC44 VQ44 CS48 TQ100 /GCK B7 22 /GCK B6 23 /GCK3 7 1 A7 27 /GTS E6 3 /GTS F6 4 /GSR G7 99 TCK A1 48 TDI 15 9 B3 45 TDO G2 83 TMS A2 47 V CCINT 2.5V 21, 41 15, 35 C1, F7 5, 57, 98 V CCIO 1.8/2.5V/3.3V G3 26, 38, 51, 88 GND 10, 23, 31 4, 17, 25 A5, D1, F3 21, 31, 44, 62, 69, 75, 84, 100 No Connects , 7, 19, 24, 34, 43, 46, 73, 80 DS052 (v2.2) August 27, Advance Product Specification

8 XC9572XV High-performance CPLD R Ordering Information Example: Device Type Speed Grade XC9572XV -7 TQ 100 C Temperature Range Number of Pins Package Type Device Ordering Options Speed Package Temperature ns pin-to-pin delay PC44 44-pin Plastic Lead Chip Carrier (PLCC) C = Commercial T A = 0 C to +70 C -5 5 ns pin-to-pin delay VQ44 44-pin Very Thin Quad Flat Pack (VQFP) I = Industrial T A = 40 C to +85 C -4 4 ns pin-to-pin delay CS48 48-ball Chip Scale Package (CSP) TQ pin Thin Quad Flat Pack (TQFP) Component Availability Pins Type Plastic PLCC Plastic VQFP Plastic CSP Plastic TQFP Code PC44 VQ44 CS48 TQ100 XC9572XV -7 C, I C, I C, I C, I -5 C C C C -4 (C) (C) - (C) 1. C = Commercial (T A = 0 o C to +70 o C); I = Industrial (T A = 40 o C to +85 o C). 2. ( ) Parenthesis indicate future planned products. Please contact Xilinx for up-to-date information. Revision History Date Revision No. Description 02/01/ Initial Xilinx release. Advance information specification. 01/29/ Added -4 performance specification and VQ44 pagkage. Deleted VQ64 package. Updated I CC vs. Frequency Figure 1. 05/15/ Updated I CC formula, Recommended Operation Conditions, -4 and -5 AC Characteristics and Internal Timing Parameters 08/27/ Changed V CCIO 3.3V from 3.13 to 3.0 (min), 3.46 to 3.60 (max); DC characteristics: I IL - added "low" current, I IH - changed to "Input leakage high current"; Internal Timing: -5 T AOI from 6.5 to DS052 (v2.2) August 27, Advance Product Specification