XC2C32 CoolRunner-II CPLD

Transcription

1 0 XC2C32 Coolunner-II CPLD DS091 (v1.4) January 27, Advance Product Specification Features Optimized for 1.8V systems - As fast as 3.5 ns pin-to-pin logic delays - As low as 14 µa quiescent current Industries best 0.18 micron CMOS CPLD - Optimized architecture for effective logic systhesis - Multi-voltage operation 1.5V through 3.3V Available in multiple package options - 44-pin PLCC with 33 user - 44-pin VQFP with 33 user - 56-ball CP BGA with 33 user Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - FZP 100% CMOS product term generation - Flexible clocking modes Optional DualEDGE triggered registers - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Efficient control term clocks, output enables and set/resets for each macrocell and shared across function blocks - Advanced design security - Open-drain output option for Wired-O and LED drive - Optional configurable grounds on unused s - Mixed voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels - PLA architecture Superior pinout retention 100% product term routability across function block - Hot pluggable efer to the Coolunner -II family data sheet for architecture description. Description The Coolunner-II 32-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of two Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. The Coolunner-II 32-macrocell CPLD is compatible with standard LVTTL and LVCMOS18, LVCMOS25, and LVCMOS33 (see Table 1). This device is also 1.5V compatible with the use of Schmitt-trigger inputs Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS091 (v1.4) January 27, Advance Product Specification

2 XC2C32 Coolunner-II CPLD Fast Zero Power Design Technology Xilinx Coolunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. Coolunner-II CPLDs employ Fast Zero Power (FZP), a design technique that makes use of CMOS technology in both the fabrication and design methodology. FZP design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx Coolunner-II CPLDs achieve both high performance and low power operation. Supported Standards The Coolunner-II 32 macrocell features both LVCMOS and LVTTL implementations. See Table 1 for standard voltages. The LVTTL standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Coolunner-II CPLDs are also 1.5V compatible with the use of Schmitt-trigger inputs. Table 1: Standards for XC2C32 Types Output V CCIO Input V CCIO Input V EF Board Termination Voltage V T LVTTL N/A N/A LVCMOS N/A N/A LVCMOS N/A N/A LVCMOS N/A N/A 1.5V N/A N/A ICC (ma) 10-4, Frequency (MHz) Figure 1: I CC vs Frequency DS Table 2: I CC vs Frequency (LVCMOS 1.8V T A = 25 C) (1) Frequency (MHz) Typical -4, -6 I CC (ma) Typical -3 I CC (ma) bit up/down, resettable binary counter (one counter per function block). 2 DS091 (v1.4) January 27, Advance Product Specification

3 XC2C32 Coolunner-II CPLD Absolute Maximum atings Symbol Description Value Units V CC Supply voltage relative to ground 0.5 to 2.0 V V CCIO Supply voltage for output drivers 0.5 to 4.0 V V JTAG JTAG input voltage limits 0.5 to 4.0 V V AUX JTAG input supply voltage 0.5 to 4.0 V V IN Input voltage relative to ground (1) 0.5 to 4.0 V V TS Voltage applied to 3-state output (1) 0.5 to 4.0 V T STG Storage Temperature (ambient) 65 to +150 C T SOL Maximum Soldering temperature 1/16in. = 1.5mm) +260 C T J Junction Temperature +150 C 1. Maximum DC undershoot below GND must be limited to either 0.5V or 10 ma, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. ecommended Operating Conditions Symbol Parameter Min Max Units V CC Supply voltage for internal logic Commercial T A = 0 C to +70 C V and input buffers Industrial T A = 40 C to +85 C V V CCIO Supply voltage for output 3.3V operation V Supply voltage for output 2.5V operation V Supply voltage for output 1.8V operation V Supply voltage for output 1.5V operation V V AUX JTAG programming pins V DC Electrical Characteristics (Over ecommended Operating Conditions) Symbol Parameter Test Conditions Max. Units I CCSB Standby current (-4, -6) V CC = 1.9V, V CCIO = 3.6V 100 µa I CCSB Standby current (-3) V CC = 1.9V, V CCIO = 3.6V ma I (1) CC Dynamic current (-4, -6) f = 1 MHz 250 µa f = 50 MHz 2.5 ma I (1) CC Dynamic current (-3) f = 1 MHz ma f = 50 MHz ma C JTAG JTAG input capacitance f = 1 MHz 10 pf C CLK Global clock input capacitance f = 1 MHz 12 pf C IO capacitance f = 1 MHz 10 pf bit up/down resettable binary counter (one per Function Block) tested at V CC = V CCIO = 1.9V. DS091 (v1.4) January 27, Advance Product Specification

4 XC2C32 Coolunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage I OH = 8 ma, V CCIO = 3V V CCIO 0.4V - V I OH = 0.1 ma, V CCIO = 3V V CCIO 0.2V - V V OL Low level output voltage I OL = 8 ma, V CCIO = 3V V I OL = 0.1 ma, V CCIO = 3V V I IL Input leakage current V IN = 0V or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0V or V CCIO to 3.9V 1 1 µa LVCMOS 2.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage I OH = 8 ma, V CCIO = 2.3V V CCIO 0.4V - V I OH = 0.1 ma, V CCIO = 2.3V V CCIO 0.2V - V V OL Low level output voltage I OL = 8 ma, V CCIO = 2.3V V I OL = 0.1mA, V CCIO = 2.3V V I IL Input leakage current V IN = 0V or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0V or V CCIO to 3.9V 1 1 µa LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage 0.65 x V CCIO 3.9 V V IL Low level input voltage x V CCIO V V OH High level output voltage I OH = 8 ma, V CCIO = 1.7V V CCIO V I OH = 0.1 ma, V CCIO = 1.7V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.7V V I OL = 0.1 ma, V CCIO = 1.7V V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1 1 µa 4 DS091 (v1.4) January 27, Advance Product Specification

5 XC2C32 Coolunner-II CPLD 1.5V DC Voltage Specifications (1) Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V T+ Input hysteresis threshold voltage 0.5 x V CCIO 0.8 x V CCIO V V T 0.2 x V CCIO 0.5 x V CCIO V V OH High level output voltage I OH = 8 ma, V CCIO = 1.4V V CCIO V I OH = 0.1 ma, V CCIO = 1.4V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.4V V I OL = 0.1 ma, V CCIO = 1.4V V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1 1 µa 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V T+ Input hysteresis threshold voltage 0.5 x V CCIO 0.8 x V CCIO V V T 0.2 x V CCIO 0.5 x V CCIO V I IL Input leakage current V IN = 0 or V CCIO to 3.9V 1 1 µa I IH High-Z leakage V IN = 0 or V CCIO to 3.9V 1 1 µa DS091 (v1.4) January 27, Advance Product Specification

6 XC2C32 Coolunner-II CPLD AC Electrical Characteristics Over ecommended Operating Conditions Symbol Parameter Min. Max. Min. Max. Min. Max. T PD1 Propagation delay single p-term ns T PD2 Propagation delay O array ns T SUD Direct input register clock setup time ns T SU1 Setup time fast (single p-term) ns T SU2 Setup time (O array) ns T HD Direct input register hold time ns T H P-term hold time ns T CO Clock to output ns F TOGGLE (1) Internal toggle rate MHz F SYSTEM1 (2) Maximum system frequency MHz F SYSTEM2 (2) Maximum system frequency MHz F EXT1 (3) Maximum external frequency MHz F EXT2 (3) Maximum external frequency MHz T PSUD Direct input register p-term clock setup time ns T PSU1 P-term clock setup time (single p-term) ns T PSU2 P-term clock setup time (O array) ns T PHD Direct input register p-term clock hold time ns T PH P-term clock hold ns T PCO P-term clock to output ns T OE /T OD Global OE to output enable/disable ns T POE /T POD P-term OE to output enable/disable ns T MOE /T MOD Macrocell driven OE to output enable/disable Units ns T PAO P-term set/reset to output valid ns T AO Global set/reset to output valid ns T SUEC egister clock enable setup time ns T HEC egister clock enable hold time ns T CW Global clock pulse width High or Low ns T PCW P-term pulse width High or Low ns T CONFIG (4) Configuration time µs 1. F TOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the Coolunner-II family data sheet for more information). 2. F SYSTEM1 (1/T CYCLE ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while F SYSTEM2 is through the O array. 3. F EXT1 (1/T SU1 +T CO ) is the maximum external frequency using one p-term while F EXT2 is through the O array. 4. Typical configuration current during T CONFIG is 500 µa. 6 DS091 (v1.4) January 27, Advance Product Specification

7 XC2C32 Coolunner-II CPLD Internal Timing Parameters Symbol Parameter (1) Min. Max. Min. Max. Min. Max. Units Buffer Delays T IN Input buffer delay ns T DIN Direct register input delay ns T GCK Global Clock buffer delay ns T GS Global set/reset buffer delay ns T GTS Global 3-state buffer delay ns T OUT Output buffer delay ns T EN Output buffer enable/disable delay ns P-term Delays T CT Control term delay ns T LOGI1 Single p-term delay adder ns T LOGI2 Multiple p-term delay adder ns Macrocell Delay T PDI Input to output valid ns T SUI Setup before clock ns T HI Hold after clock ns T ECSU Enable clock setup time ns T ECHO Enable clock hold time ns T COI Clock to output valid ns T AOI Set/reset to output valid ns T CDBL Clock doubler delay ns Feedback Delays T F Feedback delay ns T OEM Macrocell to global OE delay ns Standard Time Adder Delays 1.5V T HYS15 Hysteresis input adder ns T OUT15 Output adder ns T SLEW15 Output slew rate adder ns Standard Time Adder Delays 1.8V CMOS T IN18 Standard input adder ns T HYS18 Hysteresis input adder ns T OUT18 Output adder ns T SLEW Output slew rate adder ns DS091 (v1.4) January 27, Advance Product Specification

8 XC2C32 Coolunner-II CPLD Internal Timing Parameters (Continued) Symbol Parameter (1) Min. Max. Min. Max. Min. Max. Units Standard Time Adder Delays 2.5V CMOS T IN25 Standard input adder ns T HYS25 Hysteresis input adder ns T OUT25 Output adder ns T SLEW25 Output slew rate adder ns Standard Time Adder Delays 3.3V CMOS/TTL T IN33 Standard input adder ns T HYS33 Hysteresis input adder ns T OUT33 Output adder ns T SLEW33 Output slew rate adder ns ns input pin signal rise/fall. Switching Characteristics V CC VCC = VCCIO = 25 o C Device Under Test Test Point C L Output Type 1 2 C L 4.5 LVTTL33 268Ω 235Ω 35 pf TPD2 (ns) 4.0 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS15 C L includes test fixtures and probe capacitance. 275Ω 188Ω 112.5Ω 150Ω 275Ω 188Ω 112.5Ω 150Ω 35 pf 35 pf 35 pf 35 pf Number of Outputs Switching 1.5 ns maximum rise/fall times on inputs. Figure 3: AC Load Circuit DS_ACT_08_14_02 DS091_02_ Figure 2: Derating Curve for T PD 8 DS091 (v1.4) January 27, Advance Product Specification

9 XC2C32 Coolunner-II CPLD 140 I OH = 3.3V 120 IO (Output Current ma) I OH = 2.5V 40 I OH = 1.8V I OL 0 0 I OH = 1.5V VO (Output Volts) Figure 4: Typical I/V Curve for XC2C32 Pin Descriptions DS091_04_ Function Block Macrocell PC44 VQ44 CP F E E1 1(GTS1) D1 1(GTS0) C1 1(GTS3) A3 1(GTS2) A2 1(GS) B A C C C A B C E G F H G3 2(GCK0) J1 DS091 (v1.4) January 27, Advance Product Specification

10 XC2C32 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell PC44 VQ44 CP56 2(GCK1) K1 2(GCK2) K K H K H H K H G F10 1. GTS = global output enable, GS = global set reset, GCK = global clock XC2C32 Global, JTAG, Power/Ground and No Connect Pins Pin Type PC44 VQ44 CP56 TCK K10 TDI 15 9 J10 TDO A6 TMS K9 Input Only D10 V AUX (JTAG supply voltage) D3 Power internal (V CC ) G8 Power external (V CCIO ) 13, 32 7,26 H6, C6 Ground 10,23,31 4,17,25 H4, F8, C7 No connects - - K4, K6, K7, H7, E10, A7, A9, D8, A5, A8, A4, C3 Total user Ordering Information Part Number Pin/Ball Spacing θ JA (C/Watt) θ JC (C/Watt) Package Type Package Body Dimensions Comm. (C) Ind. (I) XC2C32-3PC44C 1.27mm Plastic Leaded Chip 16.5mm x 16.5mm 33 C Carrier XC2C32-4PC44C 1.27mm Plastic Leaded Chip 16.5mm x 16.5mm 33 C Carrier XC2C32-6PC44C 1.27mm Plastic Leaded Chip 16.5mm x 16.5mm 33 C Carrier XC2C32-3VQ44C 0.8mm Very Thin Quad Flat Pack 10mm x 10mm 33 C 10 DS091 (v1.4) January 27, Advance Product Specification

11 XC2C32 Coolunner-II CPLD Part Number Pin/Ball Spacing θ JA (C/Watt) θ JC (C/Watt) Package Type Package Body Dimensions XC2C32-4VQ44C 0.8mm Very Thin Quad Flat Pack 10mm x 10mm 33 C XC2C32-6VQ44C 0.8mm Very Thin Quad Flat Pack 10mm x 10mm 33 C XC2C32-3CP56C 0.5mm Chip Scale Package 6mm x 6mm 33 C XC2C32-4CP56C 0.5mm Chip Scale Package 6mm x 6mm 33 C XC2C32-6CP56C 0.5mm Chip Scale Package 6mm x 6mm 33 C XC2C32-6PC44I 1.27mm Plastic Leaded Chip 16.5mm x 16.5mm 33 I Carrier XC2C32-6VQ44I 0.8mm Very Thin Quad Flat Pack 10mm x 10mm 33 I XC2C32-6CP56I 0.5mm Chip Scale Package 6mm x 6mm 33 I Comm. (C) Ind. (I) (2) (2) V AUX (1) (2) GND V CCIO TDI TMS TCK PC44 Top View (1) (1) (1) (3) V CCIO Gnd TDO V CC GND I (2) (2) V AUX (1) (2) GND V CCIO TDI TMS TCK VQ44 Top View (1) (1) (1) (3) V CCIO GND TDO V CC GND I Figure 5: PC44 Package (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset Figure 6: VQ44 Package (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset DS091 (v1.4) January 27, Advance Product Specification

12 XC2C32 Coolunner-II CPLD K J H G F E D C B A (2) (2) NC NC NC TMS TCK (2) TDI GND V CCIO NC V CC CP56 Bottom View GND NC (1) V AUX NC I (1) NC V CCIO GND (3) (1) (1) NC NC TDO NC NC NC evision History (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset Figure 7: CP56 Package The following table shows the revision history for this document. Date Version evision 06/04/ Initial Xilinx release. 10/18/ Add AC characteristics and minor edits. 11/26/ Minor edits. 01/09/ Minor edits. 01/27/ Updated Table 2, Typical -4, -6 device, at 0 from to ma 12 DS091 (v1.4) January 27, Advance Product Specification