XC2C256 CoolRunner-II CPLD

Transcription

1 0 XC2C256 Coolunner-II CPLD DS094 (v3.0) May 20, Features Optimized for 1.8V systems - As fast as 5.7 ns pin-to-pin delays - As low as 13 μa quiescent current Industry s best 0.18 micron CMOS CPLD - Optimized architecture for effective logic synthesis. efer to the Coolunner -II family data sheet for architecture description. - Multi-voltage operation 1.5V to 3.3V Available in multiple package options pin VQFP with 80 user pin TQFP with 118 user ball CP (0.5mm) BGA with 106 user pin PQFP with 173 user ball FT (1.0mm) BGA with 184 user - Pb-free available for all packages Advanced system features - Fastest in system programming 1.8V ISP using IEEE 1532 (JTAG) interface - IEEE JTAG Boundary Scan Test - Optional Schmitt-trigger input (per pin) - Unsurpassed low power management DataGATE enable (DGE) signal control - Two separate banks - ealdigital 100% CMOS product term generation - Flexible clocking modes Optional DualEDGE triggered registers Clock divider (divide by 2,4,6,8,10,12,14,16) CoolCLOCK - Global signal options with macrocell control Multiple global clocks with phase selection per macrocell Multiple global output enables Global set/reset - Advanced design security - PLA architecture Superior pinout retention 100% product term routability across function block - Open-drain output option for Wired-O and LED drive - Optional bus-hold, 3-state or weak pull-up on selected pins - Optional configurable grounds on unused s - Mixed voltages compatible with 1.5V, 1.8V, 2.5V, and 3.3V logic levels SSTL2-1, SSTL3-1, and HSTL-1 compatibility - Hot pluggable Description The Coolunner -II 256-macrocell device is designed for both high performance and low power applications. This lends power savings to high-end communication equipment and high speed to battery operated devices. Due to the low power stand-by and dynamic operation, overall system reliability is improved This device consists of sixteen Function Blocks inter-connected by a low power Advanced Interconnect Matrix (AIM). The AIM feeds 40 true and complement inputs to each Function Block. The Function Blocks consist of a 40 by 56 P-term PLA and 16 macrocells which contain numerous configuration bits that allow for combinational or registered modes of operation. Additionally, these registers can be globally reset or preset and configured as a D or T flip-flop or as a D latch. There are also multiple clock signals, both global and local product term types, configured on a per macrocell basis. Output pin configurations include slew rate limit, bus hold, pull-up, open drain and programmable grounds. A Schmitt-trigger input is available on a per input pin basis. In addition to storing macrocell output states, the macrocell registers may be configured as "direct input" registers to store signals directly from input pins. Clocking is available on a global or Function Block basis. Three global clocks are available for all Function Blocks as a synchronous clock source. Macrocell registers can be individually configured to power up to the zero or one state. A global set/reset control line is also available to asynchronously set or reset selected registers during operation. Additional local clock, synchronous clock-enable, asynchronous set/reset and output enable signals can be formed using product terms on a per-macrocell or per-function Block basis. A DualEDGE flip-flop feature is also available on a per macrocell basis. This feature allows high performance synchronous operation based on lower frequency clocking to help reduce the total power consumption of the device. Circuitry has also been included to divide one externally supplied global clock (GCK2) by eight different selections. This yields divide by even and odd clock frequencies. The use of the clock divide (division by 2) and DualEDGE flip-flop gives the resultant CoolCLOCK feature. DataGATE is a method to selectively disable inputs of the CPLD that are not of interest during certain points in time Xilinx, Inc. All rights reserved. All Xilinx trademarks, registered trademarks, patents, and disclaimers are as listed at All other trademarks and registered trademarks are the property of their respective owners. All specifications are subject to change without notice. DS094 (v3.0) May 20,

2 XC2C256 Coolunner-II CPLD By mapping a signal to the DataGATE function, lower power can be achieved due to reduction in signal switching. Another feature that eases voltage translation is banking. Two banks are available on the Coolunner-II 256 macrocell device that permit easy interfacing to 3.3V, 2.5V, 1.8V, and 1.5V devices. The Coolunner-II 256 macrocell CPLD is compatible with various standards (see Table 1). This device is also 1.5V compatible with the use of Schmitt-trigger inputs. ealdigital Design Technology Xilinx Coolunner-II CPLDs are fabricated on a 0.18 micron process technology which is derived from leading edge FPGA product development. Coolunner-II CPLDs employ ealdigital, a design technique that makes use of CMOS technology in both the fabrication and design methodology. ealdigital design technology employs a cascade of CMOS gates to implement sum of products instead of traditional sense amplifier methodology. Due to this technology, Xilinx Coolunner-II CPLDs achieve both high-performance and low power operation. Supported Standards The Coolunner-II 256 macrocell features LVCMOS, LVTTL, SSTL and HSTL implementations. See Table 1 for standard voltages. The LVTTL standard is a general purpose EIA/JEDEC standard for 3.3V applications that use an LVTTL input buffer and Push-Pull output buffer. The LVCMOS standard is used in 3.3V, 2.5V, 1.8V applications. Both HSTL and SSTL standards make use of a V EF pin for JEDEC compliance. Coolunner-II CPLDs are also 1.5V compatible with the use of Schmitt-trigger inputs Table 1: Standards for XC2C256 (1) IOSTANDAD Attribute Output V CCIO Input V CCIO Input V EF Board Termination Voltage V TT LVTTL N/A N/A LVCMOS N/A N/A LVCMOS N/A N/A LVCMOS N/A N/A LVCMOS15 (2) N/A N/A HSTL_ SSTL2_ SSTL3_ (1)For information on Vref, see XAPP399. (2) LVCMOS15 requires Schmitt-trigger inputs ICC (ma) Frequency (MHz) Figure 1: I CC vs Frequency 250 Table 2: I CC vs Frequency (LVCMOS 1.8V T A = 25 C) (1) Frequency (MHz) Typical I CC (ma) Notes: bit up/down, resettable binary counter (one counter per function block). 2 DS094 (v3.0) May 20, 2006

3 XC2C256 Coolunner-II CPLD Absolute Maximum atings Symbol Description Value Units V CC Supply voltage relative to ground 0.5 to 2.0 V V CCIO Supply voltage for output drivers 0.5 to 4.0 V V (2) JTAG JTAG input voltage limits 0.5 to 4.0 V V CCAUX JTAG input supply voltage 0.5 to 4.0 V V (1) IN Input voltage relative to ground 0.5 to 4.0 V V (1) TS Voltage applied to 3-state output 0.5 to 4.0 V T (3) STG Storage Temperature (ambient) 65 to +150 C T J Junction Temperature +150 C Notes: 1. Maximum DC undershoot below must be limited to either 0.5V or 10 ma, whichever is easiest to achieve. During transitions, the device pins may undershoot to 2.0v or overshoot to +4.5V, provided this over or undershoot lasts less than 10 ns and with the forcing current being limited to 200 ma. 2. Valid over commercial temperature range. 3. For soldering guidelines and thermal considerations, see the Device Packaging information on the Xilinx website. For Pb free packages, see XAPP427. ecommended Operating Conditions Symbol Parameter Min Max Units V CC Supply voltage for internal logic Commercial T A = 0 C to +70 C V and input buffers Industrial T A = 40 C to +85 C V V CCIO Supply voltage for output 3.3V operation V Supply voltage for output 2.5V operation V Supply voltage for output 1.8V operation V Supply voltage for output 1.5V operation V V CCAUX JTAG programming V DC Electrical Characteristics (Over ecommended Operating Conditions) Symbol Parameter Test Conditions Typical Max. Units I CCSB Standby current Commercial V CC = 1.9V, V CCIO = 3.6V μa I CCSB Standby current Industrial V CC = 1.9V, V CCIO = 3.6V μa I CC Dynamic current f = 1 MHz μa f = 50 MHz - 27 ma C JTAG JTAG input capacitance f = 1 MHz - 10 pf C CLK Global clock input capacitance f = 1 MHz - 12 pf C IO capacitance f = 1 MHz - 10 pf I (2) IL Input leakage current V IN = 0V or V CCIO to 3.9V - +/ 1 μa I (2) IH High-Z leakage V IN = 0V or V CCIO to 3.9V - +/ 1 μa Notes: bit up/down, resettable binary counter (one counter per function block) tested at V CC = V CCIO = 1.9V 2. See Quality and eliability section of the Coolunner-II family data sheet DS094 (v3.0) May 20,

4 XC2C256 Coolunner-II CPLD LVCMOS 3.3V and LVTTL 3.3V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage I OH = 8 ma, V CCIO = 3V V CCIO 0.4V - V I OH = 0.1 ma, V CCIO = 3V V CCIO 0.2V - V V OL Low level output voltage I OL = 8 ma, V CCIO = 3V V I OL = 0.1 ma, V CCIO = 3V V LVCMOS 2.5V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage V V IL Low level input voltage V V OH High level output voltage I OH = 8 ma, V CCIO = 2.3V V CCIO 0.4V - V I OH = 0.1 ma, V CCIO = 2.3V V CCIO 0.2V - V V OL Low level output voltage I OL = 8 ma, V CCIO = 2.3V V I OL = 0.1 ma, V CCIO = 2.3V V LVCMOS 1.8V DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V IH High level input voltage x V CCIO 3.9 V V IL Low level input voltage x V CCIO V V OH High level output voltage I OH = 8 ma, V CCIO = 1.7V V CCIO V I OH = 0.1 ma, V CCIO = 1.7V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.7V V I OL = 0.1 ma, V CCIO = 1.7V V LVCMOS 1.5V DC Voltage Specifications (1) Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V T+ Input hysteresis threshold voltage x V CCIO 0.8 x V CCIO V V T x V CCIO 0.5 x V CCIO V V OH High level output voltage I OH = 8 ma, V CCIO = 1.4V V CCIO V I OH = 0.1 ma, V CCIO = 1.4V V CCIO V 4 DS094 (v3.0) May 20, 2006

5 XC2C256 Coolunner-II CPLD Symbol Parameter Test Conditions Min. Max. Units V OL Low level output voltage I OL = 8 ma, V CCIO = 1.4V V I OL = 0.1 ma, V CCIO = 1.4V V Notes: 1. Hysteresis used on 1.5V inputs. Schmitt Trigger Input DC Voltage Specifications Symbol Parameter Test Conditions Min. Max. Units V CCIO Input source voltage V V T+ Input hysteresis threshold voltage x V CCIO 0.8 x V CCIO V V T x V CCIO 0.5 x V CCIO V SSTL2-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V CCIO Input source voltage V V (1) EF Input reference voltage V V (2) TT Termination voltage - V EF V EF V V IH High level input voltage - V EF V V IL Low level input voltage V EF 0.18 V V OH High level output voltage I OH = 8 ma, V CCIO = 2.3V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 2.3V V Notes: 1. V EF should track the variations in V CCIO, also peak to peak AC noise on V EF may not exceed ± 2% V EF 2. V TT of transmitting device must track V EF of receiving devices DS094 (v3.0) May 20,

6 XC2C256 Coolunner-II CPLD SSTL3-1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V CCIO Input source voltage V V (1) EF Input reference voltage V V (2) TT Termination voltage - V EF V EF V V IH High level input voltage - V EF V CCIO V V IL Low level input voltage V EF 0.2 V V OH High level output voltage I OH = 8 ma, V CCIO = 3V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 3V V Notes: 1. V EF should track the variations in V CCIO, also peak to peak AC noise on V EF may not exceed ± 2% V EF 2. V TT of transmitting device must track V EF of receiving devices HSTL1 DC Voltage Specifications Symbol Parameter Test Conditions Min. Typ Max. Units V CCIO Input source voltage V V (1) EF Input reference voltage V V (2) TT Termination voltage - - V CCIO x V V IH High level input voltage - V EF V V IL Low level input voltage V EF 0.1 V V OH High level output voltage I OH = 8 ma, V CCIO = 1.7V V CCIO V V OL Low level output voltage I OL = 8 ma, V CCIO = 1.7V V Notes: 1. V EF should track the variations in V CCIO, also peak-to-peak AC noise on V EF may not exceed ± 2% V EF 2. V TT of transmitting device must track V EF of receiving devices AC Electrical Characteristics Over ecommended Operating Conditions -6-7 Symbol Parameter Min. Max. Min. Max. Units T PD1 Propagation delay single p-term ns T PD2 Propagation delay O array ns T SUD Direct input register clock setup time ns T SU1 Setup time (single p-term) ns T SU2 Setup time (O array) ns T HD Direct input register hold time ns T H P-term hold time ns T CO Clock to output ns F (1) TOGGLE Internal toggle rate MHz F (2) SYSTEM1 Maximum system frequency MHz F (2) SYSTEM2 Maximum system frequency MHz F (3) EXT1 Maximum external frequency MHz F (3) EXT2 Maximum external frequency MHz T PSUD Direct input register p-term clock setup time ns 6 DS094 (v3.0) May 20, 2006

7 XC2C256 Coolunner-II CPLD -6-7 Symbol Parameter Min. Max. Min. Max. Units T PSU1 P-term clock setup time (single p-term) ns T PSU2 P-term clock setup time (O array) ns T PHD Direct input register p-term clock hold time ns T PH P-term clock hold ns T PCO P-term clock to output ns T OE /T OD Global OE to output enable/disable ns T POE /T POD P-term OE to output enable/disable ns T MOE /T MOD Macrocell driven OE to output enable/disable ns T PAO P-term set/reset to output valid ns T AO Global set/reset to output valid ns T SUEC egister clock enable setup time ns T HEC egister clock enable hold time ns T CW Global clock pulse width High or Low ns T PCW P-term pulse width High or Low ns T APPW Asynchronous preset/reset pulse width (High or Low) ns T DGSU Set-up before DataGATE latch assertion ns T DGH Hold to DataGATE latch assertion ns T DG DataGATE recovery to new data ns T DGW DataGATE low pulse width ns T CDSU CDST setup time before falling edge GCLK ns T CDH Hold time CDST after falling edge GCLK ns T (4) CONFIG Configuration time μs Notes: 1. F TOGGLE is the maximum clock frequency to which a T-Flip Flop can reliably toggle (see the Coolunner-II family data sheet for more information). 2. F SYSTEM1 (1/T CYCLE ) is the internal operating frequency for a device fully populated with one 16-bit counter through one p-term per macrocell while F SYSTEM2 is through the O array. 3. F EXT1 (1/T SU1 +T CO ) is the maximum external frequency using one p-term while F EXT2 is through the O array. 4. Typical configuration current during T CONFIG is approximately 7.7 ma. DS094 (v3.0) May 20,

8 XC2C256 Coolunner-II CPLD ( Internal Timing Parameters -6-7 Symbol Parameter (2) Min. Max. Min. Max. Buffer Delays T IN Input buffer delay ns T DIN Direct data register input delay ns T GCK Global Clock buffer delay ns T GS Global set/reset buffer delay ns T GTS Global 3-state buffer delay ns T OUT Output buffer delay ns T EN Output buffer enable/disable delay ns P-term Delays T CT Control term delay ns T LOGI1 Single P-term delay adder ns T LOGI2 Multiple P-term delay adder ns Macrocell Delay T PDI Input to output valid ns T SUI Setup before clock ns T HI Hold after clock ns T ECSU Enable clock setup time ns T ECHO Enable clock hold time ns T COI Clock to output valid ns T AOI Set/reset to output valid ns T CDBL Clock doubler delay ns Feedback Delays T F Feedback delay ns T OEM Macrocell to global OE delay ns Standard Time Adder Delays 1.5V CMOS T IN15 Standard input adder ns T HYS15 Hysteresis input adder ns T OUT15 Output adder ns T SLEW15 Output slew rate adder ns Standard Time Adder Delays 1.8V CMOS T HYS18 Hysteresis input adder ns T OUT18 Output adder ns T SLEW Output slew rate adder ns Units 8 DS094 (v3.0) May 20, 2006

9 XC2C256 Coolunner-II CPLD Internal Timing Parameters (Continued) -6-7 Symbol Parameter (2) Min. Max. Min. Max. Standard Time Adder Delays 2.5V CMOS T IN25 Standard input adder ns T HYS25 Hysteresis input adder ns T OUT25 Output adder ns T SLEW25 Output slew rate adder ns Standard Time Adder Delays 3.3V CMOS/TTL T IN33 Standard input adder ns T HYS33 Hysteresis input adder ns T OUT33 Output adder ns T SLEW33 Output slew rate adder ns Standard Time Adder Delays HSTL, SSTL SSTL2-1 Input adder to T IN, T DIN, T GCK, T GS,T GTS ns Output adder to T OUT ns SSTL3-1 Input adder to T IN, T DIN, T GCK, T GS,T GTS ns Output adder to T OUT ns HSTL-1 Input adder to T IN, T DIN, T GCK, T GS,T GTS ns Output adder to T OUT ns Notes: ns input pin signal rise/fall. Units Switching Characteristics AC Test Circuit 5.5 V CC = V CCIO = 1.8V, T = 25 o C V CC Device Under Test Test Point 2 C L 4.5 T PD2 (ns) Number of Outputs Switching Output Type LVTTL33 LVCMOS33 LVCMOS25 LVCMOS18 LVCMOS Ω 275Ω 188Ω 112.5Ω 150Ω 2 235Ω 275Ω 188Ω 112.5Ω 150Ω C L 35 pf 35 pf 35pF 35pF 35pF C L includes test fixtures and probe capacitance. 1.5 nsec maximum rise/fall times on inputs. Figure 3: AC Load Circuit DS ACT DS092_02_ Figure 2: Derating Curve for T PD DS094 (v3.0) May 20,

10 XC2C256 Coolunner-II CPLD V 50 IO (Output Current ma) V 2.5V Iol 1.5V VO (Output Volts) XC256_VoIo_all_ Figure 4: Typical I/V Curve for XC2C DS094 (v3.0) May 20, 2006

11 XC2C256 Coolunner-II CPLD 11 Pin Descriptions Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank B B4 2 1(GS) 3 99 A C A A B A B A A E B C5-197 C7 2 2(GTS2) 1 1 A1 2 3 D C3 2 2(GTS3) 3 2 B2 3 5 E B1 4 6 B2 2 2(GTS0) 5 3 C3 5 7 D D (GTS1) 12 4 C2 6 9 E C B D E C D1 - - E2 2 Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank A B D B A5-193 E A C6 191 D B B6-188 C A A C7-186 E B E E F F E G E G F F F G F H G1-22 H H H H5 2 DS094 (v3.0) May 20,

12 XC2C256 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank L N N2 1 5(GCK1) 4 23 L M L P1 1 5(GCK0) 6 22 K M L N L M K1-38 L M N M P2 1 (CDST) P4 1 6(GCK2) 4 27 N P T (DGE) P T M N N P M M Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank K L K L J K J K H J H K H J G J G J J N N M T P M T N P P T M6-74 N N M DS094 (v3.0) May 20, 2006

13 XC2C256 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank C B B B C A A C C B D B A E A A C C A A A B B C C C G D B D D E D C F E F E E G13 2 Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank B B D A A D C B E A F B B C C C A D F G E H F F F H F G G H G G H H J12 2 DS094 (v3.0) May 20,

14 XC2C256 Coolunner-II CPLD Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank N N T M N M N M M M P L N L L M P P P P P M N N P T P N M P N10 1 Pin Descriptions (Continued) Function Block Macrocell VQ100 CP132 TQ144 PQ208 FT256 Bank L L L M M K L K K K L J K J J H J H J P M8-88 T N N M P T M P N T N P T6 1 Notes: 1. GTS = global output enable, GS = global reset/set, GCK = global clock, CDST = clock divide reset, DGE = DataGATE enable. 2. GTS, GS and GCK pins can be used for general purpose DS094 (v3.0) May 20, 2006

15 XC2C256 Coolunner-II CPLD XC2C256 JTAG, Power/Ground, No Connect Pins and Total User Pin Type VQ100 CP132 TQ144 PQ208 FT256 TCK 48 M P12 TDI 45 M TDO 83 B A10 TMS 47 N N12 V CCAUX (JTAG supply 5 D F4 voltage) Power internal (V CC ) 26, 57 P1, K12, A2 1, 37, 84 1, 53, 124 P3, K13, D12, D5 Power Bank 1 (V CCIO1 ) 20, 38, 51 J3, P7, G14, P13 27, 55, 73, 93 33, 59, 79, 92, 105, 132 Power Bank 2 (V CCIO2 ) 88, 98 A14, C4, A7 109, 127, , 133, 157, 172, 181, 204 Ground 21, 25, 31, 62, 69, 75, 84, 100 K2, N1, P4, N9, N12, J14, H14, E14, B14, A9, B3 29, 36, 47, 62, 72, 89, 90, 99, 108, 123, , 24, 42, 52, 68, 81, 93, 104, 129, 130, 141, 156, 177, 190, 207 J6, K6, L7, L8, J11, K11, L10, L9 F7, F8, G6, H6, F10, F9, H11 F11, F6, G10, G7, G8, G9, H10, H7, H8, H9, J10, J7, J8, J9, K10, K7, K8, K9, L11, L6 No connects A1, C2, E6, D1, E1, G2, F1, G1, M4, T9, P9, M9, M10, T11, T12, T13, P11, T14, J16, K12, D16, G12, C15, D14, D6, C6, E7, C5 Total user DS094 (v3.0) May 20,

16 XC2C256 Coolunner-II CPLD Ordering Information Part Number Pin/Ball Spacing θ JA (C/Watt) θ JC (C/Watt) Package Type Package Body Dimensions Commercia l (C) Industrial (I) (1) XC2C256-6VQ100C 0.5mm Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-7VQ100C 0.5mm Very Thin Quad Flat 14mm x 14mm 80 C Pack XC2C256-6CP132C 0.5mm Chip Scale Package 8mm x 8mm 106 C XC2C256-7CP132C 0.5mm Chip Scale Package 8mm x 8mm 106 C XC2C256-6TQ144C 0.5mm Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-7TQ144C 0.5mm Thin Quad Flat Pack 20mm x 20mm 118 C XC2C256-6PQ208C 0.5mm Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-7PQ208C 0.5mm Plastic Quad Flat 28mm x 28mm 173 C Pack XC2C256-6FT256C 1.0mm Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-7FT256C 1.0mm Fine Pitch Thin BGA 17mm x 17mm 184 C XC2C256-6VQG100C 0.5mm Very Thin Quad Flat Pack; Pb-free XC2C256-7VQG100C 0.5mm Very Thin Quad Flat Pack; Pb-free XC2C256-6CPG132C 0.5mm Chip Scale Package; Pb-free XC2C256-7CPG132C 0.5mm Chip Scale Package; Pb-free XC2C256-6TQG144C 0.5mm Thin Quad Flat Pack; Pb-free XC2C256-7TQG144C 0.5mm Thin Quad Flat Pack; Pb-free XC2C256-6PQG208C 0.5mm Plastic Quad Flat Pack; Pb-free XC2C256-7PQG208C 0.5mm Plastic Quad Flat Pack; Pb-free XC2C256-6FTG256C 1.0mm Fine Pitch Thin BGA; Pb-free XC2C256-7FTG256C 1.0mm Fine Pitch Thin BGA; Pb-free 14mm x 14mm 80 C 14mm x 14mm 80 C 8mm x 8mm 106 C 8mm x 8mm 106 C 20mm x 20mm 118 C 20mm x 20mm 118 C 28mm x 28mm 173 C 28mm x 28mm 173 C 17mm x 17mm 184 C 17mm x 17mm 184 C XC2C256-7VQ100I 0.5mm Very Thin Quad Flat 14mm x 14mm 80 I Pack XC2C256-7CP132I 0.5mm Chip Scale Package 8mm x 8mm 106 I XC2C256-7TQ144I 0.5mm Thin Quad Flat Pack 20mm x 20mm 118 I XC2C256-7PQ208I 0.5mm Plastic Quad Flat 28mm x 28mm 173 I Pack XC2C256-7FT256I 1.0mm Fine Pitch Thin BGA 17mm x 17mm 184 I 16 DS094 (v3.0) May 20, 2006

17 XC2C256 Coolunner-II CPLD Part Number Pin/Ball Spacing θ JA (C/Watt) θ JC (C/Watt) Package Type XC2C256-7VQG100I 0.5mm Very Thin Quad Flat Pack; Pb-free XC2C256-7CPG132I 0.5mm Chip Scale Package; Pb-free XC2C256-7TQG144I 0.5mm Thin Quad Flat Pack; Pb-free XC2C256-7PQG208I 0.5mm Plastic Quad Flat Pack; Pb-free XC2C256-7FTG256I 1.0mm Fine Pitch Thin BGA; Pb-free Notes: 1. C = Commercial (T A = 0 C to +70 C); I = Industrial (T A = 40 C to +85 C). Package Body Dimensions Commercia l (C) Industrial (I) (1) 14mm x 14mm 80 I 8mm x 8mm 106 I 20mm x 20mm 118 I 28mm x 28mm 173 I 17mm x 17mm 184 I Standard Example: XC2C128 Device Speed Grade Package Type Number of Pins Temperature ange -6 TQ 144 C Pb-Free Example: XC2C128-6 TQ G 144 C Device Speed Grade Package Type Pb-Free Number of Pins Temperature ange Device Part Marking Device Type Package Speed Operating ange XC2Cxxx TQ144 7C This line not related to device part number Part marking for non-chip scale package Figure 5: Sample Package with Part Marking Note: Due to the small size of chip scale packages, the complete ordering part number cannot be included on the package marking. Part marking on chip scale packages by line are: Line 1 = X (Xilinx logo) then truncated part number Line 2 = Not related to device part number Line 3 = Not related to device part number 1. Line 4 = Package code, speed, operating temperature, three digits not related to device part number. Package codes: C5 = CP132, C6 = CPG132. DS094 (v3.0) May 20,

18 XC2C256 Coolunner-II CPLD (3) VCCIO2 VCCIO2 TDO (1) (1) (1) (1) VAUX (2) (2) (4) VQ100 Top View VCC VCC (2) (5) TDI TMS TCK (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - Data Gate Figure 6: VQ100 Very Thin Quad Flat Pack 18 DS094 (v3.0) May 20, 2006

19 XC2C256 Coolunner-II CPLD P N M VCC (5) (2) TMS (4) TDI TCK L (2) K (2) VCC J H G CP132 Bottom View F E D VAUX C B A (1) (1) VCCIO2 (1) TDO (1) VCC (3) VCCIO2 VCCIO2 (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable Figure 7: CP132 Chip Scale Package DS094 (v3.0) May 20,

20 XC2C256 Coolunner-II CPLD VCC (1) (1) (1) (1) VAUX (2) (2) (4) TQ144 Top View VCC (2) (5) TDI TMS TCK (3) VCCIO2 VCCIO2 TDO VCCIO2 VCC Figure 8: TQ144 Thin Quad Flat Pack (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable 20 DS094 (v3.0) May 20, 2006

21 XC2C256 Coolunner-II CPLD DS094 (v3.0) May 20, Figure 9: PQ208 Quad Flat Package VCC (1) (1) (1) (1) VAUX VCCIO2 (2) (2) (4) PQ208 Top View VCC (2) (5) TDI TMS TCK (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable VCCIO2 VCC (3) VCCIO2 VCCIO2 TDO VCCIO2 VCCIO

22 XC2C256 Coolunner-II CPLD A B C D E F G H J K L M N P T TDO NC NC NC NC (3) NC NC NC VCC NC VCC (1) (1) NC NC NC (1) (1) NC VCCIO2 VCCIO2 VCCIO2 VCCIO2 VAUX NC NC VCCIO2 NC NC VCCIO2 VCCIO2 NC VCC NC NC NC NC (2) (2) TMS TCK NC NC (2) VCC (4) TDI NC NC NC NC NC (5) FT256 Bottom View Figure 10: FT256 Fine Pitch Thin BGA (1) - Global Output Enable (2) - Global Clock (3) - Global Set/eset (4) - Clock Divide eset (5) - DataGATE Enable Warranty Disclaimer THESE PODUCTS AE SUBJECT TO THE TEMS OF THE XILINX LIMITED WAANTY WHICH CAN BE VIEWED AT THIS LIMITED WAANTY DOES NOT EXTEND TO ANY USE OF THE PODUCTS IN AN APPLICATION O ENVIONMENT THAT IS NOT WITHIN THE SPECIFICATIONS STATED ON THE THEN-CUENT XILINX DATA SHEET FO THE PODUCTS. PODUCTS AE NOT DESIGNED TO BE FAIL-SAFE AND AE NOT WAANTED FO USE IN APPLICATIONS THAT POSE A ISK OF PHYSICAL HAM O LOSS OF LIFE. USE OF PODUCTS IN SUCH APPLICATIONS IS FULLY AT THE ISK OF CUSTOME SUBJECT TO APPLICABLE LAWS AND EGULATIONS DS094 (v3.0) May 20, 2006

23 XC2C256 Coolunner-II CPLD Additional Information Additional information is available for the following Coolunner-II topics: XAPP784: Bulletproof CPLD Design Practices XAPP375: Timing Model XAPP376: Logic Engine XAPP378: Advanced Features XAPP382: Characteristics XAPP389: Powering Coolunner-II XAPP399: Assigning VEF Pins evision History The following table shows the revision history for this document. To access these and all application notes with their associated reference designs, click the following link and scroll down the page until you find the document you want: Coolunner-II Data Sheets and Application Notes Device Packages Date Version evision 05/09/ Initial Xilinx release. 05/13/ Updated AC Electrical Characteristics and added new parameters. 10/31/ Corrected package user, added Voltage eferenced DC tables. 03/17/ Added Characterization numbers for product release and device part marking 04/02/ Updated T SOL max from 260 to 220. Changed I CCSB units from ma to μa. 01/26/ Updated Device Part Marking. Updated links and Tsol. 02/26/ Corrected Theta JC value on XC2C256-7TQ /03/ Pb-free documentation 08/19/ Changes to I CCSB maximum specifications in DC Electrical Characteristics table, on page 3. 10/01/ Add Asynchronous Preset/eset Pulse Width specification to AC Electrical Characteristics. 03/07/ emoved -5 speed grade. Changes to Table 1, Standards. 06/28/ Move to. Change to T IN25, T OUT25, T IN33, and T OUT33 for -7 speed grade. 03/20/ Add Warranty Disclaimer. Add note to Pin Description table that GTS, GS and GCK pins can be used for general purpose. 5/20/ Moved T CONFIG specification values from MIN column to MAX column, page 7. DS094 (v3.0) May 20,