ICSSSTUB32S868D Advance Information

Transcription

1 Integrated Circuit Systems, Inc. ICSSSTUB3S868 8-Bit Configurable egistered Buffer for ecommended Application: Memory Modules Provides complete IMM solution with ICS97U877 Ideal for 400, 533 and 667 Product Features: 8-bit 1: registered buffer with parity check functionality Supports SSTL_18 JEEC specification on data inputs and outputs Supports LVCMOS switching levels on CSGEN and ESET# inputs Low voltage operation V = 1.7V to 1.9V Available in 176 BGA package Green packages available A B C E F G H J K L M N P T U V W Y AA AB Pin Configuration Functionality Truth Table Inputs Outputs 176 Ball BGA (Top View) ST# CS0# CS1# CSGEN # n, OTn, En n CS0# CS1# OT, E H L L X L L L L L H L L X H H L L H H L L X L or H L or H X H L H X L L L H L H L H X H H L H H H L H X L or H L or H X H H L X L L H L L H H L X H H H L H H H L X L or H L or H X H H H L L L H H L H H H L H H H H H H H H L L or H L or H X H H H H L 0 H H L H H H H H 0 H H H H H H H L or H L or H X L X or X or X or X or X or X or floating floating floating floating floating floating L L L L AVANCE INFOMATION documents contain information on products in the formative or design phase development. Characteristic data and other specifications are design goals. ICS reserves the right to change or discontinue these products without notice. Third party brands and names are the property of their respective owners.

2 ICSSSTUB3S868 Ball Assignments A 1 C GN V EF GN 1A 1B B 4 3 V V V V A B C 6 (E1) 8 (E0) E 9 6A (E1A) F 10 8A E0A 5 GN GN GN GN 3A 3B 7 V V V V 4A 4B GN GN GN GN 5A 5B V V V V 7A 6B (E1B) G 11 10A GN GN GN GN 9A 7B H 1 1A V V V V 11A 8B (E0B) J CS1# CS1A# GN GN GN GN 10B 9B K CS0# CS0A# V V V V 1B 11B L CSGEN PA_IN GN GN GN 14B (CS0B#) M 3 ESET# E# V V V 15B (OT0B) N P 15 (OT0) 16 (OT1) 15A (OT0A) 16A (0T1A) 1: egister A (C=0) Note: NC denotes a no-connect (ball present but not connected to the die). 13B (CS1B#) 16B (OT1B) GN GN GN GN 17B 18B V V V V 19B 0B 17 17A GN GN GN GN 18A 1B T 18 19A V V V V 0A B U 19 1A GN GN GN GN A 3B V 0 3A V V V V 4A 4B W 1 GN GN GN GN 5A 5B Y 3 4 V V V V 6A 6B AA 5 6 GN GN GN GN 7A 7B AB 7 8 NC V V EF V 8A 8B

3 ICSSSTUB3S868 Ball Assignments A 1 C GN V EF GN 1A 1B B 4 3 V V V V A B C 6 5 GN GN GN GN 3A 3B 8 7 V V V V 4A 4B E 9 6A GN GN GN GN 5A 5B F 10 8A V V V V 7A 6B G 11 10A GN GN GN GN 9A 7B H 1 1A V V V V 11A 8B J K 13 (OT1) 14 (OT0) 13A (OT1A) 14A (OT0A) GN GN GN GN 10B 9B V V V V 1B 11B L CSGEN PA_IN GN GN GN 14B (OT0B) M # ESET# E# V V V 15B (CS0B#) N 15 (CS0#) 15A (CS0#) P 16 16A (CS1#) (CS1A#) 1: egister B (C=1) Note: NC denotes a no-connect (ball present but not connected to the die). 13B (OT1B) 16B (CS1B#) GN GN GN GN 17B 18B V V V V 19B 0B 17 17A GN GN GN GN 18A 1B (E0B) T V V V V 0A B U 19 1A (E0A) V 0 3A (E1A) W Y 1 (E0) 3 (E1) GN GN GN GN A 3B (E1B) V V V V 4A 4B GN GN GN GN 5A 5B 4 V V V V 6A 6B AA 5 6 GN GN GN GN 7A 7B AB 7 8 NC V V EF V 8A 8B

4 ICSSSTUB3S868 General escription This 8-bit 1: configurable registered buffer is designed for 1.7-V to 1.9-V V operation. All inputs are compatible with the JEEC standard for SSTL_18, except the chip-select gate-enable (CSGEN), control (C), and reset (ESET) inputs, which are LVCMOS. All outputs are edge-controlled circuits optimized for unterminated IMM loads, and meet SSTL_18 specifications, except the open-drain error (E) output. The ICSSSTUB3S868 operates from a differential clock ( and ). ata are registered at the crossing of going high and going low. The device supports low-power standby operation. When ESET is low, the differential input receivers are disabled, and undriven (floating) data, clock, and reference voltage (VEF) inputs are allowed. In addition, when ESET is low, all registers are reset and all outputs are forced low except E. The LVCMOS ESET and C inputs always must be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, ESET must be held in the low state during power up. In the IMM application, ESET is specified to be completely asynchronous with respect to and. Therefore, no timing relationship can be ensured between the two. When entering reset, the register will be cleared and the data outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of ESET until the input receivers are fully enabled, the design of the ICSSSTUB3S868 must ensure that the outputs will remain low, thus ensuring no glitches on the output. Inputs ST# CS0# CS1# # Σ of inputs = H (1-8) Output PA_I N E# H L X Even L H H L X Odd L L H L X Even H L H L X Odd H H H X L Even L H H X L Odd L L H X L Even H L H X L Odd H H H H H X X E# 0 H X X L or H L or H X X E# 0 L X or floating X or floating X or floating X or floating PA_IN arrives one clock cycle after the data to which it applies. This transition assumes E# is high at the crossing of going high and # going low. If E# is low, it stays latches low for two clock cycles or until ST# is driven low. If CS0#, CS1#, and CSGEN are driven high, the device is placed in low-power mode (LPM). If a parity error occurs on the clock cycle before the device enters the LPM and the E# output is driven low, it stays latches low for the LPM duration plus two clock cycles or until ST# is driven low. X X or floating H 4

5 ICSSSTUB3S868 General escription (Continued) The ICSSSTUB3S868 includes a parity checking function. Parity, which arrives one cycle after the data input to which it applies, is checked on the PA_IN input of the device. The corresponding E output signal for the data inputs is generated two clock cycles after the data, to which the E signal applies, is registered. The ICSSSTUB3S868 accepts a parity bit from the memory controller on the parity bit (PA_IN) input, compares it with the data received on the IMM-independent -inputs (1-5, 7, 9-1, 17-8 when C = 0; or 1-1, 17-0,, 4-8 when C = 1) and indicates whether a parity error has occurred on the open-drain E pin (active low). The convention is even parity, i.e., valid parity is defined as an even number of ones across the IMM-independent data inputs combined with the parity input bit. To calculate parity, all IMM-independent -inputs must be tied to a known logic state. If an error occurs and the E output is driven low, it stays latched low for a minimum of two clock cycles or until ESET is driven low. If two or more consecutive parity errors occur, the E output is driven low and latched low for a clock duration equal to the parity error duration or until ESET is driven low. If a parity error occurs on the clock cycle before the device enters the low-power (LPM) and the E output is driven low, then it stays lateched low for the LPM duration plus two clock cycles or until ESET is driven low. The IMM-dependent signals (E0, E1, OT0, OT1, CS0 and CS1) are not included in the parity check computation. The C input controls the pinout configuration from register-a configuration (when low) to register-b configuration (when high). The C input should not be switched during normal operation. It should be hardwired to a valid low or high level to configure the register in the desired mode. The device also supports low-power active operation by monitoring both system chip select (CS0 and CS1) and CSGEN inputs and will gate the n outputs from changing states when CSGEN, CS0, and CS1 inputs are high. If CSGEN, CS0 or CS1 input is low, the n outputs will function normally. Also, if both CS0 and CS1 inputs are high, the device will gate the E output from changing states. If either CS0 or CS1 is low, the E output will function normally. The ESET input has priority over the CS0 and CS1 control and when driven low will force the n outputs low, and the E output high. If the chip-select control functionality is not desired, then the CSGEN input can be hard-wired to ground, in which case, the setup-time requirement for CS0 and CS1 would be the same as for the other data inputs. To control the low-power mode with CS0 and CS1 only, then the CSGEN input should be pulled up to V through a pullup resistor. The two VEF pins (A1 and V1) are connected together internally by approximately However, it is necessary to connect only one of the two VEF pins to the external VEF power supply. An unused VEF pin should be terminated with a VEF coupling capacitor. 5

6 ICSSSTUB3S868 Ball Assignment Terminal name escription Electrical characteristics GN Ground Ground input V Power supply voltage 1.8-V nominal V EF Input reference voltage 0.9-V nominal Positive master clock input ifferential input # Negative master clock input ifferential input C Configuration control inputs - egister A or egister B LVCMOS inputs ST# Asynchronous reset input resets registers and disables VEF data LVCMOS input and clock differential-input receivers CSGEN Chip select gate enable When high, 1-8 inputs will be latched only when at least one chip select input is low during the rising edge of the clock. When low, the1-8 inputs will be latched and redriven on every rising edge of the clock. LVCMOS input 1-8 CS0#, CS1# OT0, OT1 E0, E1 PA_IN ata input clocked in on the crossing of the rising edge of and the falling edge of #. Chip select inputs These pins initiate AM address/command decodes, and as such at least one will be low when a valid address/command is present. The egister can be programmed to redrive all inputs (CSGEN high) only when atleast one chip select input is low. If CSGEN, CS0#, and CS1# inputs are high, 1 8 inputs will be disabled. The outputs of this register bit will not be suspended by the C0# and CS1# control. The outputs of this register bit will not be suspended by the C0# and CS1# control. Parity input - arrives one clock cycle after the corresponding data input. ata inputs = 1-5, 7, 9-1, 17-8 when C=0 ata inputs = 1-1, 17-0,, 4-8 when C=1 SSTL_18 input SSTL_18 input SSTL_18 input SSTL_18 input SSTL_18 input 1-8 ata outputs that are suspended by the C0# and CS1# control. 1.8-V CMOS outputs CS0#, CS1# ata output that will not be suspended by the C0# and CS1# control. OT0, OT1 E0, E1 E# NC ata output that will not be suspended by the C0# and CS1# control. ata output that will not be suspended by the C0# and CS1# control. 1.8-V CMOS output 1.8-V CMOS output 1.8-V CMOS output Output error bit - generated one clock cycle after the corresponding data output Open-drain output No internal connection ata outputs = 1-5, 7, 9-1, 17-8 when C=0 ata outputs = 1-1, 17-0,, 4-8 when C=1 6

7 ICSSSTUB3S868 Block iagram ST# M # L1 M1 V EF A5, AB5 E0, E1 1, C1 F, E E0A, E1A H8, F8 E0B, E1B OT0, OT1 N1, P1 N, P OT0A, OT1A M7, M8 OT0B, OT1B K1 CS0# K CS0A# L7 CS0B# CSGEN L J1 CS1# J CS1A# L8 CS1B# One of Channels 1 A CE A7 1A A8 1B To 1 Other Channels (-5, 7, 9-1, 17-8) egister A configuration with C= O; (positive logic) 7

8 ICSSSTUB3S868 Parity Logic iagram ST# # M L1 M1 1-5, 7, 9-1, 17-8 V EF A5, AB5 1-5, 7, 9-1, 17-8 CE 1-5, 7, 9-1, , 7, 9-1, A-5A, 7A, 9A-1A, 17A-8A 1B-5B, 7B, 9B-1B, 17B-8B PA_IN L3 CE Parity Generator and Error Check M3 E# CS0# K1 K CS0A# L7 CS0B# CSGEN L CS1# J1 J CS1A# L8 CS1B# egister A configuration with C= O; (positive logic) 8

9 ICSSSTUB3S868 Block iagram ST# M # L1 M1 V EF A5, AB5 E0, E1 W1, Y1 U, V E0A, E1A 8, U8 E0B, E1B OT0, OT1 K1, J1 K, J OT0A, OT1A L7, L8 OT0B, OT1B N1 CS0# N CS0A# M7 CS0B# CSGEN L P1 CS1# P CS1A# M8 CS1B# One of Channels 1 A CE A7 1A A8 1B To 1 Other Channels (-1, 17-0,, 4-8) egister B configuration with C= 1; (positive logic) 9

10 ICSSSTUB3S868 Parity Logic iagram ST# # M L1 M1 1-1, 17-0,, 4-8 V EF A5, AB5 1-1, 17-0,, 4-8 CE 1-1, 17-0,, , 17-0,, 4-8 1A-1A, 17A-0A, A, 4A-8A 1B-1B, 17B-0B, B, 4B-8B PA_IN L3 CE Parity Generator and Error Check M3 E# CS0# N1 N CS0A# M7 CS0B# CSGEN L CS1# P1 P CS1A# M8 CS1B# egister B configuration with C= 1; (positive logic) 10

11 ICSSSTUB3S868 egister Timing ST# CSGEN CS0# CS1# n n + 1 n + n + 3 n + 4 # t act t su t h n, OTn, En t pdm,t pdmss to n, OTn, En t su t h PA_IN t PHL to E# t PHL, t PLH to E# E# ata to E# Latency H, L, or X H or L After ESET# is switched from low to high, all data and PA_IN input signals must be set and held low for a minimum time of tact max, to avoid false error. If the data is clocked in on the n clock pulse, the E# output sognal will be produced on the n+ clock pulse and it will be valid on the n+3 clock pulse. 11

12 ICSSSTUB3S868 egister Timing ST# CSGEN CS0# CS1# n n + 1 n + n + 3 n + 4 # t su t h n, OTn, En t pdm,t pdmss to n, OTn, En t su t h PA_IN t PHL or t PLH to E# E# ata to E# Latency Unknown input event Output signal is dependent on the prior unknown input event H or L If the data is clocked in on the n clock pulse, the E# output signal will be generated on the n + clock pulse and it will be valid on the n + 3 clock pulse. If an error occurs and the E# output is driven low, it stays low for a minimum of two clock cycles or until ST# is driven low. 1

13 ICSSSTUB3S868 egister Timing ST# t inact CSGEN CS0# CS1# # n, OTn, En n, OTn, En t PHL ST # to PA_IN E# t PLH ST# to E# H, L, or X H or L AfterST# is switched from high to low, all data and clock input signals must be held at valid logic levels (not floating) for a minimum time of t inact max. 13

14 ICSSSTUB3S868 Absolute Maximum atings Storage Temperature C to +150 C Supply Voltage to.5v Input Voltage to V +.5V Output Voltage 1, to V Input Clamp Current ±50 ma Output Clamp Current ±50mA Continuous Output Current ±50mA V or GN Current/Pin ±100mA Package Thermal Impedance C Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed.. This current will flow only when the output is in the high state level V 0 >V. 3. The package thermal impedance is calculated in accordance with JES 51. Stresses above those listed under Absolute Maximum atings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. ecommended Operating Conditions PAAMETE ESCIPTION MIN TYP MAX UNITS V I/O Supply Voltage V EF eference Voltage 0.49 x V 0.5 x V 0.51 x V V TT Termination Voltage V EF V EF V EF V I Input Voltage 0 V V IH (C) C Input High Voltage V EF V IH (AC) AC Input High Voltage V EF ata CS#, and PA_IN inputs V IL (C) C Input Low Voltage V EF V IL (C) AC Input Low Voltage V EF V V IH Input High Voltage Level 0.65 x V ESET#, C0, C1 V IL Input Low Voltage Level 0.35 x V V IC Common mode Input ange CLK, CLK# V I ifferential Input Voltage I OH High-Level Output Current -16 I OL Low-Level Output Current 16 ma T A Operating Free-Air Temperature 0 70 C 1 Guaranteed by design, not 100% tested in production. Note: eset# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless eset# is low. 14

15 ICSSSTUB3S868 Electrical Characteristics - C T A = 0-70 C; V =.5 +/-0.V, V =.5 +/-0.V; (unless otherwise stated) SYMBOL PAAMETES CONITIONS V MIN TYP MAX UNITS V OH V OL Output HIGH voltage I OH = -16mA 1.7V 1. Output LOW voltage 0. I OL = 16mA 1.7V 0.5 I I All Inputs V I = V or GN 1.9V ±5 µa Standby (Static) ESET# = GN 00 µa I V I = V IH(AC) or V IL(AC), I O = 0 1.9V Operating (Static) ESET# = V 80 ma ESET# = V, I ynamic operating V I = V IH(AC) or V IL(AC), µ/clock I O = 0 1.8V 175 (clock only) CLK and CLK# switching MHz 50% duty cycle. ESET# = V, I ynamic Operating (per each data input) 1: mode V I = V IH(AC) or V IL (AC), CLK and CLK# switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle I O = 0 1.8V 00 µa/ clock MHz/data Input capacitance, n, CSGEN, PA_IN V I = V EF ± 50 mv.5 4 pf inputs Input capacitance, V I = V EF ± 50 mv Single-die C i CS# n 1.8V.5 4 pf Input capacitance, V IC = 0.9V; V I(PP) = 600 and # inputs mv Single-die 3 pf Input capacitance, ESET# input V I = V or GN Note 3 Note 3 pf Notes: 1 - Guaranteed by design, not 100% tested in production. - The vendor must choose to comply with either single-die or dual-die specification in accordance to the device implementatio 3 - The vendor must supply this value for full device description. V Output Buffer Characteristics Output edge rates over recommended operating free-air temperature range (See figure 7) PAAMETE V = 1.8V ± 0.1V MIN MAX UNIT dv/dt_r 1 4 V/ns dv/dt_f 1 4 V/ns dv/dt_ 1-1 V/ns 1. ifference between dv/dt_r (rising edge rate) and dv/dt_f (falling edge rate) 15

16 ICSSSTUB3S868 Timing equirements (over recommended operating free-air temperature range, unless otherwise noted) Symbol Parameter Min Max Unit f clock Clock frequency MHz t W Pulse duration,, # HIGH or LOW 1 - ns t ACT ifferential inputs active time (See Notes 1 and ) - 10 ns t INACT ifferential inputs inactive time (See Notes 1 and 3) - 15 ns Setup time CS before, #, CS# high; CS# before, #, CS# high ns Setup time CS# before, #, CS# low ns t SU Setup time OT, E and data before, # ns Setup time PA_IN before, # ns Hold time CS#, OT, E and data after, # ns t H Hold time PA_IN after, # ns NOTE 1 NOTE NOTE 3 This parameter is not necessarily production tested. V EF must be held at a valid input voltage level and data inputs must be held low for a minimum time of t ACT (max) after ESET# is taken high. V EF, ata and clock inputs must be held at valid voltage levels (not floating) a minimum time of t INACT (max) after ESET# is taken low. Switching Characteristics (over recommended operating free-air temperature range, unless otherwise noted) Symbol Parameter Measurement Conditions MIN MAX Units fmax Max input clock frequency 410 MHz t PM Propagation delay, single bit switching to # n ns t LH Low to High propagation delay to # to E# 1. 3 ns t HL High to low propagation delay to # to E# 1.4 ns t PMSS Propagation delay simultaneous switching to # n ns t PHL High to low propagation delay eset# to n 3 ns t PLH Low to High propagation delay eset# to E# 3 ns 1. Guaranteed by design, not 100% tested in production. 16

17 ICSSSTUB3S868 Inputs TL=50Ω Test Point UT # Out TL=350ps, 50Ω C L = 30 pf (see Note 1) V L = 1000Ω Test Point L = 1000Ω L = 100Ω Test Point LOA CICUIT VCMOS ST# Inp ut V / V / V 0 V # V I t inact t act V IC V IC I (see Note ) 10% VOLTAGE AN CUENT WAVEFOMS INPUTS ACTIVE AN INACTIVE TIMES t w 90% V I t PLH t PHL V OH Output V TT V TT V OL VOLTAGE WAVEFOMS POPAGATION ELAY TIMES Inpu t V IC V IC VOLTAGE WAVEFOMS PULSE UATION V I # V IC LVCMOS ST# Input V / t PHL V IH V IL t su t h V OH Output V TT Inpu t V EF V EF V IH V IL V OL VOLTAGE WAVEFOMS POPAGATION ELAY TIMES VOLTAGE WAVEFOMS SETUP AN HOL TIMES Figure 6 Parameter M easurement Infor mation (V = 1.8 V ± 0.1 V) Notes: 1. C L incluces probe and jig capacitance.. I tested with clock and data inputs held at V or GN, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: P 10 MHz, Zo=50Ω, input slew rate = 1 V/ns ±0% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. V EF = V / 6. V IH = V EF + 50 mv (ac voltage levels) for differential inputs. V IH = V for LVCMOS input. 7. V IL = V EF - 50 mv (ac voltage levels) for differential inputs. V IL = GN for LVCMOS input. 8. V I = 600 mv 9. t PLH and t PHL are the same as t PM. 17

18 ICSSSTUB3S868 Output slew rate measurement information (V =1.8V±0.1V) All input pulses are supplied by generators having the following characteristics: P 10 MHz; Z o =50 ; input slew rate = 1 V/ns ± 0%, unless otherwise specified. V UT L = 50 OUT TEST POINT C L = 10 pf SEE NOTE (1) 00aaa377 (1) C L includes probe and jig capacitance. Figure 1 Load circuit, HIGH-to-LOW slew measurement OUTPUT V OH dv_f 80% 0% dt_f V OL 00aaa378 Figure 13 Voltage waveforms, HIGH-to-LOW slew rate measurement UT OUT TEST POINT C L = 10 pf SEE NOTE (1) L = 50 00aaa379 (1) C L includes probe and jig capacitance. Figure 14 Load circuit, LOW-to-HIGH slew measurement dt_r V OH 80% dv_r 0% OUTPUT V OL 00aaa380 Figure 15 Voltage waveforms, LOW-to-HIGH slew rate measurement 18

19 ICSSSTUB3S868 Error output load circuit and voltage measurement information (V =1.8V±0.1V) All input pulses are supplied by generators having the following characteristics: P 10 MHz; Z o =50 ; input slew rate = 1 V/ns ± 0%, unless otherwise specified. V UT L = 1 k OUT TEST POINT C L = 10 pf SEE NOTE (1) 00aaa500 (1) C L includes probe and jig capacitance. Figure 16 Load circuit, error output measurements LVCMOS ST# Input V CC / V CC 0 V t PLH V OH Output Waveform 0.15 V 00aaa501 0 V Figure 17 Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to ST# input Timing Inputs V IC VIC V I(PP) t HL V CC Output Waveform 1 V CC / V OL Figure 18 Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs 00aaa50 Timing Inputs V IC VIC V I(PP) t LH V OH Output Waveform 0.15 V 00aaa503 0 V Figure 19 Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs 19

20 ICSSSTUB3S868 A1 Seating Plane C T b EF Numeric esignations for Horizontal Grid A B C Alpha esignations for Vertical Grid (Letters I, O, & S not used) d TYP 1 TOP VIEW - e - TYP E h TYP 0.1 C c EF E1 - e - TYP ALL IMENSIONS IN MILLIMETES BALL GI EF. IMS E T e HOIZ VET TOTAL d h 1 E1 b c Min/Max Min/Max Min/Max Bsc 6.00 Bsc 1.00/ Bsc / / Bsc 4.55 Bsc *** Note: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source ef.: JEEC Publication 95, MO-05*, MO-5**, MO-46*** Ordering Information Example: T ICSSSTUB3S868H(LF)- ICS XXXX y H (LF)- T esignation for tape and reel packaging Lead Free, ohs Compliant (Optional) Package Type H = BGA evision esignator (will not correlate with datasheet revision) evice Type Prefix ICS = Standard evice 0