SSTUB General description. 2. Features and benefits. 3. Applications

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1 1.8 V 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2-800 RDIMM applications Rev April 2010 Product data sheet 1. General description The is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM. The accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The is packaged in a 96-ball, 6 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm 5.5 mm). 2. Features and benefits 3. Applications Configurable register supporting DDR2 up to 800 MT/s Registered DIMM applications Configurable to 25-bit 1 : 1 mode or 14-bit 1 : 2 mode Controlled output impedance drivers enable optimal signal integrity and speed Meets or exceeds JEDEC standard speed performance Supports up to 450 MHz clock frequency of operation Optimized pinout for high-density DDR2 module design Chip-selects minimize power consumption by gating data outputs from changing state Supports SSTL_18 data inputs Checks parity on the DIMM-independent data inputs Partial parity output and input allows cascading of two s for correct parity error processing Differential clock ( and ) inputs Supports LVCMOS switching levels on the control and RESET inputs Single 1.8 V supply operation (1.7 V to 2.0 V) Available in 96-ball, 13.5 mm 5.5 mm, 0.8 mm ball pitch LFBGA package 400 MT/s to 800 MT/s DDR2 registered DIMMs desiring parity checking functionality

2 4. Ordering information Table 1. Ordering information Type number Solder process Package EC/G EC/S Pb-free (SnAgCu solder ball compound) Pb-free (SnAgCu solder ball compound) 4.1 Ordering options Table 2. Name Description Version LFBGA96 LFBGA96 Ordering options Type number Temperature range EC/G T amb = 0 C to +70 C EC/S T amb = 0 C to +85 C plastic low profile fine-pitch ball grid array package; 96 balls; body mm plastic low profile fine-pitch ball grid array package; 96 balls; body mm SOT536-1 SOT536-1 _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

3 5. Functional diagram RESET VREF DE 1D C1 R QEA QEB (1) DODT 1D C1 R QODTA QODTB (1) DCS 1D C1 R QCSA QCSB (1) CSR D D C1 R Q2A Q2B (1) to 10 other channels (D3, D5, D6, D8 to D14) 002aac010 (1) Disabled in 1 : 1 configuration. Fig 1. Functional diagram of ; 1 : 2 Register A configuration with C0 = 0 and C1 = 1 (positive logic) _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

4 RESET D2, D3, D5, D6, D8 to D14 VREF 11 LPS0 (internal node) CE D CLK R D2, D3, D5, D6, D8 to D D2, D3, D5, D6, D8 to D Q2A, Q3A, Q5A, Q6A, Q8A to Q14A Q2B, Q3B, Q5B, Q6B, Q8B to Q14B PARITY CHE C1 D CLK R 0 1 D CLK R CE D CLK R 1 0 PPO PAR_IN QERR C0 CLK 2-BIT COUNTER R LPS1 (internal node) D CLK R aaa650 Fig 2. Parity logic diagram for 1 : 2 Register A configuration (positive logic); C0 = 0, C1 = 1 _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

5 6. Pinning information 6.1 Pinning ball A1 index area A B C D E F G H J K L M N P R T EC/G EC/S aac011 Transparent top view Fig 3. Pin configuration for LFBGA A B C D E F G H J K L M N P R T DE PPO VREF V DD QE DNU D2 D15 GND GND Q2 Q15 D3 D16 V DD V DD Q3 Q16 DODT QERR GND GND QODT DNU D5 D17 V DD V DD Q5 Q17 D6 D18 GND GND Q6 Q18 PAR_IN RESET V DD V DD C1 C0 DCS GND GND QCS DNU CSR V DD V DD n.c. n.c. D8 D19 GND GND Q8 Q19 D9 D20 V DD V DD Q9 Q20 D10 D21 GND GND Q10 Q21 D11 D22 V DD V DD Q11 Q22 D12 D23 GND GND Q12 Q23 D13 D24 V DD V DD Q13 Q24 D14 D25 VREF V DD Q14 Q25 002aab108 Fig 4. Ball mapping, 1 : 1 register (C0 = 0, C1 = 0) _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

6 A B C D E F G DE PPO VREF V DD QEA QEB D2 DNU GND GND Q2A Q2B D3 DNU V DD V DD Q3A Q3B DODT QERR GND GND QODTA QODTB D5 n.c. V DD V DD Q5A Q5B D6 n.c. GND GND Q6A Q6B PAR_IN RESET V DD V DD C1 C0 H DCS GND GND QCSA QCSB J K L M N P R T CSR V DD V DD n.c. n.c. D8 DNU GND GND Q8A Q8B D9 DNU V DD V DD Q9A Q9B D10 DNU GND GND Q10A Q10B D11 DNU V DD V DD Q11A Q11B D12 DNU GND GND Q12A Q12B D13 DNU V DD V DD Q13A Q13B D14 DNU VREF V DD Q14A Q14B 002aab109 Fig 5. Ball mapping, 1 : 2 Register A (C0 = 0, C1 = 1) A B C D E F G D1 PPO VREF V DD Q1A Q1B D2 DNU GND GND Q2A Q2B D3 DNU V DD V DD Q3A Q3B D4 QERR GND GND Q4A Q4B D5 DNU V DD V DD Q5A Q5B D6 DNU GND GND Q6A Q6B PAR_IN RESET V DD V DD C1 C0 H DCS GND GND QCSA QCSB J K L M N P R T CSR V DD V DD n.c. n.c. D8 DNU GND GND Q8A Q8B D9 DNU V DD V DD Q9A Q9B D10 DNU GND GND Q10A Q10B DODT DNU V DD V DD QODTA QODTB D12 DNU GND GND Q12A Q12B D13 DNU V DD V DD Q13A Q13B DE DNU VREF V DD QEA QEB 002aab110 Fig 6. Ball mapping, 1 : 2 Register B (C0 = 1, C1 = 1) _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

7 Table Pin description Pin description Symbol Pin Type Description GND B3, B4, D3, D4, F3, F4, H3, H4, K3, K4, M3, M4, P3, P4 ground input ground V DD A4, C3, C4, E3, E4, G3, G4, J3, J4, L3, L4, N3, N4, R3, R4, T4 1.8 V nominal power supply voltage VREF A3, T3 0.9 V nominal input reference voltage H1 differential input positive master clock input J1 differential input negative master clock input C0 G6 LVCMOS inputs Configuration control inputs; Register A or Register B and C1 G5 1 : 1 mode or 1 : 2 mode select. RESET G2 LVCMOS input Asynchronous reset input (active LOW). Resets registers and disables VREF data and clock. CSR J2 SSTL_18 input Chip select inputs (active LOW). Disables D1 to D25 [1] DCS H2 outputs switching when both inputs are HIGH. D1 to D25 [2] SSTL_18 input Data input. Clocked in on the crossing of the rising edge of and the falling edge of. DODT [2] SSTL_18 input The outputs of this register bit will not be suspended by the DCS and CSR control. DE [2] SSTL_18 input The outputs of this register bit will not be suspended by the DCS and CSR control. PAR_IN G1 SSTL_18 input Parity input. Arrives one clock cycle after the corresponding data input. Q1 to Q25, Q2A to Q14A, Q1B to Q14B [2] 1.8 V CMOS outputs PPO A2 1.8 V CMOS output QCS, QCSA, QCSB QODT, QODTA, QODTB QE, QEA, QEB [2] 1.8 V CMOS output [2] 1.8 V CMOS output [2] 1.8 V CMOS output QERR D2 open-drain output [1] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. [2] Depends on configuration. See Figure 4, Figure 5, and Figure 6 for ball number. Data outputs that are suspended by the DCS and CSR control. [3] Partial parity out. Indicates odd parity of inputs D1 to D25. [1] Data output that will not be suspended by the DCS and CSR control. Data output that will not be suspended by the DCS and CSR control. Data output that will not be suspended by the DCS and CSR control. Output error bit (active LOW). Generated one clock cycle after the corresponding data output. n.c. [2] - Not connected. Ball present but no internal connection to the die. DNU [2] - Do not use. Inputs are in standby-equivalent mode and outputs are driven LOW. _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

8 [3] Data outputs = Q2, Q3, Q5, Q6, Q8 to Q25 when C0 = 0 and C1 = 0. Data outputs = Q2, Q3, Q5, Q6, Q8 to Q14 when C0 = 0 and C1 = 1. Data outputs = Q1 to Q6, Q8 to Q10, Q12, Q13 when C0 = 1 and C1 = Functional description The is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity, designed for 1.7 V to 2.0 V V DD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control and reset (RESET) inputs are LVCMOS. All data outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load, and meet SSTL_18 specifications. The error (QERR) output is 1.8 V open-drain driver. The operates from a differential clock ( and ). Data are registered at the crossing of going HIGH, and going LOW. The C0 input controls the pinout configuration for the 1 : 2 pinout from A configuration (when LOW) to B configuration (when HIGH). The C1 input controls the pinout configuration from 25-bit 1 : 1 (when LOW) to 14-bit 1 : 2 (when HIGH). The accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. When used as a single device, the C0 and C1 inputs are tied LOW. In this configuration, parity is checked on the PAR_IN input which arrives one cycle after the input data to which it applies. The Partial-Parity-Out (PPO) and QERR signals are produced three cycles after the corresponding data inputs. When used in pairs, the C0 input of the first register is tied LOW and the C0 input of the second register is tied HIGH. The C1 input of both registers are tied HIGH. Parity, which arrives one cycle after the data input to which it applies, is checked on the PAR_IN input of the first device. The PPO and QERR signals are produced on the second device three clock cycles after the corresponding data inputs. The PPO output of the first register is cascaded to the PAR_IN of the second register. The QERR output of the first register is left floating and the valid error information is latched on the QERR output of the second register. If an error occurs and the QERR output is driven LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. The DIMM-dependent signals (DE, DCS, DODT, and CSR) are not included in the parity check computation. The device supports low-power standby operation. When RESET is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET is LOW all registers are reset, and all outputs are forced LOW. The LVCMOS RESET input must always be held at a valid logic HIGH or LOW level. _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

9 The device also supports low-power active operation by monitoring both system chip select (DCS and CSR) inputs and will gate the Qn and PPO outputs from changing states when both DCS and CSR inputs are HIGH. If either DCS or CSR input is LOW, the Qn and PPO outputs will function normally. The RESET input has priority over the DCS and CSR control and when driven LOW will force the Qn and PPO outputs LOW, and the QERR output HIGH. If the DCS control functionality is not desired, then the CSR input can be hard-wired to ground, in which case, the set-up time requirement for DCS would be the same as for the other Dn data inputs. To control the low-power mode with DCS only, then the CSR input should be pulled up to V DD through a pull-up resistor. To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the LOW state during power-up. In the DDR2 RDIMM application, RESET is specified to be completely asynchronous with respect to and. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the Qn outputs will be driven LOW quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are LOW, and the clock is stable during the time from the LOW to HIGH transition of RESET until the input receivers are fully enabled, the design of the must ensure that the outputs will remain LOW, thus ensuring no glitches on the output. 7.1 Function table Table 4. Function table (each flip-flop) L = LOW voltage level; H = HIGH voltage level; X = don t care; = LOW to HIGH transition; = HIGH to LOW transition. Inputs Outputs [1] RESET DCS CSR Dn, DODTn, DEn [1] Q 0 is the previous state of the associated output. Qn QCS QODT, QE H L L L L L L H L L H H L H H L L L or H L or H X Q 0 Q 0 Q 0 H L H L L L L H L H H H L H H L H L or H L or H X Q 0 Q 0 Q 0 H H L L L H L H H L H H H H H H L L or H L or H X Q 0 Q 0 Q 0 H H H L Q 0 H L H H H H Q 0 H H H H H L or H L or H X Q 0 Q 0 Q 0 L X or floating X or floating X or floating X or floating X or floating L L L _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

10 Table 5. Parity and standby function table L = LOW voltage level; H = HIGH voltage level; X = don t care; = LOW to HIGH transition; = HIGH to LOW transition. Inputs Outputs [1] RESET DCS CSR of inputs = H PAR_IN [2] PPO [3] QERR [4] (D1 to D25) H L X even L L H H L X odd L H L H L X even H H L H L X odd H L H H H L even L L H H H L odd L H L H H L even H H L H H L odd H L H H H H X X PPO 0 QERR 0 H X X L or H L or H X X PPO 0 QERR 0 L X or floating X or floating X or floating X or floating X or floating X or floating L H [1] PPO 0 is the previous state of output PPO; QERR 0 is the previous state of output QERR. [2] Data inputs = D2, D3, D5, D6, D8 to D25 when C0 = 0 and C1 = 0. Data inputs = D2, D3, D5, D6, D8 to D14 when C0 = 0 and C1 = 1. Data inputs = D1 to D6, D8 to D10, D12, D13 when C0 = 1 and C1 = 1. [3] PAR_IN arrives one clock cycle (C0 = 0), or two clock cycles (C0 = 1), after the data to which it applies. [4] This condition assumes QERR is HIGH at the crossing of going HIGH and going LOW. If QERR is LOW, it stays latched LOW for two clock cycles or until RESET is driven LOW. 8. Limiting values Table 6. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter Conditions Min Max Unit V DD supply voltage V V I input voltage receiver 0.5 [1] +2.5 [2] V V O output voltage driver 0.5 [1] V DD +0.5 [2] V I IK input clamping current V I <0V or V I >V DD - 50 ma I OK output clamping current V O <0V or V O >V DD - ±50 ma I O output current continuous; 0 V < V O < V DD - ±50 ma I CCC continuous current through - ±100 ma each V DD or GND pin T stg storage temperature C V ESD electrostatic discharge Human Body Model (HBM); 1.5 kω; 100 pf 2 - kv voltage Machine Model (MM); 0 Ω; 200 pf V [1] The input and output negative voltage ratings may be exceeded if the input and output clamping current ratings are observed. [2] This value is limited to 2.5 V maximum. _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

11 9. Recommended operating conditions Table 7. Recommended operating conditions Symbol Parameter Conditions Min Typ Max Unit V DD supply voltage V V ref reference voltage 0.49 V DD 0.50 V DD 0.51 V DD V V T termination voltage V ref V ref V ref V V I input voltage 0 - V DD V V IH(AC) AC HIGH-level input voltage data (Dn), CSR, and V ref V PAR_IN inputs V IL(AC) AC LOW-level input voltage data (Dn), CSR, and - - V ref V PAR_IN inputs V IH(DC) DC HIGH-level input voltage data (Dn), CSR, and V ref V PAR_IN inputs V IL(DC) DC LOW-level input voltage data (Dn), CSR, and - - V ref V PAR_IN inputs V IH HIGH-level input voltage RESET, Cn [1] 0.65 V DD - - V V IL LOW-level input voltage RESET, Cn [1] V DD V V ICR common mode input voltage, [2] V range V ID differential input voltage, [2] mv I OH HIGH-level output current ma I OL LOW-level output current ma T amb ambient temperature operating in free air EC/G 0-70 C EC/S 0-85 C [1] The RESET and Cn inputs of the device must be held at valid levels (not floating) to ensure proper device operation. [2] The differential inputs must not be floating, unless RESET is LOW. _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

12 10. Characteristics Table 8. Characteristics At recommended operating conditions (see Table 7); unless otherwise specified. Symbol Parameter Conditions Min Typ Max Unit V OH HIGH-level output voltage I OH = 6 ma; V DD = 1.7 V V V OL LOW-level output voltage I OL =6mA; V DD =1.7V V I I input current all inputs; V I =V DD or GND; V DD =2.0V - - ±5 μa I DD supply current static Standby mode; RESET = GND; ma I O =0mA; V DD =2.0V static Operating mode; RESET =V DD ; I O =0mA; V DD =2.0V; V I =V IH(AC) or V IL(AC) ma I DDD dynamic operating current per MHz clock only; RESET =V DD ; V I =V IH(AC) or V IL(AC) ; and switching at 50 % duty cycle; I O =0mA; V DD =1.8V per each data input, 1 : 1 mode; RESET =V DD ; V I =V IH(AC) or V IL(AC) ; and switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; I O =0mA; V DD =1.8V per each data input, 1 : 2 mode; RESET =V DD ; V I =V IH(AC) or V IL(AC) ; and switching at 50 % duty cycle; one data input switching at half clock frequency, 50 % duty cycle; I O =0mA; V DD =1.8V μa μa μa C i input capacitance data and CSR inputs; pf V I =V ref ± 250 mv; V DD =1.8V and inputs; V ICR =0.9V; 2-3 pf V i(p-p) = 600 mv; V DD =1.8V RESET input; V I =V DD or GND; V DD =1.8V 3-4 pf Input RESET V IL LOW-level input voltage V DD V V IH HIGH-level input voltage 0.7V DD V I I input current V I =V DD μa I L leakage current V I =V SS μa _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

13 Table 9. Timing requirements At recommended operating conditions (see Table 7), unless otherwise specified. See Section Symbol Parameter Conditions Min Typ Max Unit f clock clock frequency MHz t W pulse width, HIGH or LOW ns t ACT differential inputs active time [1][2] ns t INACT differential inputs inactive time [1][3] ns t su set-up time DCS before,, CSR HIGH; ns CSR before,, DCS HIGH DCS before,, CSR LOW ns DODT, DE and data (Dn) before, ns PAR_IN before, ns t h hold time DCS, DODT, DE and data (Dn) after ns, PAR_IN after, ns [1] This parameter is not necessarily production tested. [2] VREF must be held at a valid input voltage level and data inputs must be held LOW for a minimum time of t ACT(max) after RESET is taken HIGH. [3] VREF, data and clock inputs must be held at valid levels (not floating) a minimum time of t INACT(max) after RESET is taken LOW. Table 10. Switching characteristics At recommended operating conditions (see Table 7), unless otherwise specified. See Section Symbol Parameter Conditions Min Typ Max Unit f max maximum input clock frequency MHz t PDM peak propagation delay single bit switching; [1] ns from and to Qn t PD propagation delay from and to PPO ns t LH LOW to HIGH delay from and to QERR ns t HL HIGH to LOW delay from and to QERR ns t PDMSS simultaneous switching peak from and to Qn [1][2] ns propagation delay t PHL HIGH to LOW propagation delay from RESET to Qn ns from RESET to PPO ns t PLH LOW to HIGH propagation delay from RESET to QERR ns [1] Includes 350 ps of test load transmission line delay. [2] This parameter is not necessarily production tested. Table 11. Data output edge rates At recommended operating conditions (see Table 7), unless otherwise specified. See Section Symbol Parameter Conditions Min Typ Max Unit dv/dt_r rising edge slew rate from 20 % to 80 % 1-4 V/ns dv/dt_f falling edge slew rate from 80 % to 20 % 1-4 V/ns dv/dt_δ absolute difference between dv/dt_r and dv/dt_f from 20 % or 80 % to 80 % or 20 % V/ns _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

14 10.1 Timing diagrams RESET DCS CSR m m + 1 m + 2 m + 3 m + 4 t su t h D1 to D25 Q1 to Q25 t PD to Q t su t h PAR_IN t PD to PPO PPO t PD to QERR t PD to QERR QERR 002aaa655 Fig 7. Timing diagram for used as a single device; C0 = 0, C1 = 0 _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

15 RESET DCS CSR m m + 1 m + 2 m + 3 m + 4 t su t h D1 to D14 Q1 to Q14 t PD to Q t su t h PAR_IN t PD to PPO PPO t PD to QERR t PD to QERR QERR (not used) 002aaa656 Fig 8. Timing diagram for the first (1 : 2 Register A configuration) device used in pair; C0 = 0, C1 = 1 _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

16 RESET DCS CSR m m + 1 m + 2 m + 3 m + 4 t su t h D1 to D14 Q1 to Q14 t PD to Q t su t h PAR_IN (1) t PD to PPO PPO (not used) t PD to QERR t PD to QERR QERR 002aaa657 Fig 9. (1) PAR_IN is driven from PPO of the first device. Timing diagram for the second (1 : 2 Register B configuration) device used in pair; C0 = 1, C1 = 1 _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

17 11. Test information 11.1 Parameter measurement information for data output load circuit V DD =1.8V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z o =50Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. The outputs are measured one at a time with one transition per measurement. V DD inputs 50 Ω test point DUT OUT delay = 350 ps Zo = 50 Ω CL = 30 pf (1) RL = 1000 Ω RL = 1000 Ω RL = 100 Ω test point 002aaa371 (1) C L includes probe and jig capacitance. Fig 10. Load circuit, data output measurements LVCMOS V DD RESET 0.5V DD 0.5V DD 0 V t INACT t ACT I DD (1) 10 % 90 % 002aaa372 (1) I DD tested with clock and data inputs held at V DD or GND, and I O =0mA. Fig 11. Voltage and current waveforms; inputs active and inactive times t W input V IH V ICR V ICR V ID V IL 002aaa373 Fig 12. V ID = 600 mv. V IH =V ref mv (AC voltage levels) for differential inputs. V IH =V DD for LVCMOS inputs. V IL =V ref 250 mv (AC voltage levels) for differential inputs. V IL = GND for LVCMOS inputs. Voltage waveforms; pulse duration _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

18 V ICR V ID t su t h V IH input V ref V ref V IL 002aaa374 Fig 13. V ID = 600 mv. V ref =0.5V DD. V IH =V ref mv (AC voltage levels) for differential inputs. V IH =V DD for LVCMOS inputs. V IL =V ref 250 mv (AC voltage levels) for differential inputs. V IL = GND for LVCMOS inputs. Voltage waveforms; set-up and hold times V ICR t PLH V ICR t PHL V i(p-p) output V T V OH V OL 002aaa375 Fig 14. t PLH and t PHL are the same as t PD. Voltage waveforms; propagation delay times (clock to output) RESET LVCMOS 0.5V DD V IH t PHL V IL output V T V OH V OL 002aaa376 Fig 15. t PLH and t PHL are the same as t PD. V IH =V ref mv (AC voltage levels) for differential inputs. V IH =V DD for LVCMOS inputs. V IL =V ref 250 mv (AC voltage levels) for differential inputs. V IL = GND for LVCMOS inputs. Voltage waveforms; propagation delay times (reset to output) _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

19 11.2 Data output slew rate measurement information V DD =1.8V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z o =50Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. V DD DUT R L = 50 Ω OUT test point C L = 10 pf (1) 002aaa377 Fig 16. (1) C L includes probe and jig capacitance. Load circuit, HIGH-to-LOW slew measurement output V OH dv_f 80 % 20 % dt_f 002aaa378 V OL Fig 17. Voltage waveforms, HIGH-to-LOW slew rate measurement DUT OUT test point C L = 10 pf (1) R L = 50 Ω 002aaa379 Fig 18. (1) C L includes probe and jig capacitance. Load circuit, LOW-to-HIGH slew measurement output dv_r dt_r 20 % 80 % 002aaa380 V OH V OL Fig 19. Voltage waveforms, LOW-to-HIGH slew rate measurement _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

20 11.3 Error output load circuit and voltage measurement information V DD =1.8V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z o =50Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. V DD DUT R L = 1 kω OUT test point C L = 10 pf (1) 002aaa500 Fig 20. (1) C L includes probe and jig capacitance. Load circuit, error output measurements LVCMOS V DD RESET 0.5V DD 0 V t PLH output waveform V V OH 0 V 002aaa501 Fig 21. Voltage waveforms, open-drain output LOW to HIGH transition time with respect to RESET input. timing inputs V ICR VICR V i(p-p) t HL V DD output waveform 1 0.5V DD V OL 002aaa502 Fig 22. Voltage waveforms, open-drain output HIGH to LOW transition time with respect to clock inputs _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

21 timing inputs V ICR VICR V i(p-p) t LH output waveform V V OH 0 V 002aaa503 Fig 23. Voltage waveforms, open-drain output LOW to HIGH transition time with respect to clock inputs 11.4 Partial parity out load circuit and voltage measurement information V DD =1.8V± 0.1 V. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz; Z o =50Ω; input slew rate = 1 V/ns ± 20 %, unless otherwise specified. DUT OUT test point C L = 5 pf (1) R L = 1 kω 002aaa654 Fig 24. (1) C L includes probe and jig capacitance. Partial parity out load circuit V ICR t PLH V ICR t PHL V i(p-p) output V T V OH V OL 002aaa375 Fig 25. V T =0.5V DD. t PLH and t PHL are the same as t PD. V i(p-p) = 600 mv. Partial parity out voltage waveforms; propagation delay times with respect to clock inputs _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

22 RESET LVCMOS 0.5V DD V IH t PHL V IL output V T V OH V OL 002aaa376 Fig 26. V T =0.5V DD. t PLH and t PHL are the same as t PD. V IH =V ref mv (AC voltage levels) for differential inputs. V IH =V DD for LVCMOS inputs. V IL =V ref 250 mv (AC voltage levels) for differential inputs. V IL = GND for LVCMOS inputs. Partial parity out voltage waveforms; propagation delay times with respect to RESET input _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

23 12. Package outline LFBGA96: plastic low profile fine-pitch ball grid array package; 96 balls; body 13.5 x 5.5 x 1.05 mm SOT536-1 D B A ball A1 index area E A A 2 A 1 detail X e e 1 1/2 e b v M w M C C A B y 1 C C y T R P N M L K J H G F E D C B A ball A1 index area e 1/2 e e 2 X mm DIMENSIONS (mm are the original dimensions) A UNIT A 1 A 2 b D E e e 1 e 2 v w y max. mm scale y OUTLINE VERSION SOT536-1 REFERENCES IEC JEDEC JEITA EUROPEAN PROJECTION ISSUE DATE Fig 27. Package outline SOT536-1 (LFBGA96) _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

24 13. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 Surface mount reflow soldering description Introduction to soldering Soldering is one of the most common methods through which packages are attached to Printed Circuit Boards (PCBs), to form electrical circuits. The soldered joint provides both the mechanical and the electrical connection. There is no single soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and Surface Mount Devices (SMDs) are mixed on one printed wiring board; however, it is not suitable for fine pitch SMDs. Reflow soldering is ideal for the small pitches and high densities that come with increased miniaturization Wave and reflow soldering Wave soldering is a joining technology in which the joints are made by solder coming from a standing wave of liquid solder. The wave soldering process is suitable for the following: Through-hole components Leaded or leadless SMDs, which are glued to the surface of the printed circuit board Not all SMDs can be wave soldered. Packages with solder balls, and some leadless packages which have solder lands underneath the body, cannot be wave soldered. Also, leaded SMDs with leads having a pitch smaller than ~0.6 mm cannot be wave soldered, due to an increased probability of bridging. The reflow soldering process involves applying solder paste to a board, followed by component placement and exposure to a temperature profile. Leaded packages, packages with solder balls, and leadless packages are all reflow solderable. Key characteristics in both wave and reflow soldering are: Board specifications, including the board finish, solder masks and vias Package footprints, including solder thieves and orientation The moisture sensitivity level of the packages Package placement Inspection and repair Lead-free soldering versus SnPb soldering 13.3 Wave soldering Key characteristics in wave soldering are: Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave Solder bath specifications, including temperature and impurities _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

25 13.4 Reflow soldering Key characteristics in reflow soldering are: Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see Figure 28) than a SnPb process, thus reducing the process window Solder paste printing issues including smearing, release, and adjusting the process window for a mix of large and small components on one board Reflow temperature profile; this profile includes preheat, reflow (in which the board is heated to the peak temperature) and cooling down. It is imperative that the peak temperature is high enough for the solder to make reliable solder joints (a solder paste characteristic). In addition, the peak temperature must be low enough that the packages and/or boards are not damaged. The peak temperature of the package depends on package thickness and volume and is classified in accordance with Table 12 and 13 Table 12. SnPb eutectic process (from J-STD-020C) Package thickness (mm) Package reflow temperature ( C) Volume (mm 3 ) < < Table 13. Lead-free process (from J-STD-020C) Package thickness (mm) Package reflow temperature ( C) Volume (mm 3 ) < to 2000 > 2000 < to > Moisture sensitivity precautions, as indicated on the packing, must be respected at all times. Studies have shown that small packages reach higher temperatures during reflow soldering, see Figure 28. _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

26 temperature maximum peak temperature = MSL limit, damage level minimum peak temperature = minimum soldering temperature peak temperature time 001aac844 Fig 28. MSL: Moisture Sensitivity Level Temperature profiles for large and small components 14. Abbreviations For further information on temperature profiles, refer to Application Note AN10365 Surface mount reflow soldering description. Table 14. Acronym CMOS DDR DIMM LVCMOS PPO PRR RDIMM SSTL Abbreviations Description Complementary Metal Oxide Semiconductor Double Data Rate Dual In-line Memory Module Low Voltage Complementary Metal Oxide Semiconductor Partial Parity Out Pulse Repetition Rate Registered Dual In-line Memory Module Stub Series Terminated Logic _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

27 15. Revision history Table 15. Revision history Document ID Release date Data sheet status Change notice Supersedes _ Product data sheet - _3 Modifications: Section 1 General description, first paragraph: deleted second sentence Table 8 Characteristics : added sub-section Input RESET _ Product data sheet - _2 _ Product data sheet - _1 _ Product data sheet - - _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

28 16. Legal information 16.1 Data sheet status Document status [1][2] Product status [3] Definition Objective [short] data sheet Development This document contains data from the objective specification for product development. Preliminary [short] data sheet Qualification This document contains data from the preliminary specification. Product [short] data sheet Production This document contains the product specification. [1] Please consult the most recently issued document before initiating or completing a design. [2] The term short data sheet is explained in section Definitions. [3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status information is available on the Internet at URL Definitions Draft The document is a draft version only. The content is still under internal review and subject to formal approval, which may result in modifications or additions. NXP Semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall have no liability for the consequences of use of such information. Short data sheet A short data sheet is an extract from a full data sheet with the same product type number(s) and title. A short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. Product specification The information and data provided in a Product data sheet shall define the specification of the product as agreed between NXP Semiconductors and its customer, unless NXP Semiconductors and customer have explicitly agreed otherwise in writing. In no event however, shall an agreement be valid in which the NXP Semiconductors product is deemed to offer functions and qualities beyond those described in the Product data sheet Disclaimers Limited warranty and liability Information in this document is believed to be accurate and reliable. However, NXP Semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. Notwithstanding any damages that customer might incur for any reason whatsoever, NXP Semiconductors aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the Terms and conditions of commercial sale of NXP Semiconductors. Right to make changes NXP Semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. This document supersedes and replaces all information supplied prior to the publication hereof. Suitability for use NXP Semiconductors products are not designed, authorized or warranted to be suitable for use in medical, military, aircraft, space or life support equipment, nor in applications where failure or malfunction of an NXP Semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. NXP Semiconductors accepts no liability for inclusion and/or use of NXP Semiconductors products in such equipment or applications and therefore such inclusion and/or use is at the customer s own risk. Applications Applications that are described herein for any of these products are for illustrative purposes only. NXP Semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. NXP Semiconductors does not accept any liability related to any default, damage, costs or problem which is based on a weakness or default in the customer application/use or the application/use of customer s third party customer(s) (hereinafter both referred to as Application ). It is customer s sole responsibility to check whether the NXP Semiconductors product is suitable and fit for the Application planned. Customer has to do all necessary testing for the Application in order to avoid a default of the Application and the product. NXP Semiconductors does not accept any liability in this respect. Limiting values Stress above one or more limiting values (as defined in the Absolute Maximum Ratings System of IEC 60134) will cause permanent damage to the device. Limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the Recommended operating conditions section (if present) or the Characteristics sections of this document is not warranted. Constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. Terms and conditions of commercial sale NXP Semiconductors products are sold subject to the general terms and conditions of commercial sale, as published at unless otherwise agreed in a valid written individual agreement. In case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. NXP Semiconductors hereby expressly objects to applying the customer s general terms and conditions with regard to the purchase of NXP Semiconductors products by customer. No offer to sell or license Nothing in this document may be interpreted or construed as an offer to sell products that is open for acceptance or the grant, conveyance or implication of any license under any copyrights, patents or other industrial or intellectual property rights. Export control This document as well as the item(s) described herein may be subject to export control regulations. Export might require a prior authorization from national authorities. Non-automotive qualified products Unless this data sheet expressly states that this specific NXP Semiconductors product is automotive qualified, the product is not suitable for automotive use. It is neither qualified nor tested in accordance with automotive testing or application requirements. NXP Semiconductors accepts no liability for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. In the event that customer uses the product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without NXP Semiconductors warranty of the _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

29 product for such automotive applications, use and specifications, and (b) whenever customer uses the product for automotive applications beyond NXP Semiconductors specifications such use shall be solely at customer s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors standard warranty and NXP Semiconductors product specifications Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. 17. Contact information For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com _4 All information provided in this document is subject to legal disclaimers. NXP B.V All rights reserved. Product data sheet Rev April of 30

30 18. Contents 1 General description Features and benefits Applications Ordering information Ordering options Functional diagram Pinning information Pinning Pin description Functional description Function table Limiting values Recommended operating conditions Characteristics Timing diagrams Test information Parameter measurement information for data output load circuit Data output slew rate measurement information Error output load circuit and voltage measurement information Partial parity out load circuit and voltage measurement information Package outline Soldering of SMD packages Introduction to soldering Wave and reflow soldering Wave soldering Reflow soldering Abbreviations Revision history Legal information Data sheet status Definitions Disclaimers Trademarks Contact information Contents Please be aware that important notices concerning this document and the product(s) described herein, have been included in section Legal information. NXP B.V All rights reserved. For more information, please visit: For sales office addresses, please send an to: salesaddresses@nxp.com Date of release: 15 April 2010 Document identifier: _4