PI74SSTVF32852A. 24-Bit to 48-Bit Registered Buffer. Product Description. Product Features. Logic Block Diagram. Product Pin Description

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1 PI74SSTF32852A Product Features PI74 SSTF32852A is designed f low-voltage operation, 2.5 f PC1600 ~ PC2700; 2.6 f PC3200 Suppts SSTL_2 Class I specifications on outputs All s are SSTL_2 Compatible, except which is LCMOS. Designed f DDR Memy Packaging: 114-Ball LFBGA Pb-free available Logic Block Diagram D1 REF A3 A4 R3 T2 R4 Product Pin Description Pin Name D Q DD DDQ REF R D TO 23 OTER CANNELS Descriptio n Reset (Active Low) LCMO S A2 A5 Clock, Positive Differential Clock, Negative Differential Data Data Output Ground Ce Supply oltage, 2.5 Nomina l Output Supply oltage, 2.5 Nomina l Reference oltage, 1.25 Nomina l Q1A Q1B Product Description Pericom Semiconduct s PI74SSTF32852A logic circuit is produced using the Company s advanced sub-micron CMOS technology, achieving industry leading speed. All inputs are compatible with the JEDEC standard f SSTL_2, except the LCMOS reset () input. All outputs are SSTL_2, Class II compatible. The device operates from a differential clock (CK and CK). Data registered at the crossing of CK going IG, and CK going LOW. The PI74SSTF32852A suppts low-power standby operation. When is LOW, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (REF) inputs are allowed. In addition, when is LOW, all registers are reset, and all outputs are fced LOW. The LCMOS input must always be held at a valid logic IG LOW level. To ensure defined outputs from the register befe a stable clock has been supplied, must be held in the LOW state during power up. In the DDR DIMM application, is specified to be completely asynchronous with respect to CK and CK. Therefe, no timing relationship can be guaranteed between the two. When entering, the register will be cleared and the outputs will be driven LOW quickly, relative to the time to disable the differential input receivers, thus ensuring no glitches on the output. owever, when coming out of, the register will become active quickly, relative to the time to enable the differential input receivers. When the data inputs are LOW, and the clock is stable, during the time from the LOW-to-IG transition of until the input receivers are fully enabled, the design must ensure that the outputs will remain LOW. Pericom s PI74SSTF32852A is characterized f operation from 0 to 70 C. Truth Table (1) L X Floatin g s Output s D Q X Floatin g X Floatin g Η L L L L L X o Q (2) Notes: 1. = igh Signal Level; L = Low Signal Level; = Transition LOW-to-IG; = Transition IG-to-LOW X = Irrelevant floating 2. Output level befe the indicated steady state input conditions were established. 1 PS8682A 11/10/08

2 PI74SSTF32852A Product Pin Configuration A B C D E F G J K L M N P R Q2A Q1A Q3A DDQ Q5A Q7A Q8A Q10A Q12A Q13A Q14A Q17A Q18A Q4A DQ Q6A D DDQ DQ Q9A DQ Q11A Q1B DDQ D DDQ D DDQ CC DDQ DDQ Q15A Q16A DQ Q19A Q20A DDQ Q22A Q23A DDQ Q24A D DDQ Q21A DQ CC D DDQ REF Q4B Q6B Q9B Q11B CC Q15B Q16B Q19B DDQ Q21B DDQ T D2 D1 D6 D18 D13 D14 U D4 D3 D10 D22 D15 D16 D5 D7 D11 D23 D19 D17 W D8 D9 D12 D24 D21 D20 NB Package (Top iew) A B C D E F G J K L M N P R T U W CC Q2B Q3B Q5B Q7B Q8B Q10B Q12B Q13B Q14B Q17B Q18B Q20B Q22B Q23B Q24B 2 PS8682A 11/10/08

3 PI74SSTF32852A Maximum Ratings (Above which the useful life may be impaired. F user guidelines, not tested.) Stage Item temperature Supply voltage I nput voltage 1,2) O utput voltage 1,2) clamp current Output clamp current ontinuous output current DD, DDQ current/pi n P ackage Thermal Impedance 3) Symbol/Condition s T tg Ratings 65 to to to 0.5 to D 5 ±5 ±5 ±10 s 0 DD DDQ 6 DD D Q +0. 5, I < 0 I > DD 0, O < 0 O > DDQ 0, O =0 to DDQ 0 I DD, IDDQ I 0 ( I ( O I IK I OK C I O C ( θj A 36 C/ W Note: Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions f extended periods may affect reliability. 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This value is limited to 3.6 Maximum. 3. The package thermal impedance is calculated in accdance with JESD ma Recommended Operating Conditions (4) Parameters DD / DDQ REF TT I I IL I IL I IL ICR ID I O I OL T A Ce Output Supply oltage Reference oltage D escriptio n M in. N om. REF = 0.5X DDQ PC1600 PC PC PC1600 PC2700 Termination oltag e EF PC R 0.04 EF R REF oltag e 0 DD AC igh -Level oltag e AC Low -Level oltag e R EF 310m Data s DC igh -Level oltag e REF + 150m REF m DC Low -Level oltag e REF 150m igh -Level oltag e 1.7 Reset Low -Level oltag e 0. 7 Common-mode input range CK, CK Differential oltag e igh-level Output Current 16 ma Low-Level Output Current 16 Operating Free-Air Temperatur e 0 70 º C Note: 4. The input of the device must be held at DD to ensure proper device operation. The differential inputs must not be floating, unless is LOW. 3 PS8682A 11/10/08

4 PI74SSTF32852A DC Electrical Characteristics f PC1600 ~ PC2700 (Over the Operating Range, T A = 0 C to +70 C, DD = 2.5 ± 200m, DDQ = 2.5 ± 200m) Parameters (1) Test Conditions CC M in. Typ. IK II = 18mA IO = 100μA D D 0.2 O IO = 8mA IOL = 100μA OL IO =8mA I I All s, I = DD Standby (Static) I D D Operating Static IDDD Dynamic Operating - Clock only Dynamic Operating -per each data input = = DD I = I ( AC) I (AC) = DD I = I( AC) I L(AC), CK and CK switching 50% duty cycle = DD I = I ( AC) o r I L(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle I O =0 2.7 ± μa 35 ma μa/ clock μa/ clock Data C I Data inputs I = REF ± 310m CK and CK ICR = 1.25, I(PP) = 360m I = CC pf Note: 1. All typical values are at DD = 2.5, T A = 25 C. 4 PS8682A 11/10/08

5 PI74SSTF32852A DC Electrical Characteristics f PC3200 (Over the Operating Range, T A = 0 C to +70 C, DD = 2.6 ± 100m, DDQ = 2.6 ± 100m) Parameters Test Conditions CC M in. T yp. ( 1) Max. IK II = 18mA IO = 100μA D D 0.2 O IO = 8mA IOL = 100μA OL IO =8mA I I All s, I = DD Standby (Static) I D D Operating Static IDDD Dynamic Operating - Clock only Dynamic Operating -per each data input = = DD I = I ( AC) I (AC) = DD I = I( AC) I L(AC), CK and CK switching 50% duty cycle = DD I = I ( AC) o r I L(AC), CK and CK switching 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle I O =0 2.7 ± μa 35 ma μa/ clock μa/ clock Data C I Data inputs I = REF ± 350m CK and CK ICR = 1.25, I(PP) = 360m I = CC pf Note: 1. All typical values are at DD = 2.5, T A = 25 C. 5 PS8682A 11/10/08

6 PI74SSTF32852A Timing Requirements (over recommended operating free-air temperature range, unless otherwise noted) DD= 2. 5 ± 0.2 DD= 2. 6 ±0.1 M in. M ax. M in. fclock t W Clock Frequenc y Pulse Duration,, igh Low tact Differential inputs igh active time, data inputs must be low after t inac t t SU t h Differential s inactive time, data and clock inputs must be held at valid levels (not floating) after Low S etup time, fast slew rate (5,7) Setup time, slow slew rate old time, fast slew rate (5,7) old time, slow slew rate 6,7) Data befe CK,CK ( 6,7). 9 Data befe CK,CK ( ns Notes: 5. Data signal input slew rate 1 /ns 6. Data signal input slew rate 0.5/ns and <1/ns 7., input slew rates are 1 /ns. Switching Characteristics f PC1600 ~ PC2700 (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching wavefms). Parameter From () To (Output) DD = 2.5 ±0.2 M in. T yp. fma x 210 t pd tphl, Q Q 5. 0 ns Switching Characteristics f PC3200 (over recommended operating free-air temperature range, unless otherwise noted.) (See test circuits and switching wavefms). Parameter From () To (Output) DD = 2.6 ±0.1 M in. T yp. fma x 210 t pd tphl, Q Q 5. 0 ns 6 PS8682A 11/10/08

7 PI74SSTF32852A Test Circuit and Switching Wavefms LCMOS I DD (9) DD /2 tinact 10% DD 0 From Output Under Test tact 500Ω I DD 90% I DDL Load Circuit Test Point CL = 30pF (8) oltage and Current Wavefms Active and Inactive Times Timing ICR ICR I(PP) REF tw REF I Output t PL TT t PL TT O IL OL oltage Wavefms - Pulse Duration oltage Wavefms - Propagation Delay Times Timing tsu REF ICR oltage Wavefms - Setup and old Times th REF I(PP) I IL LCMOS Output DD /2 t PL TT oltage Wavefms - Propagation Delay Times I IL O OL Parameter Measurement Infmation Notes: 8. C L includes probe and jig capacitance. 9. I DD tested with clock and data inputs held at DD, and I O = 0mA. 10. All input pulses are supplied by generats having the following characteristics: PRR 10, Z O = 50 ohms. slew rate = 1/ns ±20% (unless otherwise specified). 11. The outputs are measured one at a time with one transition per measurement. 12. TT = REF = DDQ /2 13. I = REF + 310m (ac voltage levels) f SSTL inputs. I = DD f LCMOS input. 14. IL = REF + 310m (ac voltage levels) f SSTL inputs. IL = f LCMOS input. 15. t PL and t PL are the same as t pd. 7 PS8682A 11/10/08

8 PI74SSTF32852A 114-Ball LFBGA (NB) Package ± BSC 0.87mm. Min. (2 layer) 0.90mm. Min. (4 layer) 1.40 (2 layer) 1.45 (4 layer) Ordering Infmation Ordering Code PI74SSTF32852ANB Package Code NB Package Type 114-Ball LFBGA Notes: 1. Thermal characteristics can be found on the company web site at Pericom Semiconduct Cpation 2380 Bering Drive San Jose, CA Fax (408) PS8682A 11/10/08