PI6CV

Transcription

1 for 2.5 R-SDRAM Memory Product Features PLL clock distribution optimized for Double Data Rate SDRAM applications. Distributes one differential clock input pair to ten differential clock output pairs. Inputs (,) and (,): SSTL_2 Input PWRDWN: LCMOS Outputs (Yx, Yx), (, ): SSTL_2 External feedback pins (,) are used to synchronize the outputs to the clock input. Operates at A = 2.5 for core circuit and internal PLL, and Q = 2.5 for differential output drivers Packaging: (Pb-free & Green available) Plastic 48-pin TSSOP (A) Block Diagram/Pin Configuration Product Description PI6C857 PLL clock device is developed for registered R DIMM applications This PLL Clock Buffer is designed for 2.5 Q and 2.5 A operation and differential data input and output levels. Package options include plastic Thin Shrink Small-Outline Package (TSSOP).The device is a zero delay buffer that distributes a differential clock input pair (, ) to ten differential pairs of clock outputs (Y[0:9], Y[0:9]) and one differential pair feedback clock outputs (,). The clock outputs are controlled by the input clocks (, ), the feedback clocks (,), the 2.5 LCMOS input (PWRDWN) and the Analog Power input (A ). When input PWRDWN is low while power is applied, the input receivers are disabled, the PLL is turned off and the differential clock outputs are 3-stated. When the A is strapped low, the PLL is turned off and bypassed for test purposes. When the input frequency falls below a suggested detection frequency that is below the operating frequency of the PLL, the device will enter a low power mode. An input frequency detection circuit will detect the low frequency condition and perform the same low power features as when the PWRDWN input is low. The PLL in the PI6C857 clock driver uses input clocks (, ) and feedback clocks (,) to provide high-performance, lowskew, low-jitter output differential clocks (Y[0:9], Y[0:9]). PI6C857 is also able to track Spread Spectrum Clocking for reduced EMI. PWRDWN A PLL Powerdown and Test Logic Y0 Y0 Y Y Y2 Y2 Y3 Y3 Y4 Y4 Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 Y0 Y0 Y Y Y2 Y2 A A Y3 Y3 Y4 Y Pin A Y5 Y5 Y6 Y6 Y7 Y7 PWRDWN Y8 Y8 Y9 Y9

2 Pinout Table P in Name Pin No. I/O Type Descriptio n 3 4 I Reference Clock inpu t Yx 3,5,0,20,22,27,29,39,44,46 Clock outputs. Yx 2,6,9,9,23,26,30,40,43,47 Complement Clock outputs. O Feedback output, and Complement Feedback Output Feedback output, and Complement Feedback Output PWRDWN 37 Q 4,,2,5,2,28,34,38,45 A 6 I Power Power down and output disable for all Yx and Yx outputs. When PWRDWN = 0, the part is powered down and the differential clock outputs are disabled to a 3-state. When PWRDWN =, all differential clock outputs are enabled and run at the same frequency as. Power Supply for I/O. Analog /core power supply. A can be used to bypass the PLL for testin g purposes. When A is strapped to ground, PLL is bypassed and is buffered directly to the device outputs. A 7 Analog/core ground. Provides the ground reference for the analog/core circuitry Ground,7,8,8,24,25,3,4,42,48 Ground Function Table Inputs Output s PLL State A PWRDWN Y Y H L H L H L H Bypassed/of f H H L H L H L Bypassed/of f X L L H Z Z Z Z off X L H L Z Z Z Z off 2.5(nom) H L H L H L H on 2.5(nom) H H L H L H L on 2.5(nom) X < 20 MHz ( ) Z Z Z Z off Notes: For testing and power saving purposes, PI6C857 will power down if the frequency of the reference inputs, is well below the operating frequency range. The maximum power down clock frequency is below 20 MHz. For example, PI6C857 will be powered down when the, stop running. Z = High impedance X = Don t care 2

3 Absolute Maximum Ratings (Over operating free-air temperature range) Symbol Q, A P aramete r M in. Max. I/O supply voltage range and analog/core supply voltage range Units I O Input voltage range 0. 5 Output voltage range 0. 5 Q Tstg Storage temperatur e o C Note: Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Timing Requirements (Over recommended operating free-air temperature) Symbol Descriptio n A, = 2.5 ±0.2 M in. Max. Units f CK Operating clock frequenc y (,2) A pplication clock frequency 3) ( MHz t t DC STAB Input clock duty cycle % PLL stabilization time after powerup 00 μs Notes:. The PLL is able to handle spread spectrum induced skew. 2. Operating clock frequency indicates a range over which the PLL is able to lock, but in which the clock is not required to meet the other timing parameters. (Used for low-speed debug). 3. Application clock frequency indicates a range over which the PLL meets all of the timing parameters. 3

4 DC Specifications Recommended Operating Conditions Symbol A Q IL IH OH OL IX P aramete r M in. N om. Max. Analog/core supply voltag e Output supply voltag e Low-level input voltage for PWRDWN pin High-level input voltage for PWRDWN pin. 7 DQ +0. D 3 High-level output voltag e. 8 Q Low-level output voltag e Input differential-pair crossing voltag e ( / 2) 0. 2 ( Q/2) Units OX Output differential-pair crossing voltage at the DRAM clock inpu t ( / 2) 0. 2 ( Q/2) IN ID Input voltage leve l 0. 3 DQ +0. D 3 Input differential voltage between CK and CK 0.36 DQ +0. D 6 OD Output differential and voltage between Y[n] and Y[n] and 0.70 DQ +0. D 6 T A Operating free air temperatur e 0 70 C 4

5 Electrical Characteristics Parameter Test Condition s A, D DQ M in. T yp. Max. Units IK All input s I I = 8mA OH High output voltag e I OH I OH = 00μA 2.3 to 2.7 Q 0. = 4mA OL Low output voltag e I OL I OL = 00μA 2.3 to = 4mA I I IQ CK, I = or PWRDWN I = or Dynamic supply current of Static supply current = 2.7 () 2.7 ± 0 μa 300 ma CK & CK <20 MHz or ( 2) 00 μa PWRDWN = Low IA Dynamic supply current of A Static supply current = 2.7 () 2 ma CK & CK <20 MHz or ( 2) 00 μa PWRDWN = Low C I CK and CK and I = or pf Notes:. Driving 9 or 8 R SDRAM memory chips with 20-ohm termination resistor for each clock output pair at 34 MHz. 2. The maximum power down clock frequency is below 20 MHz. 5

6 AC Specifications Switching characteristics over recommended operating free-air temperature range (unless otherwise noted) Parameter tjit(cc) t( θ) tsk(o) tjit(per) tjit(hper) tsl(i) tsl(o) Descriptio n Diagram A, M in. Nom. = 2.5 ±0.2 Max Cycle-to-cycle jitte r see Figure S tatic phase offse t ) ( ee Figure 4 s Output clock skew see Figure 5 00 Period jitte r see Figure Half-period jitte r see Figure I nput clock slew rate 2) O utput clock slew rate 2) ( ee Figure 8 ( ee Figure 8 s s Units ps /ns T he PLL on PI6C857 meets the above parameters while supporting SSC synthesizers with the following parameters 3) SSC modulation frequency khz SSC clock input frequency deviation % PLL loop bandwidth 2 MHz Phase angle 0.03 degrees Notes:. Static Phase offset does not include Jitter. 2. The slew rate is determined from the IBIS model and not from the test load. 3. The SSC requirements meet the Intel PC00 SDRAM Registered DIMM specification. (. 6

7 /2 PI6C857 Figure. Output Load /2 C = 4pF /2 C = 4pF /2 PI6C857 SCOPE /2 Figure 2. Output Load Test Circuit 7

8 Yx, Yx, tcycle n tcycle n+ t jit(cc) = t cycle n - t cycle n+ Figure 3. Cycle-to-Cycle Jitter CK CK t ( ) n t ( ) n+ n=n t = N t ( ) n (N is a large number of samples) Figure 4. Static Phase Offset Yx Yx t sk(o) Figure 5. Output Skew 8

9 t cycle n f O t jit(per) = t cycle n f O Figure 6. Period Jitter t half period n t n+ half period f O t jit(hper) = t half period n 2*f O Figure 7. Half-Period Jitter 80% 80% ID Clock Inputs and Outputs 20% t sl(i), t sl(o) t sl(i), t sl(o) 20% Figure 8. Input and Output Slew Rates 9

10 Packaging Mechanical: 48-Pin TSSOP (A) 48 DOCUMENT CONTROL NO. PD See Note 4 REISION: G DATE: 03/09/ See Note Max SEATING PLANE X.XX X.XX DENOTES DIMENSIONS IN MILLIMETERS.097 BSC BSC 8. Note:. Controlling dimensions in millimeters. 2. Ref: JEDEC MO-53F/ED 3. Dimension does not include mold ash, protrusions or gate burrs. Mold ash, protrusions and gate burrs shall not exceed 0.5mm per side. 4. Dimension does not include interlead ash or protrusion. Interlead ash or protrusion shall not exceed 0.25mm per side. Pericom Semiconductor Corporation 3545 N. st Street, San Jose, CA DESCRIPTION: 48-Pin 240-Mil Wide TSSOP PACKAGE CODE: A Ordering Information Ordering Code Package Code Package Type PI6C857AE A Pb-free & Green, 48-pin, 240-mil wide TSSOP Pericom Semiconductor Corporation