ICS95V V Wide Range Frequency Clock Driver (45MHz - 233MHz) Pin Configuration. Block Diagram. Functionality. Integrated Circuit Systems, Inc.

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1 Integrated Circuit Systems, Inc. ICS95V V Wide Range Frequency Clock river (45MHz - 233MHz) Recommended Application: R Memory Modules / Zero elay Board Fan Out Provides complete R registered IMM solution with ICSSSTVF6857, ICSSSTVF6859 or ICSSSTV32852 Product escription/features: Low skew, low jitter PLL clock driver to 0 differential clock distribution (SSTL_2) Feedback pins for input to output synchronization P# for power management Spread Spectrum-tolerant inputs Auto P when input signal removed Specifications: Meets PC3200 Class A+ specification for R-I 400 support Covers all RI speed grades Switching Characteristics: CYCLE - CYCLE jitter: <50ps OUTPUT - OUTPUT skew: <40ps Period jitter: ±30ps CLKC0 CLKT0 CLKT CLKC CLKC2 CLKT2 CLK_IT CLK_IC A A CLKC3 CLKT3 CLKT4 CLKC4 Pin Configuration ICS95V CLKC5 CLKT5 CLKT6 CLKC6 CLKC7 CLKT7 P# FB_IT FB_IC FB_OUTC FB_OUTT CLKC8 CLKT8 CLKT9 CLKC9 48-Pin TSSOP/TVSOP 6.0 mm Body, 0.50 mm Pitch = TSSOP 4.40 mm Body, 0.40 mm Pitch = TVSOP Block iagram FB_OUTT FB_OUTC Functionality A P# IPUTS CLK_IT CLK_IC CLKT CLKC OUTPUTS FB_OUTT FB_OUTC PLL State P# Control Logic CLKT0 CLKC0 CLKT CLKC CLKT2 CLKC2 H L H L H L H Bypassed/off H H L H L H L Bypassed/off 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) 2.5V (nom) L L H Z Z Z Z off L H L Z Z Z Z off H L H L H L H on H H L H L H L on ( ) < 20MHz) of Z Z Z Z f FB_IT FB_IC CLK_IC CLK_IT PLL CLKT3 CLKC3 CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9

2 Pin Configuration A B C E F G H J K Ball BGA Top View A CLKT0 CLKC0 CLKC5 CLKT5 B CLKC CLKT CLKT6 CLKC6 C C C CLKT2 CLKC2 C C CLKC7 CLKT7 E B B P# F CLK_IT CLK_IC B B FB_IC FB_IT G A C C FB_OUTC H A C C FB_OUTT J CLKC3 CLKT3 CLKT8 CLKC8 K CLKT4 CLKC4 CLKC9 CLKT9 CLKC CLKT CLKT0 CLKC0 CLKC5 CLKT5 CLKT6 CLKC CLKC2 CLKT2 CLK_IT CLK_IC A A 0 ICS95V CLKC7 CLKT7 P# FB_IT FB_IC FB_OUTC FB_OUTT 20 CLKC3 CLKT3 CLKT4 CLKC4 CLKC9 CLKT9 CLKT8 CLKC8 40-Pin MLF 2

3 Pin escriptions PI AME TYPE ESCRIPTIO A A CLKT(9:0) CLKC(9:0) CLK_IC CLK_IT FB_OUTC FB_OUTT FB_IT FB_IC P# PWR PWR PWR PWR OUT OUT I I OUT OUT I I I Power supply, 2.5V Ground Analog power supply, 2.5V Analog ground "True" Clock of differential pair outputs "Complementary" clocks of differential pair outputs "Complementary" reference clock input "True" reference clock input "Complementary" Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_IC "True" " Feedback output, dedicated for external feedback. It switches at the same frequency as the CLK. This output must be wired to FB_IT "True" Feedback input, provides feedback signal to the internal PLL for synchronization with CLK_IT to eliminate phase error "Complementary" Feedback input, provides signal to the internal PLL for synchronization with CLK_IC to eliminate phase error Power own. LVCMOS input This PLL Clock Buffer is designed for a V of 2.5V, an AV of 2.5V and differential data input and output levels. The ICS95V857 is a zero delay buffer that distributes a differential clock input pair (CLK_IC, CLK_IT) to ten differential pair of clock outputs (CLKT[0:9], CLKC[0:9]) and one differential pair feedback clock output (FB_OUT, FB_OUTC). The clock outputs are controlled by the input clocks (CLK_IC, CLK_IT), the feedback clocks (FB_IT, FB_IC), the 2.5-V LVCMOS input (P#) and the Analog Power input (AV ). When input (P#) is low while power is applied, the receivers are disabled, the PLL is turned off and the differential clock outputs are tri-stated. When AV is grounded, the PLL is turned off and bypassed for test purposes. When the input frequency is less than the operating frequency of the PLL, appproximately 20MHz, the device will enter a low power mode. An input frequency detection circuit on the differential inputs, independent from the input buffers, will detect the low frequency condition and perform the same low power features as when the (P#) input is low. When the input frequency increases to greater than approximately 20 MHz, the PLL will be turned back on, the inputs and outputs will be enabled and PLL will obtain phase lock between the feedback clock pair (FB_IT, FB_IC) and the input clock pair (CLK_IC, CLK_IT). The PLL to the ICS95V857 clock driver uses the input clocks (CLK_IC, CLK_IT) and the feedback clocks (FB_IT, FB_IC) provide high-performance, low-skew, low-jitter, output differential clocks (CLKT[0:9], CLKC[0:9]). The ICS95V857 is also able to track Spread Spectrum Clock (SSC) for reduced EMI. The ICS95V857 is characterized for operation from 0 C to 85 C, and will meet JEEC Standard 82- and 82-A Class A+ for registered R clock drivers. 3

4 Absolute Maximum Ratings Supply Voltage ( & A) V to 4.6V Logic Inputs V to V V Ambient Operating Temperature C to +85 C Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output Parameters T A = 0-85 C; Supply Voltage A, V = 2.5V ± 0.2V PARAMETER SYMBOL COITIOS MI TYP MA UITS Input High Current I IH V I = V or 5 µa Input Low Current I IL V I = V or 5 µa Operating Supply I 2.5 C L = 200MHz ma Current I P C L = 0pf 00 µa Output High Current I OH V = 2.3V, V OUT = V ma Output Low Current I OL V = 2.3V, V OUT =.2V ma High Impedance Output Current I OZ V =2.7V, Vout=V or ±0 ma Input Clamp Voltage V IK V Q = 2.3V Iin = -8mA -.2 V V = min to max, V Q - 0. V High-level output I OH = - ma V voltage OH V Q = 2.3V,.7 V I OH = -2 ma Low-level output voltage V OL V = min to max I OL = ma 0. V V Q = 2.3V I OH =2 ma 0.6 V Input Capacitance C I V I = or V 3 pf Output Capacitance C OUT V OUT = or V 3 pf Guaranteed by design at 220MHz, not 00% tested in production. 4

5 Recommended Operating Condition (see note) T A = 0-85 C; Supply Voltage A, = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL COITIOS MI TYP MA UITS Supply Voltage V, A V Low level input voltage High level input voltage C input signal voltage (note 2) ifferential input signal voltage (note 3) Output differential crossvoltage (note 4) Input differential crossvoltage (note 4) High level output current CLKT, CLKC, FB_IC 0.4 V /2-0.8 V P# V CLKT, CLKC, FB_IC V / V P#.7 V V V I -0.3 V V C - CLKT, FB_IT 0.36 V V AC - CLKT, FB_IT 0.7 V V V O V /2-0.5 V / V V I V /2-0.2 V /2 V / V I OH -6.4 ma Low level output current I OL 5.5 ma Operating free-air temperature V IL V IH V I T A 0 85 C otes:. Unused inputs must be held high or low to prevent them from floating. 2. C input signal voltage specifies the allowable C execution of differential input. 3. ifferential inputs signal voltages specifies the differential voltage [VTR-VCP] required for switching, where VT is the true input level and VCP is the complementary input level. 4. ifferential cross-point voltage is expected to track variations of V and is the voltage at which the differential signal must be crossing. 5

6 Timing Requirements T A = 0-85 C; Supply Voltage A, V = 2.5 V +/- 0.2V (unless otherwise stated) PARAMETER SYMBOL COITIOS MI MA UITS Max clock frequency freq op 25 o C MHz Application Frequency freq App Range 25 o C MHz Input clock duty cycle d tin % CLK stabilization T STAB 5 µs Switching Characteristics (see note 3) PARAMETER SYMBOL COITIO MI TYP MA UITS Low-to high level propagation delay time t PLH CLK_I to any output 3.5 ns High-to low level propagation delay time t PLL CLK_I to any output 3.5 ns Output enable time t E P# to any output 3 ns Output disable time tdis P# to any output 3 ns Period jitter T jit (per) 00MHz to 200MHz ps Half-period jitter t(jit_hper) 00MHz to 200MHz ps Input clock slew rate t sl(i) 4 V/ns Output clock slew rate t sl(o) 2 V/ns Cycle to Cycle Jitter T cyc -T cyc 00MHz to 200MHz ps Static Phase Offset 4 t (static phase offset) ps Output to Output Skew T skew 40 ps otes:. Refers to transition on noninverting output in PLL bypass mode. 2. While the pulse skew is almost constant over frequency, the duty cycle error increases at higher frequencies. This is due to the formula: duty cycle=t wh /t c, where the cycle (t c ) decreases as the frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. 6

7 Parameter Measurement Information V V(CLKC) R=60Ω R=60Ω /2 V(CLKC) ICS95V857 Figure. IBIS Model Output Load V /2 ICS95V857 C=4pF-V /2 SCOPE Z=60Ω R=0Ω Z=50Ω Z=60Ω R=0Ω Z=50Ω V(TT) R=50Ω C=4pF V(TT) R=50Ω -V /2 -V /2 OTE: V(TT) = Figure 2. Output Load Test Circuit Y, FB_OUTC Y, FB_OUTT tc(n) tc(n+) tjit(cc) =tc(n) ±tc(n+) Figure 3. Cycle-to-Cycle Jitter 7

8 Parameter Measurement Information CLK_IC CLK_IT FB_IC FB_IT t ( ) n n= t ( ) n t ( ) = ( is a large number of samples) Figure 4. Static Phase Offset t ( ) n+ Y # Y Y, FB_OUTC Y, FB_OUTT t (SK_O) Figure 5. Output Skew Y, FB_OUTC Y, FB_OUTT Y, FB_OUTC Y, FB_OUTT f O t (jit_per) = tc(n) - f O Figure 6. Period Jitter 8

9 Parameter Measurement Information Y, FB_OUTC Y, FB_OUTT t (hper_n) t(hper_n+) fo t (jit_hper) = t (jit_hper_n) - 2xf O Figure 7. Half-Period Jitter 80% 80% VI, VO Clock Inputs and Outputs 20% 20% Rise t sl Fall t sl Figure 8. Input and Output Slew Rates 9

10 IE AREA A2 e 2 b E E A A c -C- - SEATIG PLAE aaa C L In Millimeters In Inches SYMBOL COMMO IMESIOS COMMO IMESIOS MI MA MI MA A A A b c E SEE VARIATIOS 8.0 BASIC SEE VARIATIOS 0.39 BASIC E e 0.50 BASIC BASIC L SEE VARIATIOS SEE VARIATIOS a aaa VARIATIOS mm. (inch) MI MA MI MA Reference oc.: JEEC Publication 95, MO mm. Body, 0.50 mm. pitch TSSOP (240 mil) (0.020 mil) Ordering Information y G (LF) T esignation for tape and reel packaging Lead Free (Optional) Package Type G = TSSOP Revision esignator (will not correlate with datasheet revision) evice Type Example: 95V857AGLFT 0

11 IE AREA A2 e 2 b E E A A c -C- C - SEATIG PLAE aaa C α L In Millimeters In Inches SYMBOL COMMO IMESIOS COMMO IMESIOS MI MA MI MA A A A b c E SEE VARIATIOS 6.40 BASIC SEE VARIATIOS BASIC E e 0.40 BASIC 0.06 BASIC L SEE VARIATIOS SEE VARIATIOS a aaa VARIATIOS mm. (inch) MI MA MI MA Reference oc.: JEEC Publication 95, MO mm. Body, 0.40 mm. pitch TSSOP (73 mil) (6 mil) Ordering Information y L (LF) T esignation for tape and reel packaging Lead Free (Optional) Package Type L = TSSOP (TVSOP) Revision esignator (will not correlate with datasheet revision) evice Type Example: 95V857ALLFT

12 Index Area 2 E Top View Seating Plane Anvil Singulation or A Sawn Singulation A3 L E2 E2 2 (-)x e (Ref.) (Ref.) & E Even 2 e (Typ.) 2 If & E are Even (E -)x e (Ref.) b A 0.08 C e (Ref.) & E Odd C Thermal Base THERMALLY EHACE, VERY THI, FIE PITCH QUA FLAT / O LEA PLASTIC PACKAGE ALL IMESIOS I MILLIMETERS 40 SYMBOL MI. MA. 0 A E 0 A x E BASIC 6.00 x 6.00 A Reference 2 MI. / MA / 3.05 b E2 MI. / MA / 3.05 e 0.50 BASIC L MI. / MA / 0.50 Ordering Information Source Reference: MLF2 SE y K (LF) T esignation for tape and reel packaging Lead Free (Optional) Package Type K = MLF Revision esignator (will not correlate with datasheet revision) evice Type Example: 95V857AKLFT 2

13 A Seating Plane C T b REF umeric esignations for Horizontal Grid A B C Alpha esignations for Vertical Grid (Letters I, O, Q & S not used) d TYP TOP VIEW - e - TYP E h TYP 0.2 C c REF E - e - TYP ALL IMESIOS I MILLIMETERS BALL GRI Max. REF. IMESIOS E T e HORIZ VERT TOTAL d h E b c Min/Max Min/Max Min/Max 7.00 Bsc 4.50 Bsc 0.86/ Bsc / / Bsc 3.25 Bsc ** ote: Ball grid total indicates maximum ball count for package. Lesser quantity may be used. * Source Ref.: JEEC Publication 95, MO-205*, MO-225** Ordering Information y H (LF) T esignation for tape and reel packaging Lead Free (Optional) Package Type H = BGA Revision esignator (will not correlate with datasheet revision) evice Type Example: 95V857AHLFT 3

ICS95V850. DDR Phase Lock Loop Clock Driver (60MHz - 210MHz) Integrated Circuit Systems, Inc. Pin Configuration. Block Diagram.

ICS95V850. DDR Phase Lock Loop Clock Driver (60MHz - 210MHz) Integrated Circuit Systems, Inc. Pin Configuration. Block Diagram. Integrated Circuit Systems, Inc. ICS95V850 DDR hase Lock Loop Clock Driver (60MHz - 20MHz) Recommended Application: DDR Clock Driver roduct Description/Features: Low skew, low jitter LL clock driver Feedback