OE CLKC CLKT PL PL PL PL602-39
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1 PL602-3x XIN VDD / * SEL0^ / VDD* SEL^ FEATURES Selectable 750kHz to 800MHz range. Low phase noise output -27dBc/Hz for 0kHz offset -5dBc/Hz for 0kHz offset LVCMOS (PL602-37), LVPECL (PL and PL602-38) or LVDS (PL602-39) output. 2MHz to 25MHz crystal input. No external crystal load capacitors required. Output Enable selector. Selectable /6 to x32 frequency divider/multiplier. 3.3V operation. Available in 6-Pin TSSOP or 6-pin 3x3mm QFN GREEN/RoHS compliant packages. PIN CONFIGURATION (Top View) VDD XIN X SEL3^ SEL2^ OE TSSOP-6L 9 SEL0^ SEL^ CLKC VDD CLKT DESCRIPTION The PL (LVPECL with inverted OE), PL (LVCMOS), PL (LVPECL), and PL (LVDS) are high performance and low phase noise XO IC chips. They provide phase noise performance as low as 27dBc at 0kHz offset (at 55MHz), by multiplying the input crystal frequency up to 32x. The very low jitter makes them ideal for a wide range of applications, including SONET/SDH and FEC. They accept fundamental parallel resonant mode crystals from 2MHz to 25MHz. X SEL3^ SEL2^ OE PL602-3x CLKC VDD CLKT BLOCK DIAGRAM SEL[3:0] XIN X Oscillator Amplifier w/ integrated load cap. PLL (Phase Locked Loop) PLL by-pass PL602-3x OE CLKC CLKT ^: Internal pull -up *: On QFN package, PL /-38 do not have SEL0 available: Pin 0 is VDD, pin is. However, PL602-37/-39 have SEL0 (pin 0), and pin is VDD. See pin assignment table for d etails. Note: On QFN package there is a large center pad for thermal relief. This pad needs to be connected to. PUT ENABLE LOGICAL LEVELS Part # OE State PL PL PL PL QFN-6L 0 (Default) Output enabled Tri-state 0 Tri-state (Default) Output enabled OE input: Logical states defined by LVPECL levels for PL Logical states defined by LVCMOS levels for PL602-37/ -39 Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page
2 FREQUENCY SELECTION TABLE SEL3 SEL2 SEL SEL0 Selected Multiplier 0 0 Fin x Fin / 8 0 Fin x Fin / Fin / 6 0 Fin x Fin / 4 0 Fin x 8 0 Fin x 6 No multiplication Note: SEL0 is not available (always ) for PL and PL in 3x3mm package PIN DESCRIPTIONS PL and PL (see next page for PL602-37/-39) Name TSSOP Pin number 3x3mm QFN Pin number Type Description XIN 2 2 I Crystal input (See Crystal Specification on page 4) X 3 3 I Crystal output (See Crystal Specification on page 4 ) OE 6 6 I Output enable pin (See OE logic state table on page ) 7,8,9,0,4,2,3,4,8, P Ground connection CLKT 5 O LVPECL True output CLKC 3 7 O LVPECL Complementary output SEL0 6 Not available I SEL 5 9 I SEL2 5 5 I SEL3 4 4 I VDD, 2 6,0 P +3.3V power supply. Multiplier selector pins. These pins have an internal pullup that will default SEL to when not connected to. Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 2
3 PIN DESCRIPTIONS PL602-37/-39 (see previous page for PL602-35/-38) Name TSSOP Pin number 3x3mm QFN Pin number Type Description XIN 2 2 I Crystal input. See Crystal Specification on page 4. X 3 3 I Crystal output. See Crystal Specification on page 4. OE 6 6 I Output enable pin (see OE logic state table on page ). 7,8,9,0,4,2,3,4,8 P Ground. CLKT 5 O CLKC 3 7 O SEL0 6 0 I SEL 5 9 I SEL2 5 5 I SEL3 4 4 I LVDS True output for PL No Connect for PL VDD, 2 6, P +3.3V power supply. LVDS Complementary output for PL LVCMOS out for PL Multiplier selector pins. These pins have an internal pull-up that will default SELx to when not connected to. Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 3
4 ELECTRICAL SPECIFICATIONS. Absolute Maximum Ratings PARAMETERS SYMBOL MIN. MAX. UNITS Supply Voltage V DD 4.6 V Input Voltage, dc V I -0.5 V DD +0.5 V Output Voltage, dc V O -0.5 V DD +0.5 V Storage Temperature T S C Ambient Operating Temperature* T A C Junction Temperature T J 25 C Lead Temperature (soldering, 0s) 260 C ESD Protection, Human Body Model 2.5 kv Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only. 2. Crystal Specifications Crystal Resonator Frequency F XIN Parallel Fundamental Mode 2 25 MHz Crystal Loading Rating C L (x ta l) 20 pf Recommended ESR R E AT cut 30 Ω 3. General Electrical Specifications Supply Current, Dynamic (with Loaded Outputs) Operating Voltage Output Clock Duty Cycle Short Circuit Current I DD LVPECL/LVDS/ LVCMOS F <24MHz 60/28/5 24MHz< F O UT <96MHz 65/45/30 96MHz< F O UT <800MHz 00/80/40 V DD % V DD V DD.3V (LVPECL) ma % ma Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 4
5 4. Jitter Specifications PARAMETERS CONDITIONS FREQUENCY MIN. TYP. MAX. UNITS Period Jitter, RMS Period Jitter, Peak-to-Peak Integrated Jitter, RMS 5. Phase Noise Specifications With capacitive decoupling between V DD and. Over 0,000 cycles. With capacitive decoupling between V DD and. Over 0,000 cycles. Integrated 2 khz to 20 MHz 55.52MHz MHz MHz MHz MHz MHz 2.5 @00kHz UNITS Phase Noise, relative to carrier (typical) 55.52MHz MHz ps ps ps dbc/hz 6. LVCMOS Electrical Characteristics I OH V OH = V DD -0.4V, V DD =3.3V 0 ma Output drive current I OL V OL = 0.4V, V DD = 3.3V 0 ma Output Clock Rise/Fall Time 0.3V ~ 3.0V with 5 pf load 2.4 ns Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 5
6 7. LVDS Electrical Characteristics Output Differential Voltage V OD mv V DD Magnitude Change V OD mv Output High Voltage V OH R L = 00Ω.4.6 V Output Low Voltage V OL (see figure) 0.9. V Offset Voltage V OS V Offset Magnitude Change V OS mv Power-off Leakage I O XD V ou t = V DD or V DD = 0V 0 ua Output Short Circuit Current I O SD ma 8. LVDS Switching Characteristics Differential Clock Rise Time t r R L = 00Ω ns C L = 0 pf Differential Clock Fall Time t f (see figure) ns LVDS Levels Test Circuit LVDS Switching Test Circuit 50 C L = 0pF V OD V OS V DIFF R L = C L = 0pF LVDS Transistion Time Waveform 0V (Differential) 80% 80% V DIFF 0V 20% 20% t R t F Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 6
7 9. LVPECL Electrical Characteristics PARAMETERS SYMBOL CONDITIONS MIN. MAX. UNITS Output High Voltage V OH R L = 50Ω to (V DD 2V) V DD.025 V Output Low Voltage V OL (see figure) V DD.620 V 0. LVPECL Switching Characteristics Clock Rise Time t r ns 20%~80% of Waveform Clock Fall Time t f ns LVPECL Levels Test Circuit LVPECL Output Skew VDD 50? 2.0V 50% 50? tskew LVPECL Transistion Time Waveform DUTY CYCLE 45-55% 55-45% 80% 50% 20% tr tf Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 7
8 E DED PACKAGE INFORMATION (GREEN PACKAGE COMPLIANT) TSSOP-6L Symbol Dimension in MM Min. Max. A -.20 A b C D D E H L e 0.65 BSC A C E H A e B L QFN-6L e DDD Symbol Dimension (mm) Min Nom Max D L A A A b D b Pin Dot E D A E L e 0.50BSC SEATING PLANE A3 A Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 8
9 ORDERING INFORMATION For part ordering, please contact our Sales D epartment: 280 Fortune Drive, San Jose, CA 953, USA Tel: (408) Fax: (408) PART NUMBER The order number for this device is a combination of the following: Part number, Package type, Operating temperature range, shipping method PL602-3x X X - X Part Number None=Tube R=Tape & Reel Package Type O=TSSOP-6L Q=QFN-6L Temperature C=Commercial (0 C to 70 C) Part/Order Number Marking Package Option PL602-35OC P OC PL602-35OC-R LLLLL P602 PL602-35QC-R 35 LLL PL602-37OC P OC PL602-37OC-R LLLLL P602 PL602-37QC-R 37 LLL PL602-38OC P OC PL602-38OC-R LLLLL P602 PL602-38QC-R 38 LLL PL602-39OC P OC PL602-39OC-R LLLLL P602 PL602-39QC-R 39 LLL *Note: LLL and LLLLL designates lot number 6-Pin TSSOP Tube 6-Pin TSSOP (Tape and Reel) 6-Pin 3 3 QFN (Tape and Reel) 6-Pin TSSOP Tube 6-Pin TSSOP (Tape and Reel) 6-Pin 3 3 QFN (Tape and Reel) 6-Pin TSSOP Tube 6-Pin TSSOP (Tape and Reel) 6-Pin 3 3 QFN (Tape and Reel) 6-Pin TSSOP Tube 6-Pin TSSOP (Tape and Reel) 6-Pin 3 3 QFN (Tape and Reel) Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax +(408) Rev 03/07/202 Page 9
10 Micrel Inc., reserves the right to make changes in its products or specifications, or both at any time without notice. The in formation furnished by Micrel is believed to be accurate and reliable. However, Micrel makes no guara ntee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: Micrel s products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of Micrel Inc. Micrel Inc. 280 Fortune Drive San Jose, CA 953 USA tel +(408) fax + (408) Rev 03 /07/202 Page 0
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DSC55703 General Description The DSC55703 is a crystalless, two output PCI express clock generator meeting Gen1, Gen2, and Gen3 specifications. The clock generator uses proven silicon MEMS technology to
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-01 Description The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks
MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET
DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low
SY89871U. General Description. Features. Typical Performance. Applications
2.5GHz Any Diff. In-To-LVPECL Programmable Clock Divider/Fanout Buffer w/ Internal Termination General Description The is a 2.5V/3.3V LVPECL output precision clock divider capable of accepting a high-speed
DSC400. Configurable Four Output, Low Jitter Crystal-less Clock Generator. General Description. Block Diagram. Applications.
DSC400 Configurable Four Output, Low Jitter Crystalless Clock Generator General Description The DSC400 is a four output crystalless clock generator. It utilizes Micrel s proven PureSilicon MEMS technology
ULTRA PRECISION 4 4 CML SWITCH WITH INTERNAL I/O TERMINATION
ULTRA PRECISION 4 4 CML SWITCH WITH INTERNAL I/O TERMINATION Precision Edge FEATURES Provides crosspoint switching between any input pair to any output pair Ultra-low jitter design: 67fs RMS phase jitter
HIGH FREQUENCY, LOW JITTER CLOCK OSCILLATOR
DESCRIPTION FEATURES + The XCO clock series is a cutting edge family of low to high frequency, low jitter output, single or multi - frequency clock oscillators. The XCO clocks are available in 7.0 x 5.0,
NOT RECOMMENDED FOR NEW DESIGNS
NOT RECOMMENDED FOR NEW DESIGNS ULTRA PRECISION 8:1 MUX WITH INTERNAL TERMINATION AND 1:2 400mV LVPECL FANOUT BUFFER FEATURES - Selects between 1 of 8 inputs, and provides 2 precision, low skew LVPECL
TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features
DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency
Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:2 Oscillator Fanout Buffer Revision 2.0 General Description The is an advanced oscillator fanout buffer design for high performance, low-power, small form-factor
ICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs
ICS HIGH PERFORMANCE VCXO. Features. Description. Block Diagram DATASHEET
DATASHEET ICS3726-02 Description The ICS3726-02 is a low cost, low-jitter, high-performance designed to replace expensive discrete s modules. The ICS3726-02 offers a wid operating frequency range and high
Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
Revision 1.1 General Description The series is a low-power, small form-factor, high-performance OTP-based device and a member of Micrel s JitterBlocker, factory programmable jitter attenuators. The JitterBlocker
XCO FAST TURNAROUND CLOCK OSCILLATOR HIGH FREQUENCY, LOW JITTER CLOCK OSCILLATOR FEATURES + DESCRIPTION SELECTOR GUIDE LVCMOS LVDS LVPECL
XCO FAST TURNAROUND DESCRIPTION FEATURES + The XCO clock series is a cutting edge family of low to high frequency, low jitter output, single or multi - frequency clock oscillators. The XCO clocks are available
Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)
2.5V Low Jitter, Low Skew 1:12 LVDS Fanout Buffer with 2:1 Input MUX and Internal Termination General Description The is a 2.5V low jitter, low skew, 1:12 LVDS fanout buffer optimized for precision telecom
3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX
3.3V/5V 2.5GHz PECL/ECL 1:4 FANOUT BUFFER WITH 2:1 INPUT MUX FEATURES High-speed 1:4 PECL/ECL fanout buffer 2:1 multiplexer input Guaranteed AC parameters over temp/voltage: > 2.5GHz f MAX (toggle) < 225ps
High Performance MEMS Jitter Attenuator
Moisture Sensitivity Level: MSL=1 FEATURES: APPLICATIONS: Low power and miniature package programmable jitter attenuator 1/10/40/100 Gigabiy Ethernet (GbE) Input frequency up to 200MHz SONET/SDH Output
SERIALLY PROGRAMMABLE CLOCK SOURCE. Features
DATASHEET ICS307-02 Description The ICS307-02 is a versatile serially programmable clock source which takes up very little board space. It can generate any frequency from 6 to 200 MHz and have a second
ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET
PRELIMINARY DATASHEET ICS1493-17 Description The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device
Features. Applications. Markets
1.5GHz Precision, LVPECL 1:5 Fanout with 2:1 MUX and Fail Safe Input with Internal Termination Precision Edge General Description The is a 2.5/3.3V, 1:5 LVPECL fanout buffer with a 2:1 differential input
ICS650-40A ETHERNET SWITCH CLOCK SOURCE. Description. Features. Block Diagram DATASHEET
DTSHEET ICS650-40 Description The ICS650-40 is a clock chip designed for use as a core clock in Ethernet Switch applications. Using IDT s patented Phase-Locked Loop (PLL) techniques, the device takes a
MK2703 PLL AUDIO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET
DATASHEET MK2703 Description The MK2703 is a low-cost, low-jitter, high-performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using IDT
Low-Jitter Precision LVPECL Oscillator
DSC0 General Description The DSC0 & series of high performance oscillators utilizes a proven silicon MEMS technology to provide excellent jitter and stability over a wide range of supply voltages and temperatures.
ICS HDTV AUDIO/VIDEO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET
DATASHEET ICS662-03 Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior
ICS501 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS501 Description The ICS501 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands
ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA
BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part
Features VDD. PLL Clock Synthesis and Spread Spectrum Circuitry GND
DATASHEET ICS7151 Description The ICS7151-10, -20, -40, and -50 are clock generators for EMI (Electro Magnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux
2.5V/3.3V 500MHz Low Skew 1-to-10 Differential to LVPECL Fanout Buffer with 2 to 1 Differential Clock Input Mux Features F MAX = 500MHz 10 pairs of differential LVPECL outputs Low additive jitter,
6GHz, 1:6 CML FANOUT BUFFER WITH 2:1 MUX INPUT AND INTERNAL I/O TERMINATION
6GHz, 1:6 CML FANOUT BUFFER WITH 2:1 MUX PUT AND TERNAL I/O TERMATION Precision Edge FEATURES Provides six ultra-low skew copies of the selected input 2:1 MUX input included for clock switchover applications
ICS553 LOW SKEW 1 TO 4 CLOCK BUFFER. Description. Features. Block Diagram DATASHEET
DATASHEET ICS553 Description The ICS553 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest skew, small clock buffer. See the ICS552-02 for
PI6C557-03B. PCIe 3.0 Clock Generator with 2 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TSSOP) Block Diagram
Features ÎÎPCIe 3.0 compliant à à PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V
FemtoClock Crystal-to-LVDS Clock Generator ICS DATA SHEET. Features. General Description. Pin Assignment. Block Diagram
FemtoClock Crystal-to-LVDS Clock Generator ICS844011 DATA SHEET General Description The ICS844011 is a Fibre Channel Clock Generator. The ICS844011 uses an 18pF parallel resonant crystal. For Fibre Channel
SY58608U. General Description. Features. Functional Block Diagram
3.2Gbps Precision, 1:2 LVDS Fanout Buffer with Internal Termination and Fail Safe Input General Description The is a 2.5V, high-speed, fully differential 1:2 LVDS fanout buffer optimized to provide two
Features. Applications. Markets
Precision LVPECL Runt Pulse Eliminator 2:1 MUX with 1:2 Fanout and Internal Termination General Description The is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source
DSC2042. Low-Jitter Configurable HCSL-LVPECL Oscillator. General Description. Features. Block Diagram. Applications
LowJitter Configurable HCSLLVPECL Oscillator General Description The DSC2042 series of high performance dual output oscillators utilize a proven silicon MEMS technology to provide excellent jitter and
Features. Applications. Markets
Precision LVPECL Runt Pulse Eliminator 2:1 Multiplexer General Description The is a low jitter PECL, 2:1 differential input multiplexer (MUX) optimized for redundant source switchover applications. Unlike