DESCRIPTION CLKOUT CLK2 CLK4 CLK1 VDD GND SOP-8L

DESCRIPTION CLKA1 CLKA2 CLKA3 CLKA4 CLKB1 CLKB2 CLKB3 CLKB4

PL123-05 PL123-09 FEATURES DESCRIPTION Frequency Range 10MHz to 134 MHz Output Options: o 5 outputs PL123-05 o 9 outputs PL123-09 Zero input - output delay Optional Drive Strength: Standard (8mA) High

DESCRIPTION CLK1 CLK2 GND CLK1 CLK2 VDD CLK3 CLK4 VDD

PL123-05N PL123-09N FEATURES Output fanout buffer for DC to 134MHz Output Options: o 1:5 output fanout with PL123-05 o 1:9 output fanout with PL123-09 Low power consumption for portable applications Low

Low-Power 2.25V to 3.63V DC to 150MHz 1:6 Fanout Buffer IC DESCRIPTION

FEATURES 1:6 LVCMOS output fanout buffer for DC to 150MHz 8mA Output Drive Strength Low power consumption for portable applications Low input-output delay Output-Output skew less than 250ps Low Additive

Low-Power, 1.62V to 3.63V, 1MHz to 150MHz, 1:3 Fanout Buffer IC CLK2 VDD CLK0 SOT23-6L

FEATURES 3 LVCMOS Outputs 12mA Output Drive Strength Input/Output Frequency: o Reference Clock: 1MHz to 150MHz Supports LVCMOS or Sine Wave Input Clock Very Low Jitter and Phase Noise Low Current Consumption

Low-Power, 1.62V to 3.63V, 1MHz To 150MHz, 1:2 Fanout Buffer IC OE CLK1. DFN-6L (2.0 x 1.3 x 0.6mm) FIN CLK1

FEATURES 2 LVCMOS Outputs Input/Output Frequency: 1MHz to 150MHz Supports LVCMOS or Sine Wave Input Clock Extremely low additive Jitter 8 ma Output Drive Strength Low Current Consumption Single 1.8V, 2.5V,

PL600-27T CLK0 XIN/FIN 1. Xtal Osc CLK1 XOUT CLK2. Low Power 3 Output XO PIN ASSIGNMENT FEATURES DESCRIPTION CLK2 GND VDD FIN CLK0 SOT23-6L

FEATURES 3 LVCMOS outputs with OE tri -state control Low current consumption: o

Note: ^ Deno tes 60K Ω Pull-up resisto r. Phase Detector F VCO = F REF * (M/R) F OUT = F VCO / P

FEATURES Advanced programmable PLL with Spread Spectrum Crystal or Reference Clock input o Fundamental crystal: 10MHz to 40MHz o Reference input: 1MHz to 200MHz Accepts 0.1V reference signal input voltage

The PL is an advanced Spread Spectrum clock generator (SSCG), and a member of PicoPLL Programmable Clock family.

FEATURES Advanced programmable PLL with Spread Spectrum Reference Clock input o 1MHz to 200MHz Output Frequency o

CLK1 GND. Phase Detector F VCO = F REF * (2 * M/R) VCO. P-Counter (14-bit) F OUT = F VCO / (2 * P) Programming Logic

PL611s-19 PL611s-19 FEATURES Designed for Very Low-Power applications Input Frequency, AC Coupled: o Reference Input: 1MHz to 125MHz o Accepts >0.1V input signal voltage Output Frequency up to 125MHz LVCMOS

19MHz to 800MHz Low Phase-Noise XO PIN CONFIGURATION

PL685-XX FEATURES < 0.5ps RMS phase jitter (12kHz to 20MHz) at 622.08MHz 30ps max peak to peak period jitter Ultra Low-Power Consumption о < 90 ma @622MHz PECL output о

PL High Speed Translator Buffer to LVDS FEATURES PIN CONFIGURATION

FEATURES Differential output Single AC coupled input (min. 100mV swing). Input range from 0 to 1.0GHz. 2.5V to 3.3V operation. Available in 8-Pin SOP or 3x3mm QFN GREEN/RoHS compliant packaging. PIN CONFIGURATION

OE CLKC CLKT PL PL PL PL602-39

PL602-3x XIN VDD / * SEL0^ / VDD* SEL^ FEATURES Selectable 750kHz to 800MHz range. Low phase noise output -27dBc/Hz for 55.52MHz @ 0kHz offset -5dBc/Hz for 622.08MHz @ 0kHz offset LVCMOS (PL602-37), LVPECL

PL XIN CLK XOUT VCON. Xtal Osc. Varicap. Low Phase Noise VCXO (17MHz to 36MHz) PIN CONFIGURATION FEATURES DESCRIPTION BLOCK DIAGRAM

FEATURES PIN CONFIGURATION VCXO output for the 17MHz to 36MHz range Low phase noise (-130dBc @ 10kHz offset at 35.328MHz) LVCMOS output with OE tri-state control 17 to 36MHz fundamental crystal input Integrated

Phase Detector. Charge Pump. F out = F VCO / (4*P)

PL611-30 FEATURES Advanced programmable PLL design Very low Jitter and Phase Noise (< 40ps Pk -Pk typ.) Supports complementary LVCMOS outputs to drive LVPECL and LVDS i nputs. Output Frequencies: o < 400MHz

3.3V Zero Delay Buffer

3.3V Zero Delay Buffer Features Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations see Available Configurations table Multiple low-skew outputs 10-MHz

Phase Detector. Selectable / 1,/ 2,/4,/8. Selectable / 1,/2

Programming Logic PL611-01 FEATURES Advanced programmable PLL design Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) Up to 3 programmable outputs Output frequency up to 200MHz CMOS. Accepts Crystal

PCI-EXPRESS CLOCK SOURCE. Features

DATASHEET ICS557-01 Description The ICS557-01 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 100 MHz in a small 8-pin SOIC package.

Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

Revision 1.1 General Description The series is a low-power, small form-factor, high-performance OTP-based device and a member of Micrel s JitterBlocker, factory programmable jitter attenuators. The JitterBlocker

ICS QUAD PLL CLOCK SYNTHESIZER. Description. Features. Block Diagram PRELIMINARY DATASHEET

PRELIMINARY DATASHEET ICS348-22 Description The ICS348-22 synthesizer generates up to 9 high-quality, high-frequency clock outputs including multiple reference clocks from a low frequency crystal or clock

ICS PCI-EXPRESS CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

DATASHEET ICS557-0 Description The ICS557-0 is a clock chip designed for use in PCI-Express Cards as a clock source. It provides a pair of differential outputs at 00 MHz in a small 8-pin SOIC package.

Features. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

Low Power, 1.62V to 3.63V, 10MHz to 40MHz, 1:2 Oscillator Fanout Buffer Revision 2.0 General Description The is an advanced oscillator fanout buffer design for high performance, low-power, small form-factor

ICS OSCILLATOR, MULTIPLIER, AND BUFFER WITH 8 OUTPUTS. Description. Features (all) Features (specific) DATASHEET

DATASHEET ICS552-01 Description The ICS552-01 produces 8 low-skew copies of the multiple input clock or fundamental, parallel-mode crystal. Unlike other clock drivers, these parts do not require a separate

Low Phase Noise, LVPECL VCXO (for 150MHz to 160MHz Fundamental Crystals) FEATURES. * Internal 60KΩ pull-up resistor

0.952mm VDD QB PL586-55/-58 FEATURES DIE CONFIGURATION Advanced non multiplier VCXO Design for High Performance Crystal Oscillators Input/Output Range: 150MHz to 160MHz Phase Noise Optimized for 155.52MHz:

ICS542 CLOCK DIVIDER. Features. Description. Block Diagram DATASHEET. NOTE: EOL for non-green parts to occur on 5/13/10 per PDN U-09-01

DATASHEET ICS542 Description The ICS542 is cost effective way to produce a high-quality clock output divided from a clock input. The chip accepts a clock input up to 156 MHz at 3.3 V and produces a divide

ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

DATASHEET ICS180-51 Description The ICS180-51 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase-Locked Loop (PLL) technology

ICS HDTV AUDIO/VIDEO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET

DATASHEET ICS662-03 Description The ICS662-03 provides synchronous clock generation for audio sampling clock rates derived from an HDTV stream. The device uses the latest PLL technology to provide superior

ICS NETWORKING AND PCI CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

DATASHEET Description The is a low cost frequency generator designed to support networking and PCI applications. Using analog/digital Phase Locked-Loop (PLL) techniques, the device uses a standard fundamental

ICS LOW EMI CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

DATASHEET ICS180-01 Description The ICS180-01 generates a low EMI output clock from a clock or crystal input. The device uses IDT s proprietary mix of analog and digital Phase Locked Loop (PLL) technology

MK1413 MPEG AUDIO CLOCK SOURCE. Features. Description. Block Diagram DATASHEET

DATASHEET MK1413 Description The MK1413 is the ideal way to generate clocks for MPEG audio devices in computers. The device uses IDT s proprietary mixture of analog and digital Phase-Locked Loop (PLL)

MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET

DATASHEET MK1714-01 Description The MK1714-01 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread spectrum designed to generate high frequency clocks

MK SPREAD SPECTRUM MULTIPLIER CLOCK. Description. Features. Block Diagram DATASHEET

DATASHEET MK1714-02 Description The MK1714-02 is a low cost, high performance clock synthesizer with selectable multipliers and percentages of spread designed to generate high frequency clocks with low

ICS NETWORKING CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET

DATASHEET Description The generates four high-quality, high-frequency clock outputs. It is designed to replace multiple crystals and crystal oscillators in networking applications. Using ICS patented Phase-Locked

ICS LOW EMI CLOCK GENERATOR. Features. Description. Block Diagram DATASHEET

DATASHEET ICS10-52 Description The ICS10-52 generates a low EMI output clock from a clock or crystal input. The device uses ICS proprietary mix of analog and digital Phase-Locked Loop (PLL) technology

2 TO 4 DIFFERENTIAL CLOCK MUX ICS Features

DATASHEET 2 TO 4 DIFFERENTIAL CLOCK MUX ICS557-06 Description The ICS557-06 is a two to four differential clock mux designed for use in PCI-Express applications. The device selects one of the two differential

Analog Frequency Multiplier

Analog Frequency Multiplier DESCRIPTION Analog Frequency Multipliers TM (AFMs) are the industry s first Balanced Oscillator utilizing analog multiplication of the fundamental frequency (at double or quadruple

LOW SKEW 1 TO 4 CLOCK BUFFER. Features

DATASHEET ICS651 Description The ICS651 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is a low skew, small clock buffer. IDT makes many non-pll and

ICS553 LOW SKEW 1 TO 4 CLOCK BUFFER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS553 Description The ICS553 is a low skew, single input to four output, clock buffer. Part of IDT s ClockBlocks TM family, this is our lowest skew, small clock buffer. See the ICS552-02 for

ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS670-02 Description The ICS670-02 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. Part of IDT

ICS558A-02 LVHSTL TO CMOS CLOCK DIVIDER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS558A-02 Description The ICS558A-02 accepts a high-speed LVHSTL input and provides four CMOS low skew outputs from a selectable internal divider (divide by 3, divide by 4). The four outputs

ICS2510C. 3.3V Phase-Lock Loop Clock Driver. Integrated Circuit Systems, Inc. General Description. Pin Configuration.

Integrated Circuit Systems, Inc. ICS250C 3.3V Phase-Lock Loop Clock Driver General Description The ICS250C is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology

ICS660 DIGITAL VIDEO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

DATASHEET ICS660 Description The ICS660 provides clock generation and conversion for clock rates commonly needed in digital video equipment, including rates for MPEG, NTSC, PAL, and HDTV. The ICS660 uses

TRIPLE PLL FIELD PROG. SPREAD SPECTRUM CLOCK SYNTHESIZER. Features

DATASHEET ICS280 Description The ICS280 field programmable spread spectrum clock synthesizer generates up to four high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency

MK LOW PHASE NOISE T1/E1 CLOCK GENERATOR. Features. Description. Block Diagram DATASHEET. Pullable Crystal

DATASHEET LOW PHASE NOISE T1/E1 CLOCK ENERATOR MK1581-01 Description The MK1581-01 provides synchronization and timing control for T1 and E1 based network access or multitrunk telecommunication systems.

3.3 VOLT COMMUNICATIONS CLOCK PLL MK Description. Features. Block Diagram DATASHEET

DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK PLL MK2049-45 Description The MK2049-45 is a dual Phase-Locked Loop (PLL) device which can provide frequency synthesis and jitter attenuation. The first PLL is VCXO

ICS276 TRIPLE PLL FIELD PROGRAMMABLE VCXO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS276 Description The ICS276 field programmable VCXO clock synthesizer generates up to three high-quality, high-frequency clock outputs including multiple reference clocks from a low-frequency

3.3V Zero Delay Buffer

3.3V Zero Delay Buffer Features Zero input-output propagation delay, adjustable by capacitive load on FBK input Multiple configurations, see Available CY2308 Configurations on page 3 Multiple low skew

PL565-37/38 VCXO Family

(Preliminary) Analog Frequency Multiplier PRODUCT DESCRIPTION The Analog Frequency Multiplier (AFM) is the industry s first Balanced Oscillator utilizing analog multiplication of the fundamental frequency

ICS High Performance Communication Buffer. Integrated Circuit Systems, Inc. General Description. Block Diagram.

Integrated Circuit Systems, Inc. ICS905 High Performance Communication Buffer General Description The ICS905 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology

ICS LOW PHASE NOISE ZERO DELAY BUFFER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS670-04 Description The ICS670-04 is a high speed, low phase noise, Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. It is identical

ICS571 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET

DATASHEET Description The is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques. IDT introduced

PI6C557-03B. PCIe 3.0 Clock Generator with 2 HCSL Outputs. Features. Description. Pin Configuration (16-Pin TSSOP) Block Diagram

Features ÎÎPCIe 3.0 compliant à à PCIe 3.0 Phase jitter - 0.45ps RMS (High Freq. Typ.) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal or clock input frequency ÎÎHCSL outputs, 0.8V

19MHz to 250MHz Low Phase-Noise XO PAD CONFIGURATION

FEATURES < 0.6ps RMS phase jitter (12kHz to 20MHz) at 155.52MHz 30ps max peak to peak period jitter 8bit Switch Capacitor for ±50PPM crystal CLoad tuning о Load Capacitance Tuning Range: 8pF to 12pF Ultra

PI6C557-03AQ. PCIe 2.0 Clock Generator with 2 HCSL Outputs for Automotive Applications. Description. Features. Pin Configuration (16-Pin TSSOP)

PCIe.0 Clock Generator with HCSL Outputs for Automotive Applications Features ÎÎPCIe.0 compliant à à Phase jitter -.1ps RMS (typ) ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz crystal

ICS309 SERIAL PROGRAMMABLE TRIPLE PLL SS VERSACLOCK SYNTH. Description. Features. Block Diagram DATASHEET

DATASHEET ICS309 Description The ICS309 is a versatile serially-programmable, triple PLL with spread spectrum clock source. The ICS309 can generate any frequency from 250kHz to 200 MHz, and up to 6 different

MK2705 AUDIO CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

DATASHEET MK2705 Description The MK2705 provides synchronous clock generation for audio sampling clock rates derived from an MPEG stream, or can be used as a standalone clock source with a 27 MHz crystal.

IDT9170B CLOCK SYNCHRONIZER AND MULTIPLIER. Description. Features. Block Diagram DATASHEET

DATASHEET IDT9170B Description The IDT9170B generates an output clock which is synchronized to a given continuous input clock with zero delay (±1ns at 5 V VDD). Using IDT s proprietary phase-locked loop

MK3722 VCXO PLUS AUDIO CLOCK FOR STB. Description. Features. Block Diagram DATASHEET

DATASHEET MK3722 Description The MK3722 is a low cost, low jitter, high performance VCXO and PLL clock synthesizer designed to replace expensive discrete VCXOs and multipliers. The patented on-chip Voltage

100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs

0 Features CY2280 100-MHz Pentium II Clock Synthesizer/Driver with Spread Spectrum for Mobile or Desktop PCs Mixed 2.5V and 3.3V operation Clock solution for Pentium II, and other similar processor-based

MK VCXO-BASED FRAME CLOCK FREQUENCY TRANSLATOR. Features. Description. Block Diagram DATASHEET. Pullable Crystal

DATASHEET MK2059-01 Description The MK2059-01 is a VCXO (Voltage Controlled Crystal Oscillator) based clock generator that produces common telecommunications reference frequencies. The output clock is

3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE

3.3V ZERO DELAY CLOCK BUFFER, SPREAD SPECTRUM COMPATIBLE IDT23S05 FEATURES: Phase-Lock Loop Clock Distribution 10MHz to 133MHz operating frequency Distributes one clock input to one bank of five outputs

Features. EXTERNAL PULLABLE CRYSTAL (external loop filter) FREQUENCY MULTIPLYING PLL 2

DATASHEET 3.3 VOLT COMMUNICATIONS CLOCK VCXO PLL MK2049-34A Description The MK2049-34A is a VCXO Phased Locked Loop (PLL) based clock synthesizer that accepts multiple input frequencies. With an 8 khz

Features VDD 2. 2 Clock Synthesis and Control Circuitry. Clock Buffer/ Crystal Oscillator GND

DATASHEET Description The is a low cost, low jitter, high performance clock synthesizer for networking applications. Using analog Phase-Locked Loop (PLL) techniques, the device accepts a.5 MHz or 5.00

Features VDD 1 CLK1. Output Divide PLL 2 OE0 GND VDD. IN Transition Detector CLK1 INB. Output Divide PLL 2 OE0 GND

DATASHEET ICS58-0/0 Description The ICS58-0/0 are glitch free, Phase Locked Loop (PLL) based clock multiplexers (mux) with zero delay from input to output. They each have four low skew outputs which can

PI6C PCI Express Clock. Product Features. Description. Block Diagram. Pin Configuration

Product Features ÎÎLVDS compatible outputs ÎÎSupply voltage of 3.3V ±10% ÎÎ5MHz input frequency ÎÎHCSL outputs, 0.7V Current mode differential pair ÎÎJitter 60ps cycle-to-cycle (typ) ÎÎSpread of ±0.5%,

IDT5V60014 LOW PHASE NOISE ZERO DELAY BUFFER. Description. Features. Block Diagram DATASHEET

DATASHEET IDT5V60014 Description The IDT5V60014 is a high speed, high output drive, low phase noise Zero Delay Buffer (ZDB) which integrates IDT s proprietary analog/digital Phase Locked Loop (PLL) techniques.

ICS502 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS502 Description The ICS502 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output and a reference from a lower frequency crystal or clock input. The

Features VDD. PLL Clock Synthesis and Spread Spectrum Circuitry GND

DATASHEET ICS7151 Description The ICS7151-10, -20, -40, and -50 are clock generators for EMI (Electro Magnetic Interference) reduction (see below for frequency ranges and multiplier ratios). Spectral peaks

FIELD PROGRAMMABLE DUAL OUTPUT SS VERSACLOCK SYNTHESIZER. Features VDD PLL1 PLL2 GND

DATASHEET ICS252 Description The ICS252 is a low cost, dual-output, field programmable clock synthesizer. The ICS252 can generate two output frequencies from 314 khz to 200 MHz using up to two independently

ICS LOW SKEW 2 INPUT MUX AND 1 TO 8 CLOCK BUFFER. Features. Description. Block Diagram INA INB SELA

BUFFER Description The ICS552-02 is a low skew, single-input to eightoutput clock buffer. The device offers a dual input with pin select for glitch-free switching between two clock sources. It is part

LOW PHASE NOISE CLOCK MULTIPLIER. Features

DATASHEET Description The is a low-cost, low phase noise, high performance clock synthesizer for applications which require low phase noise and low jitter. It is IDT s lowest phase noise multiplier. Using

PI6CL V/1.5V, 200MHz, 1:4 Networking Clock Buffer. Features. Description. Pin Description

Features High-speed, low-noise, non-inverting 1:4 buffer Maximum Frequency up to 200 MHz Low output skew < 100ps Low propagation delay < 3.5ns Optimized duty cycle 3.3 tolerent input 1.2 or 1.5 supply

PL V-3.3V Low-Skew 1-4 Differential PECL Fanout Buffer

-48 FEATURES Four differential 2.5V/3.3V LVPECL output pairs. Output Frequency: 1GHz. Two selectable differential input pairs. Translates any standard single-ended or differential input format to LVPECL

ICS512 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS512 Description The ICS512 is the most cost effective way to generate a high-quality, high frequency clock output and a reference clock from a lower frequency crystal or clock input. The name

Features. Applications

PCIe Octal, Ultra-Low Jitter, HCSL Frequency Synthesizer General Description The PL607081 and PL607082 are members of the PCI Express family of devices from Micrel and provide extremely low-noise spread-spectrum

(Prelim inary ) Analog Frequency Multiplier. Oscillator Amplifier

OSCOFF SEL GNDOSC VCON XIN VDDBUF QBAR Q GNDBUF (Prelim inary ) Analog Frequency Multiplier PRODUCT DESCRIPTION The Analog Frequency Multiplier (AFM) is the industry s first Balanced Oscillator utilizing

MK2703 PLL AUDIO CLOCK SYNTHESIZER. Description. Features. Block Diagram DATASHEET

DATASHEET MK2703 Description The MK2703 is a low-cost, low-jitter, high-performance PLL clock synthesizer designed to replace oscillators and PLL circuits in set-top box and multimedia systems. Using IDT

ICS511 LOCO PLL CLOCK MULTIPLIER. Description. Features. Block Diagram DATASHEET

DATASHEET ICS511 Description The ICS511 LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands

ICS663 PLL BUILDING BLOCK. Description. Features. Block Diagram DATASHEET

DATASHEET ICS663 Description The ICS663 is a low cost Phase-Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled

Distributed by: www.jameco.com 1-800-831-4242 The content and copyrights of the attached material are the property of its owner. Features Three integrated phase-locked loops Ultra-wide divide counters

3.3V ZERO DELAY CLOCK MULTIPLIER

3.3V ZERO DELAY CLOCK MULTIPLIER IDT2308 FEATURES: Phase-Lock Loop Clock Distribution for Applications ranging from 10MHz to 1 operating frequency Distributes one clock input to two banks of four outputs

ICS CLOCK MULTIPLIER AND JITTER ATTENUATOR. Description. Features. Block Diagram DATASHEET

DATASHEET ICS2059-02 Description The ICS2059-02 is a VCXO (Voltage Controlled Crystal Oscillator) based clock multiplier and jitter attenuator designed for system clock distribution applications. This

PCS2P2309/D. 3.3V 1:9 Clock Buffer. Functional Description. Features. Block Diagram

3.3V 1:9 Clock Buffer Features One-Input to Nine-Output Buffer/Driver Buffers all frequencies from DC to 133.33MHz Low power consumption for mobile applications Less than 32mA at 66.6MHz with unloaded

Spread Spectrum Frequency Timing Generator

Spread Spectrum Frequency Timing Generator Features Maximized EMI suppression using Cypress s Spread Spectrum technology Generates a spread spectrum copy of the provided input Selectable spreading characteristics

MK3727D LOW COST 24 TO 36 MHZ 3.3 VOLT VCXO. Description. Features. Block Diagram DATASHEET

DATASHEET MK3727D Description The MK3727D combines the functions of a VCXO (Voltage Controlled Crystal Oscillator) and PLL (Phase Locked Loop) frequency doubler onto a single chip. Used in conjunction

ICS650-40A ETHERNET SWITCH CLOCK SOURCE. Description. Features. Block Diagram DATASHEET

DTSHEET ICS650-40 Description The ICS650-40 is a clock chip designed for use as a core clock in Ethernet Switch applications. Using IDT s patented Phase-Locked Loop (PLL) techniques, the device takes a

ICS PLL BUILDING BLOCK

Description The ICS673-01 is a low cost, high performance Phase Locked Loop (PLL) designed for clock synthesis and synchronization. Included on the chip are the phase detector, charge pump, Voltage Controlled

SM Features. General Description. Applications. Block Diagram

ClockWorks 10GbE (156.25MHz, 312.5MHz), Ultra-Low Jitter, LVPECL Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise

High-accuracy EPROM Programmable Single-PLL Clock Generator

Features High-accuracy PLL with 12-bit multiplier and -bit divider EPROM-programmability 3.3 or 5 operation Operating frequency 390 khz 133 MHz at 5 390 khz 0 MHz at 3.3 Reference input from either a 30

LOCO PLL CLOCK MULTIPLIER. Features

DATASHEET ICS501A Description The ICS501A LOCO TM is the most cost effective way to generate a high quality, high frequency clock output from a lower frequency crystal or clock input. The name LOCO stands

ICS9112A-16. Low Skew Output Buffer. General Description. Pin Configuration. Block Diagram. 8 pin SOIC, TSSOP

Low Skew Output Buffer General Description The ICS92A-6 is a high performance, low skew, low jitter clock driver. It uses a phase lock loop (PLL) technology to align, in both phase and frequency, the REF

ICS CLOCK SYNTHESIZER FOR PORTABLE SYSTEMS. Description. Features. Block Diagram PRELIMINARY DATASHEET

PRELIMINARY DATASHEET ICS1493-17 Description The ICS1493-17 is a low-power, low-jitter clock synthesizer designed to replace multiple crystals and oscillators in portable audio/video systems. The device

LOCO PLL CLOCK MULTIPLIER. Features

DATASHEET ICS501 Description The ICS501 LOCO TM is the most cost effective way to generate a high-quality, high-frequency clock output from a lower frequency crystal or clock input. The name LOCO stands

One-PLL General Purpose Clock Generator

One-PLL General Purpose Clock Generator Features Integrated phase-locked loop Low skew, low jitter, high accuracy outputs Frequency Select Pin 3.3V Operation with 2.5 V Output Option 16-TSSOP Benefits

NB3N502/D. 14 MHz to 190 MHz PLL Clock Multiplier

4 MHz to 90 MHz PLL Clock Multiplier Description The NB3N502 is a clock multiplier device that generates a low jitter, TTL/CMOS level output clock which is a precise multiple of the external input reference

Features. Applications. Micrel Inc Fortune Drive San Jose, CA USA tel +1 (408) fax + 1 (408)

Flexible Ultra-Low Jitter Clock Synthesizer Clockworks FLEX General Description The SM802xxx series is a member of the ClockWorks family of devices from Micrel and provide an extremely low-noise timing

SM General Description. ClockWorks. Features. Applications. Block Diagram

ClockWorks PCI-e Octal 100MHz/200MHz Ultra-Low Jitter, HCSL Frequency Synthesizer General Description The is a member of the ClockWorks family of devices from Micrel and provides an extremely low-noise

Features. Applications

PCIe Fanout Buffer 267MHz, 8 HCSL Outputs with 2 Input MUX PrecisionEdge General Description The is a high-speed, fully differential 1:8 clock fanout buffer optimized to provide eight identical output

General Purpose Clock Synthesizer

1CY 290 7 fax id: 3521 CY2907 General Purpose Clock Synthesizer Features Highly configurable single PLL clock synthesizer provides all clocking requirements for numerous applications Compatible with all

PL560/ VCXO Family

OSCOFF SEL GNDOSC VCON XIN VDDBUF QBAR Q GNDBUF (Prelim inary ) Analog Frequency Multiplier PRODUCT DESCRIPTION The Analog Frequency Multiplier (AFM) is the industry s first Balanced Oscillator utilizing

ICS7151A-50 SPREAD SPECTRUM CLOCK GENERATOR. Description. Features. Block Diagram DATASHEET

DATASHEET ICS7151A-50 Description The ICS7151A-50 is a clock generator for EMI (Electromagnetic Interference) reduction. Spectral peaks are attenuated by modulating the system clock frequency. Down or