ICS95V850. DDR Phase Lock Loop Clock Driver (60MHz - 210MHz) Integrated Circuit Systems, Inc. Pin Configuration. Block Diagram.

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1 Integrated Circuit Systems, Inc. ICS95V850 DDR hase Lock Loop Clock Driver (60MHz - 20MHz) Recommended Application: DDR Clock Driver roduct Description/Features: Low skew, low jitter LL clock driver Feedback pins for input to output synchronization Spread Spectrum tolerant inputs With bypass mode mux Operating frequency 60 to 20 MHz AC Coupled (Universal) CLK inputs: mv switching amplitude - (LVTTL, LVELL, LVDS, LVCMOS) standards translation to SSTL2 Switching Characteristics: CYCLE - CYCLE jitter: <60ps OUTUT - OUTUT skew: <60ps eriod jitter: ±30ps DUTY CYCLE: 49.5% % CLKC0 CLKT0 CLKT CLKC CLKC2 CLKT2 C CLK_IT CLK_IC C A A CLKC3 CLKT3 CLKT4 CLKC4 in Configuration ICS95V CLKC5 CLKT5 CLKT6 CLKC6 CLKC7 CLKT7 C FB_IC FB_IT FB_OUTT FB_OUTC CLKC8 CLKT8 CLKT9 CLKC9 48-in TSSO 6.0mm Body, 0.5mm itch Block Diagram FB_OUTT FB_OUTC CLKT0 CLKC0 CLKT CLKC CLKT2 CLKC2 CLKT3 CLKC3 Functionality A IUTS CLK_IT CLK_IC CLKT CLKC OUTUTS FB_OUTT FB_OUTC LL State L H L H L H Bypassed/Off H L H L H L Bypassed/Off 2.5V (nom) 2.5V (nom) L H L H L H On H L H L H L On FB_IT FB_IC CLK_IC CLK_IT A LL CLKT4 CLKC4 CLKT5 CLKC5 CLKT6 CLKC6 CLKT7 CLKC7 CLKT8 CLKC8 CLKT9 CLKC9

2 2 ICS95V850 in Descriptions UMBER I E AM I E Y T DESCRITIO 25, 24, 8, 8, 7,, 48 42, 4, 3, D G R W d Groun 47, 43, 40, 30, 26, 2 6, 9, 9, 23, LK[9:0] C T U O s output pair differential of clocks "Complementary" 46, 44, 39, 29, 27, 3 5, 0, 20, 22, LK[9:0] C T U O s output pair differential of Clock "True" 28, 2,, 4, 45, 38, 34, DD V R W V 2.5 supply, ower 3 T LK_I C I t inpu clock reference "True" 4 C LK_I C I t inpu clock reference "Complementary" 6 D VD A R W V 2.5 supply, power Analog 7 D G A R W d groun Analog 2 3 C B_OUT F T OU It feedback. external for dedicated output, Feedback "Complementary" wired be must output This CLK. as frequency same at switches FB_IC to 3 3 T B_OUT F T OU switches It feedback. external for dedicated output, Feedback " "True" to wired be must output This CLK. as frequency same at FB_IT 5 3 T B_I F I for LL internal to signal feedback provides input, Feedback "True" error phase eliminate CLK_IT to with synchronization 6 3 C B_I F I LL internal to signal provides input, Feedback "Complementary" error phase eliminate CLK_IC to with synchronization for 37 5, 2, C s Connect o

3 Absolute Maximum Ratings Supply Voltage: ( & A) V to 3.6V Input clamp current: I IK (VI < 0 or VI > ) /- 50mA Output clamp current: I OK (VO < 0 or VO > ).. +/- 50mA Continuous output current: I O (VO = 0 to ).... +/- 50mA ackage rmal impedance, ta JA: DGG package +89 C/Ω Storage Temperature C to +50 C Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to device. These ratings are stress specifications only and functional operation of device at se or any or conditions above those listed in operational sections of specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability. Electrical Characteristics - Input/Supply/Common Output arameters T A = 0-85 C; Supply Voltage A, V DD = 2.5 V +/- 0.2V (unless orwise stated) ARAMETER SYMBOL CODITIOS MI TY MA UITS Input High Current I IH V I = V DD or 5 µa Input Low Current I IL V I = V DD or 5 µa Operating Supply I DD2.5 C L = 200MHz 48 ma Current I DDD C L = 0pf 00 µa High Impedance V I DD = 2.7V, Vout = V DD or OZ Output Current ±0 ma Input Clamp Voltage V IK V DD = 2.3V Iin = -8mA -.2 V High-level output I OH = - ma V DD - 0. V V voltage OH I OH = -2 ma.7v V Low-level output voltage V OL I OL = ma 0. V I OH =2 ma 0.6 V Input Capacitance C I V I = or V DD pf Guaranteed by design at 233MHz, not 00% tested in production. 3

4 Recommended Operating Condition (see note) T A = 0-85 C; Supply Voltage A, = 2.5 V +/- 0.2V (unless orwise stated) ARAMETER SYMBOL CODITIOS MI TY MA UITS Supply Voltage V DD, A V CLK_IT, CLK_IC, FB_IC 0.4 V DD /2-0.8 V Low level input voltage V IL CLK_IT, CLK_IC (Universal Input) -0.3 V DD V High level input voltage DC input signal voltage (note 2) Differential input signal voltage (note 3) V IH CLK_IT, CLK_IC, FB_IC V DD / V CLK_IT, CLK_IC (Universal Input) 0.4 V DD V V I -0.3 V DD V DC - CLK_IT, FB_IT 0.36 V DD V V ID AC - CLK_IT, FB_IT (Universal Input) 0.4 V DD V Output differential crossvoltage (note 4) V O V DD /2-0.5 V DD / V Input differential crossvoltage (note 4) V I (Universal Input) 0.45(V IH - V IL ) 0.55(V IH - V IL ) V High level output current I OH -6.4 ma Low level output current I OL 5.5 ma Operating free-air temperature T A 0 85 C otes:. Unused inputs must be held high or low to prevent m from floating. 2. DC input signal voltage specifies allowable DC execution of differential input. 3. Differential inputs signal voltages specifies differential voltage [VTR-VC] required for switching, where VT is true input level and VC is complementary input level. 4. Differential cross-point voltage is expected to track variations of V DD and is voltage at which differential signal must be crossing. Timing Requirements T A = 0-85 C; Supply Voltage A, = 2.5 V +/- 0.2V (unless orwise stated) ARAMETER SYMBOL CODITIOS MI TY MA UITS Operating clock frequency freq op MHz Input clock duty cycle d tin % CLK stabilization T STAB 5 µs 4

5 Switching Characteristics (see note 3) ARAMETER SYMBOL CODITIO MI TY MA UITS Low-to high level propagation delay time t LH CLK_I to any output 5.5 ns High-to low level propagation delay time t LL CLK_I to any output 5.5 ns eriod jitter T jit (per) 00MHz to 200MHz ps Half-period jitter t(jit_hper) 00MHz to 200MHz ps Input clock slew rate t sl(i) 4 V/ns Output clock slew rate t sl(o) 2.5 V/ns Cycle to Cycle Jitter T cyc -T cyc 00MHz to 200MHz 60 ps hase error 4 t (phase error) ps Output to Output Skew T skew 60 ps otes:. Refers to transition on noninverting output in LL bypass mode. 2. While pulse skew is almost constant over frequency, duty cycle error increases at higher frequencies. This is due to formula: duty cycle=t wh /t c, where cycle (t c ) decreases as frequency goes up. 3. Switching characteristics guaranteed for application frequency range. 4. Static phase offset shifted by design. 5

6 arameter Measurement Information V DD V(CLKC) R=60Ω R=60Ω /2 V(CLKC) ICS95V850 Figure. IBIS Model Output Load V DD/2 ICS95V850 C=4pF-V DD/2 SCOE Z=60Ω R=0Ω Z=50Ω Z=60Ω R=0Ω Z=50Ω V(TT) R=50Ω C=4pF V(TT) R=50Ω -V DD/2 -V DD/2 OTE: V(TT) = Figure 2. Output Load Test Circuit Y, FB_OUTC Y, FB_OUTT tc(n) tc(n+) tjit(cc) =tc(n) ±tc(n+) Figure 3. Cycle-to-Cycle Jitter 6

7 arameter Measurement Information CLK_IC CLK_IT FB_IC FB_IT t ( ) n n= t ( ) n t ( ) = ( is a large number of samples) Figure 4. Static hase Offset t ( ) n+ Y # Y Y, FB_OUTC Y, FB_OUTT t (SK_O) Figure 5. Output Skew Y, FB_OUTC Y, FB_OUTT Y, FB_OUTC Y, FB_OUTT f O t (jit_per) = tc(n) - f O Figure 6. eriod Jitter 7

8 arameter Measurement Information Y, FB_OUTC Y, FB_OUTT t (hper_n) t(hper_n+) fo t (jit_hper) = t (jit_hper_n) - 2xf O Figure 7. Half-eriod Jitter 80% 80% VID, VOD Clock Inputs and Outputs 20% 20% Rise t sl Fall t sl Figure 8. Input and Output Slew Rates 8

9 Recommended Layout for ICS95V850 General Layout recautions: Use copper flooded ground on top signal layer under clock buffer The area under U on right is an example. Flood over ground vias. ) Use power vias for power and ground. Vias 20 mil or larger in diameter have lower high frequency impedance. Vias for signals may be minimum drill size. 2) Make all power and ground traces are as wide as via pad for lower inductance. 3) VAA for pin 6 has a low pass RC filter to decouple digital and analog supplies. The 4.7uF capacitors may be replaced with a single low ESR device with same total capacitance. VAA is routed on a outside signal layer. Do not cut a power or ground plane and route in it. 4) otice that ground vias are never shared. 5) When ever possible, VCC (net V25 in schematic) pins have a decoupling capacitor. ower is always routed from plane connection via to capacitor pad to VCC pin on clock buffer. Moats or plane cuts are not used to isolate power. 6) Differential mode clock output traces are routed: a. With a ground trace between pairs. Trace is grounded on both ends. b. Without a ground trace, clock pairs are routed with a separation of at least 5 times thickness of dielectric. If dielectric thickness is 4.5 mil, trace separation is at least 8 mils. 7) Terminate differential CLK_I and FB_I traces after routing to buffer pads. Component Values: Ref Desg. Value Description ackage C,C4,C5,.0uF CERAMIC MLC 0603 C7,C,C2 C2,C3,C8, 4.7uF CERAMIC MLC 206 C9 C0.22uF CERAMIC MLC 0603 C6 2200pF CERAMIC MLC 0603 R9,R2 20 Ω 0603 R9 4.7 Ω 0603 U ICS95V850 TSSO48 9

10 IDE AREA A2 e 2 D b E A A E c -C- - SEATIG LAE aaa C 6.0 mm. Body, 0.50 mm. pitch TSSO (240 mil) (0.020 mil) L In Millimeters In Inches SYMBOL COMMO DIMESIOS COMMO DIMESIOS MI MA MI MA A A A b c D E SEE VARIATIOS 8.0 BASIC SEE VARIATIOS 0.39 BASIC E e 0.50 BASIC BASIC L SEE VARIATIOS SEE VARIATIOS α aaa VARIATIOS D mm. D (inch) MI MA MI MA Reference Doc.: JEDEC ublication 95, MO Ordering Information Example: 95V850yLFGT y G (LF) - T Designation for tape and reel packaging Lead Free (Optional) ackage Type G = TSSO Revision Designator (will not correlate with datasheet revision) Device Type 0