All Devices Discontinued!

Transcription

1 GAL 22LV Device Datasheet June 2 All Devices Discontinued! Product Change Notifications (PCNs) have been issued to discontinue all devices in this data sheet The original datasheet pages have not been modified and do not reflect those changes Please refer to the table below for reference PCN and current product status Product Line Ordering Part Number Product Status Reference PCN GAL22LVC-7LJ GAL22LVC-7LJN PCN#6-7 GAL22LVC-LJ GAL22LVC Discontinued GAL22LVC-LJN PCN#9- GAL22LVC-5LJ GAL22LVC-5LJN GAL22LVD-4LJ GAL22LVD GAL22LVD-4LJN GAL22LVD-5LJ Discontinued PCN#9- GAL22LVD-5LJN 5555 NE Moore Ct Hillsboro, Oregon Phone (53) FAX (53) nternet:

2 New 5V Tolerant nputs on 22LVD GAL22LV Low Voltage E 2 CMOS PLD Generic Array Logic Features Functional Block Diagram HGH PERFORMANCE E 2 CMOS TECHNOLOGY 4 ns Maximum Propagation Delay Fmax = 25 MHz 3 ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology 33V LOW VOLTAGE 22V ARCHTECTURE JEDEC-Compatible 33V nterface Standard 5V Compatible nputs /O nterfaces with Standard 5V TTL Devices (GAL22LVC) ACTVE PULL-UPS ON ALL PNS (GAL22LVD) E 2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) 2 Year Data Retention TEN OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs Programmable Output Polarity PRELOAD AND POWER-ON RESET OF ALL REGSTERS % Functional Testability APPLCATONS NCLUDE: Glue Logic for 33V Systems DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON LEAD-FREE PACKAGE OPTONS Description The GAL22LVD, at 4 ns maximum propagation delay time, provides the highest speed performance available in the PLD market The GAL22LVC can interface with both 33V and 5V signal levels The GAL22LV is manufactured using Lattice Semiconductor's advanced 33V E 2 CMOS process, which combines CMOS with Electrically Erasable (E 2 ) floating gate technology High speed erase times (<ms) allow the devices to be reprogrammed quickly and efficiently The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products n addition, erase/write cycles and data retention in excess of 2 years are specified / NC / NC PROGRAMMABLE AND-ARRAY (32X44) Pin Configuration ALL DEVCES 4 GND PLCC DSCONTNUED NC Vcc 6 RESET PRESET /O/Q /O/Q GAL22LV Top View 8 /O/Q 9 8 /O/Q 23 2 /O/Q /O/Q /O/Q NC /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q Copyright 28 Lattice Semiconductor Corp All brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice LATTCE SEMCONDUCTOR CORP, 5555 Northeast Moore Ct, Hillsboro, Oregon 9724, USA August 28 Tel (53) 268-8; -8-LATTCE; FAX (53) ; 22lv_7

3 Specifications GAL22LV GAL22LV Ordering nformation Conventional Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GAL22LVD-4LJ GAL22LVD-5LJ AL22LVC-7LJ GAL22LVC-LJ 5 75 GAL22LVC-5LJ Lead-Free Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # Discontinued per PCN #6-7 Contact Rochester Electronics for available inventory Part Number Description GAL22LVD GAL22LVC L = Low Power Device Name Speed (ns) Power _ XXXXXXXX XX X X X 28-Lead PLCC 28-Lead PLCC 28-Lead PLC 28-Lead PLCC 28-Lead PLCC G C Grade Package Package Package GAL22LVD-4LJN Lead-Free 28-Lead PLCC GAL22LVD-5LJN Lead-Free 28-Lead PLCC GAL22LVC-7LJN Lead-Free 28-Lead PLCC GAL22LVC-LJN Lead-Free 28-Lead PLCC 5 75 GAL22LVC-5LJN Lead-Free 28-Lead PLCC ALL DEVCES Blank = Commercial J = PLCC JN = Lead-Free PLCC DSCONTNUED 2

4 Specifications GAL22LV Output Logic Macrocell () The GAL22LV has a variable number of product terms per Of the ten available s, two s have access to eight product terms (pins 7 and 27), two have ten product terms (pins 8 and 26), two have twelve product terms (pins 9 and 25), two have fourteen product terms (pins 2 and 24), and two s have sixteen product terms (pins 2 and 23) n addition to the product terms available for logic, each has an additional product-term dedicated to output enable control The output polarity of each can be individually programmed to be true or inverting, in either combinatorial or registered mode This allows each output to be individually configured as either active high or active low Each of the Macrocells of the GAL22LV has two primary functional modes: registered, and combinatorial /O The modes and the output polarity are set by two bits (SO and S), which are normally controlled by the logic compiler Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page REGSTERED n registered mode the output pin associated with an individual is driven by the Q output of that s D-type flip-flop Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each, and can therefore be defined by a logic equation The D flip-flop s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array D 2 TO MUX AR SP Q Q GAL22LV OUTPUT LOGC MACROCELL () The GAL22LV has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP) These two product terms are common to all registered s The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen 4 TO MUX ALL DEVCES Output Logic Macrocell Configurations NOTE: n registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic /O, as can the combinatorial pins DSCONTNUED COMBNATORAL /O n combinatorial mode the pin associated with an individual is driven by the output of the sum term gate Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either on (dedicated output), off (dedicated input), or product-term driven (dynamic /O) Feedback into the AND array is from the pin side of the output enable buffer Both polarities (true and inverted) of the pin are fed back into the AND array 3

5 Specifications GAL22LV Registered Mode S = S = Combinatorial Mode D AR SP ACTVE LOW ACTVE LOW Q Q S = S = ACTVE HGH ALL DEVCES DSCONTNUED D AR SP Q Q ACTVE HGH S = S = S = S = 4

6 Specifications GAL22LV GAL22LV Logic Diagram/JEDEC Fuse Map PLCC Package Pinout ASYNCHRONOUS RESET (TO ALL REGSTERS) S 588 S 589 S 58 S 58 S 582 S 583 S 584 S 585 S 586 S 587 S 588 S 589 S 582 S 582 ALL DEVCES S 5822 S 5823 DSCONTNUED S 5824 S 5825 S 5826 S 5827 SYNCHRONOUS PRESET (TO ALL REGSTERS) , 5829 Electronic Signature 589, 589 Byte 7 Byte 6 Byte 5 Byte 4 Byte 3 Byte 2 Byte Byte M S B L S B 5

7 Specifications GAL22LVD Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC -5 to +46V nput voltage applied -5 to +56V /O voltage applied -5 to +46V Off-state output voltage applied -5 to +46V Storage Temperature -65 to 5 C Ambient Temperature with Power Applied -55 to 25 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) DC Electrical Characteristics VL nput Low Voltage Vss V VH nput High Voltage V COMMERCAL /O High Voltage 2 Vcc+5 V L nput or /O Low Leakage Current V VN VL (MAX) - μa H nput or /O High Leakage Current (Vcc-2)V VN VCC μa nput High Leakage Current Vcc VN 525V μa /O High Leakage Current Vcc VN 46V 2 ma VOL Output Low Voltage OL = MAX Vin = VL or VH 4 V CC Operating Power VL = V VH = 3V Unused nputs at VL 9 3 ma Supply Current ftoggle = MHz Outputs Open Commercial Devices: Ambient Temperature (T A ) to 75 C Supply voltage (V CC ) with Respect to Ground +3 to +36V Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN TYP 3 MAX UNTS OL = 5μA Vin = VL or VH 2 V ALL DEVCES VOH Output High Voltage OH = MAX Vin = VL or VH 24 V OH = -μa Vin = VL or VH Vcc-2V V OL Low Level Output Current 8 ma OH High Level Output Current 8 ma OS 2 Output Short Circuit Current VCC = 33V VOUT = 5V T A = 25 C -5-8 ma DSCONTNUED ) The leakage current is due to the internal pull-up resistor on all pins See nput Buffer section for more information 2) One output at a time for a maximum duration of one second Vout = 5V was selected to avoid test problems caused by tester ground degradation Characterized but not % tested 3) Typical values are at Vcc = 33V and TA = 25 C 6

8 Specifications GAL22LVD AC Switching Characteristics PARAMETER TEST COND DESCRPTON Over Recommended Operating Conditions tpd 2 A nput or /O to Combinational Output 4 5 ns tco 2 A Clock to Output Delay 3 35 ns tcf 3 Clock to Feedback Delay 25 3 ns tsu Setup Time, nput or Feedback before Clock 3 35 ns th Hold Time, nput or Feedback after Clock ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 4 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with 25 2 MHz No Feedback twh 4 Clock Pulse Duration, High 2 25 ns twl 4 Clock Pulse Duration, Low 2 25 ns ten B nput or /O to Output Enabled 5 6 ns tdis C nput or /O to Output Disabled 5 6 ns tar A nput or /O to Asynchronous Reset of Register ns tarw Asynchronous Reset Pulse Duration ns tarr Asynchronous Reset to Clock Recovery Time 35 4 ns tspr Synchronous Preset to Clock Recovery Time 35 4 ns ) Refer to Switching Test Conditions section 2) Minimum values for tpd and tco are not % tested but established by characterization 3) Calculated from fmax with internal feedback Refer to fmax Descriptions section 4) Refer to fmax Descriptions section Characterized but not % tested SYMBOL PARAMETER TYPCAL UNTS TEST CONDTONS C nput Capacitance 5 pf V CC = 33V, V = V C /O /O Capacitance 5 pf V CC = 33V, V /O = V MN COM ALL DEVCES Capacitance (T A = 25 C, f = MHz) -4 MAX MN COM -5 MAX UNTS DSCONTNUED 7

9 Specifications GAL22LVC Absolute Maximum Ratings () Recommended Operating Conditions Supply voltage V CC -5 to +56V nput voltage applied -5 to +56V Off-state output voltage applied -5 to +56V Storage Temperature -65 to 5 C Ambient Temperature with Power Applied -55 to 25 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) DC Electrical Characteristics Commercial Devices: Ambient Temperature (T A ) to +75 C Supply voltage (V CC ) with Respect to Ground +3 to +36V SYMBOL PARAMETER CONDTON MN TYP 2 MAX UNTS VL nput Low Voltage Vss 5 8 V VH nput High Voltage V L nput or /O Low Leakage Current V VN VL (MAX) - μa H nput or /O High Leakage Current (VCC - 2)V VN VCC μa VCC VN 525V 3 ma VOL Output Low Voltage OL = 8mA Vin = VL or VH 4 V OL = 6 ma Vin = VL or VH 5 V OL = 5 ma Vin = VL or VH 2 V VOH Output High Voltage OH = MAX Vin = VL or VH 24 V OH = -5 ma Vin = VL or VH Vcc-45 V OH = - μa Vin = VL or VH Vcc-2 V OL Low Level Output Current VOL = 4 V 8 ma VOL = 5V 6 ma OH High Level Output Current -4 ma OS Output Short Circuit Current VCC = 33V VOUT = 5V TA = 25 C -5-6 ma COMMERCAL Over Recommended Operating Conditions (Unless Otherwise Specified) ALL DEVCES DSCONTNUED CC Operating Power VL = V VH = 3V ma Supply Current ftoggle = MHz Outputs Open ) One output at a time for a maximum duration of one second Vout = 5V was selected to avoid test problems by tester ground degradation Characterized but not % tested 2) Typical values are at Vcc = 33V and TA = 25 C 8

10 Specifications GAL22LVC AC Switching Characteristics PARAM TEST COND DESCRPTON Over Recommended Operating Conditions UNTS MN MAX MN MAX MN MAX tpd 2 A nput or /O to Combinatorial Output ns tco 2 A Clock to Output Delay 5 65 ns tcf 3 Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk 6 75 ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 4 A Maximum Clock Frequency with 8 66 MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High ns twl Clock Pulse Duration, Low ns ten B nput or /O to Output Enabled ns tdis C nput or /O to Output Disabled ns tar A nput or /O to Asynch Reset of Reg ns tarw Asynch Reset Pulse Duration 6 8 ns tarr Asynch Reset to Clk Recovery Time 6 8 ns tspr Synch Preset to Clk Recovery Time 6 8 ns ) Refer to Switching Test Conditions section 2) Minimum values for tpd and tco are not % tested but established by characterization 3) Calculated from fmax with internal feedback Refer to fmax Description section 4) Refer to fmax Description section SYMBOL PARAMETER TYPCAL UNTS TEST CONDTONS C nput Capacitance 8 pf V CC = 33V, V = V C /O /O Capacitance 8 pf V CC = 33V, V /O = V COM COM ALL DEVCES Capacitance (T A = 25 C, f = MHz) DSCONTNUED COM 9

11 Specifications GAL22LV Switching Waveforms NPUT or /O FEEDBACK COMBNATORAL OUTPUT NPUT or /O FEEDBACK OUTPUT NPUT or /O FEEDBACK DRVNG SP REGSTERED OUTPUT Combinatorial Output nput or /O to Output Enable/Disable tw h tdis Clock Width / fm ax (w/o fdbk) VALD NPUT tpd tw l ten NPUT or /O FEEDBACK REGSTERED OUTPUT NPUT or /O FEEDBACK DRVNG AR REGSTERED FEEDBACK REGSTERED OUTPUT VALD NPUT ts u / fm ax (external fdbk) Registered Output tc f fmax with Feedback ALL DEVCES tsu th tco tspr tarw tar th tc o / fmax (internal fdbk) DSCONTNUED tsu tarr Synchronous Preset Asynchronous Reset

12 Specifications GAL22LV fmax Descriptions LOGC ARRAY tsu REGSTER fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco LOGC ARRAY tsu + th REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl) This is to allow for a clock duty cycle of other than 5% tco LOGC ARRAY tcf tpd REGSTER fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu) The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above For example, the timing from clock to a combinatorial output is equal to tcf + tpd ALL DEVCES DSCONTNUED

13 Specifications GAL22LV GAL22LVD: Switching Test Conditions nput Pulse Levels GND to 3V nput Rise and Fall Times 5ns % 9% nput Timing Reference Levels 5V Output Timing Reference Levels 5V Output Load See Figure Output Load Conditions (see figure) Test Condition R CL A 5Ω 35pF B High Z to Active High at 9V 5Ω 35pF High Z to Active Low at V 5Ω 35pF C Active High to High Z at 9V 5Ω 35pF Active Low to High Z at V 5Ω 35pF GAL22LVC: Switching Test Conditions nput Pulse Levels GND to 3V nput Rise and Fall Times 2ns % 9% nput Timing Reference Levels 5V Output Timing Reference Levels 5V Output Load See Figure 3-state levels are measured 5V from steady-state active level Output Load Conditions (see figure) Test Condition R R2 CL A 36Ω 348Ω 35pF B Active High 36Ω 348Ω 35pF Active Low 36Ω 348Ω 35pF C Active High 36Ω 348Ω 5pF Active Low 36Ω 348Ω 5pF FROM OUTPUT (O/Q) UNDER TEST TEST PONT Z = 5Ω, CL = 35pF* *C L includes test fixture and probe capacitance FROM OUTPUT (O/Q) UNDER TEST ALL DEVCES R 2 +33V C * L +45V R TEST PONT *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE DSCONTNUED R 2

14 Specifications GAL22LV Electronic Signature Output Register Preload An electronic signature (ES) is provided in every GAL22LV device t contains 64 bits of reprogrammable memory that can contain user-defined data Some uses include user D codes, revision numbers, or inventory control The signature data is always available to the user independent of the state of the security cell The electronic signature is an additional feature not present in other manufacturers' 22V devices To use the extra feature of the userprogrammable electronic signature it is necessary to choose a Lattice Semiconductor 22V device type when compiling a set of logic equations n addition, many device programmers have two separate selections for the device, typically a GAL22LV and a GAL22V-UES (UES = User Electronic Signature) or GAL22V- ES This allows users to maintain compatibility with existing 22V designs, while still having the option to use the GAL device's extra feature The JEDEC map for the GAL22LV contains the 64 extra fuses for the electronic signature, for a total of 5892 fuses However, the GAL22LV device can still be programmed with a standard 22V JEDEC map (5828 fuses) with any qualified device programmer Security Cell A security cell is provided in every GAL22LV device to prevent unauthorized copying of the array patterns Once programmed, this cell prevents further read access to the functional bits in the device This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed The Electronic Signature is always available to the user, regardless of the state of this control cell Latch-Up Protection GAL22LV devices are designed with an on-board charge pump to negatively bias the substrate The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch Device Programming GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section) Complete programming of the device takes only a few seconds Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc) To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (ie, illegal) state into the registers Then the machine can be sequenced and the outputs tested for correct next state conditions The GAL22LV device includes circuitry that allows each registered output to be synchronously set either high or low Thus, any present state condition can be forced for test sequencing f necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically nput Buffers GAL22LV devices are designed with TTL level compatible input buffers These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices The input and /O pins on the GAL22LVD also have built-in active pull-ups As a result, floating inputs will float to a TTL high (logic ) However, Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to an adjacent active input, Vcc, or ground Doing so will tend to improve noise immunity and reduce cc for the device (See equivalent input and /O schematics on the following page) nput Current (μa) Typical nput Pull-up Characteristic ALL DEVCES DSCONTNUED nput Voltage (V)

15 Specifications GAL22LV Power-Up Reset Vcc Vcc (min) tsu PN PN Vcc ESD Protection Circuit ESD Protection Circuit Vref NTERNAL REGSTER Q - OUTPUT ACTVE LOW OUTPUT REGSTER ACTVE HGH OUTPUT REGSTER nput/output Equivalent Schematics Active Pull-up Circuit (GAL22LVD Only) Vcc Vcc tpr twl nternal Register Reset to Logic "" Device Pin Reset to Logic "" Device Pin Reset to Logic "" Circuitry within the GAL22V provides a reset signal to all registers during power-up All internal registers will have their Q outputs set low after a specified time (tpr, μs MAX) As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins This feature can greatly simplify state machine design by providing a known state on power-up The timing diagram for power-up is shown below Because of the asynchronous nature of system power-up, some conditions must be met to provide a valid power-up reset of the GAL22V First, the Vcc rise must be monotonic Second, the clock input must be at static TTL level as shown in the diagram during power up The registers will reset within a maximum of tpr time As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met The clock must also meet the minimum pulse width requirements Data Output Feedback ALL DEVCES Tri-State Control Active Pull-up Circuit (GAL22LVD Only) DSCONTNUED Vcc Vref PN PN Typ Vref = Vcc Typ Vref = Vcc Feedback (To nput Buffer) Typical nput Typical Output 4

16 Specifications GAL22LV GAL22LVD: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd 2 PT H->L PT L->H Supply Voltage (V) Normalized Tpd vs Temp 3 2 PT H->L PT L->H Temperature (deg C) Delta Tpd (ns) Normalized Tco Normalized Tco 5 RSE Delta Tpd vs # of Outputs Switching RSE Number of Outputs Switching Supply Voltage (V) Normalized Tco vs Temp RSE Temperature (deg C) Normalized Tsu Normalized Tsu 2 PT H->L PT L->H Delta Tco vs # of Outputs Switching ALL DEVCES Delta Tpd (ns) Delta Tpd vs Output Loading RSE Delta Tco (ns) Delta Tco (ns) Number of Outputs Switching Supply Voltage (V) Normalized Tsu vs Temp PT H->L PT L->H RSE Delta Tco vs Output Loading Temperature (deg C) DSCONTNUED RSE Output Loading (pf) Output Loading (pf) 5

17 Specifications GAL22LV GAL22LVD: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh Vol (V) Normalized cc Delta cc (ma) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg C) nput Clamp (Vik) ALL DEVCES Vik (V) Voh (V) Normalized cc oh(ma) Normalized cc vs Freq Frequency (MHz) DSCONTNUED 6

18 Specifications GAL22LV GAL22LVC: Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd 2 5 PT H->L PT L->H 25 RSE Supply Voltage (V) Normalized Tpd vs Temp 3 2 PT H->L PT L->H Temperature (deg C) Delta Tpd (ns) Delta Tpd (ns) Normalized Tco Normalized Tco Delta Tpd vs # of Outputs Switching Number of Outputs Switching Supply Voltage (V) Normalized Tco vs Temp RSE Temperature (deg C) Normalized Tsu Normalized Tsu 2 PT H->L PT L->H Supply Voltage (V) Normalized Tsu vs Temp RSE Delta Tpd vs Output Loading RSE Delta Tco (ns) Delta Tco (ns) Delta Tco vs # of Outputs Switching ALL DEVCES RSE Number of Outputs Switching Delta Tco vs Output Loading RSE Output Loading (pf) Output Loading (pf) PT H->L PT L->H Temperature (deg C) DSCONTNUED 7

19 Specifications GAL22LV GAL22LVC: Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh 4 3 Delta cc (ma) Normalized cc Vol (V) ol (ma) Normalized cc vs Vcc Supply Voltage (V) Delta cc vs Vin ( input) Vin (V) Voh (V) Normalized cc ik (ma) oh(ma) Normalized cc vs Temp Temperature (deg C) nput Clamp (Vik) ALL DEVCES Vik (V) Voh (V) Normalized cc oh(ma) Normalized cc vs Freq Frequency (MHz) DSCONTNUED 8

20 Specifications GAL22LV Revision History Date Version Change Summary - 22lv_5 Previous Lattice release August 26 22lv_6 Updated for lead-free package options August 28 22lv_7 Correction for DC electrical characteristics ALL DEVCES DSCONTNUED 9