Lead-Free Package Options Available! I/CLK I I I I/O/Q. Vcc I/CLK

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1 Features Lead-Free Package Options Available! Specifications GAL22V GAL22V High Performance E 2 CMOS PLD Generic Array Logic Functional Block Diagram HGH PERFORMANCE E 2 CMOS TECHNOLOGY ns Maximum Propagation Delay Fmax = 25 MHz 35 ns Maximum from Clock nput to Data Output UltraMOS Advanced CMOS Technology ACTVE PULL-UPS ON ALL PNS COMPATBLE WTH STANDARD 22V DEVCES Fully Function/Fuse-Map/Parametric Compatible with Bipolar and UVCMOS 22V Devices 5% to 75% REDUCTON N POWER VERSUS BPOLAR 9mA Typical cc on Low Power Device 5mA Typical cc on Quarter Power Device E 2 CELL TECHNOLOGY Reconfigurable Logic Reprogrammable Cells % Tested/% Yields High Speed Electrical Erasure (<ms) 2 Year Data Retention TEN OUTPUT LOGC MACROCELLS Maximum Flexibility for Complex Logic Designs PRELOAD AND POWER-ON RESET OF REGSTERS % Functional Testability APPLCATONS NCLUDE: DMA Control State Machine Control High Speed Graphics Processing Standard Logic Speed Upgrade ELECTRONC SGNATURE FOR DENTFCATON LEAD-FREE PACKAGE OPTONS ESCRPTON Description The GAL22V, at ns maximum propagation delay time, combines a high performance CMOS process with Electrically Erasable (E 2 ) floating gate technology to provide the highest performance available of any 22V device on the market CMOS circuitry allows the GAL22V to consume much less power when compared to bipolar 22V devices E 2 technology offers high speed (<ms) erase times, providing the ability to reprogram or reconfigure the device quickly and efficiently The generic architecture provides maximum design flexibility by allowing the Output Logic Macrocell () to be configured by the user The GAL22V is fully function/fuse map/parametric compatible with standard bipolar and CMOS 22V devices Unique test circuitry and reprogrammable cells allow complete AC, DC, and functional testing during manufacture As a result, Lattice Semiconductor delivers % field programmability and functionality of all GAL products n addition, erase/write cycles and data retention in excess of 2 years are specified NC Vcc 2 / / NC /O/Q /O/Q 7 23 /O/Q 9 / 2 GND /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /OE 6 NC Vcc 6 PROGRAMMABLE AND-ARRAY (32X) Pin Configuration PLCC /O/Q /O/Q GAL22V Top View SOC GAL22V Top View /O/Q 9 /O/Q GND NC /O/Q /O/Q /O/Q RESET PRESET / GND 6 DP GAL 22V /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q Vcc /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q /O/Q Copyright 2 Lattice Semiconductor Corp All brand or product names are trademarks or registered trademarks of their respective holders The specifications and information herein are subject to change without notice LATTCE SEMCONDUCTOR CORP, 5555 Northeast Moore Ct, Hillsboro, Oregon 972, USA August 2 Tel (53) 26-; --LATTCE; FAX (53) ; 22v_9

2 Specifications GAL22V GAL22V Ordering nformation Conventional Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GAL22VD-LJ 5 3 GAL22VD-5LJ GAL22VD-7LP 5 5 GAL22VD-7LJ GAL22VD-QP 55 GAL22VD-QJ 3 GAL22VD-LP 3 GAL22VD-LJ 3 GAL22VD-LS 5 55 GAL22VD-5QP 55 GAL22VD-5QJ 3 GAL22VD-5LP 3 GAL22VD-5LJ 3 GAL22VD-5LS GAL22VD-25QP 55 GAL22VD-25QJ 9 GAL22VD-25LP 9 GAL22VD-25LJ 9 GAL22VD-25LS Package 2-Pin Plastic DP 2-Pin Plastic DP 2-Pin Plastic DP 2-Pin SOC 2-Pin Plastic DP 2-Pin Plastic DP 2-Pin SOC 2-Pin Plastic DP 2-Pin Plastic Dip 2-Pin SOC ndustrial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # Package GAL22VD-7LP 2-Pin Plastic DP GAL22VD-7LJ GAL22VD-LP 2-Pin Plastic DP 5 5 GAL22VD-5LP 5 GAL22VD-5LJ 2 5 GAL22VD-2LP 5 GAL22VD-2LJ GAL22VD-25LP 6 GAL22VD-LJ 5 GAL22VD-25LJ 2-Pin Plastic DP 2-Pin Plastic DP 2-Pin Plastic DP 2

3 Specifications GAL22V Lead-Free Packaging Commercial Grade Specifications T pd (ns) T su (ns) T co (ns) cc (ma) Ordering # GAL22VD-LJN 5 3 GAL22VD-5LJN GAL22VD-7LPN 5 5 GAL22VD-7LJN GAL22VD-QPN 55 GAL22VD-QJN 3 GAL22VD-LPN 3 GAL22VD-LJN 5 55 GAL22VD-5QPN 55 GAL22VD-5QJN 3 GAL22VD-5LPN 3 GAL22VD-5LJN GAL22VD-25QPN 55 GAL22VD-25QJN 9 GAL22VD-25LPN 9 GAL22VD-25LJN Package Lead-Free Lead-Free Lead-Free 2-Pin Plastic DP Lead-Free Lead-Free 2-Pin Plastic DP Lead-Free Lead-Free 2-Pin Plastic DP Lead-Free Lead-Free 2-Pin Plastic DP Lead-Free Lead-Free 2-Pin Plastic DP Lead-Free Lead-Free 2-Pin Plastic DP Lead-Free Lead-Free 2-Pin Plastic Dip Lead-Free Part Number Description _ XXXXXXXX XX X XX X GAL22VD Device Name Speed (ns) Grade Blank = Commercial = ndustrial L = Low Power Q = Quarter Power Power Package P = Plastic DP PN = Lead-Free Plastic DP J = PLCC JN = Lead-Free PLCC S = SOC 3

4 Specifications GAL22V Output Logic Macrocell () The GAL22V has a variable number of product terms per Of the ten available s, two s have access to eight product terms (pins and 23, DP pinout), two have ten product terms (pins 5 and 22), two have twelve product terms (pins 6 and 2), two have fourteen product terms (pins 7 and 2), and two s have sixteen product terms (pins and 9) n addition to the product terms available for logic, each has an additional product-term dedicated to output enable control The output polarity of each can be individually programmed to be true or inverting, in either combinatorial or registered mode This allows each output to be individually configured as either active high or active low The GAL22V has a product term for Asynchronous Reset (AR) and a product term for Synchronous Preset (SP) These two product terms are common to all registered s The Asynchronous Reset sets all registers to zero any time this dedicated product term is asserted The Synchronous Preset sets all registers to a logic one on the rising edge of the next clock pulse after this product term is asserted NOTE: The AR and SP product terms will force the Q output of the flip-flop into the same state regardless of the polarity of the output Therefore, a reset operation, which sets the register output to a zero, may result in either a high or low at the output pin, depending on the pin polarity chosen AR D Q Q TO MUX SP 2 TO MUX GAL22V OUTPUT LOGC MACROCELL () Output Logic Macrocell Configurations Each of the Macrocells of the GAL22V has two primary functional modes: registered, and combinatorial /O The modes and the output polarity are set by two bits (SO and S), which are normally controlled by the logic compiler Each of these two primary modes, and the bit settings required to enable them, are described below and on the following page REGSTERED n registered mode the output pin associated with an individual is driven by the Q output of that s D-type flip-flop Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each, and can therefore be defined by a logic equation The D flip-flop s /Q output is fed back into the AND array, with both the true and complement of the feedback available as inputs to the AND array NOTE: n registered mode, the feedback is from the /Q output of the register, and not from the pin; therefore, a pin defined as registered is an output only, and cannot be used for dynamic /O, as can the combinatorial pins COMBNATORAL /O n combinatorial mode the pin associated with an individual is driven by the output of the sum term gate Logic polarity of the output signal at the pin may be selected by specifying that the output buffer drive either true (active high) or inverted (active low) Output tri-state control is available as an individual product-term for each output, and may be individually set by the compiler as either on (dedicated output), off (dedicated input), or product-term driven (dynamic /O) Feedback into the AND array is from the pin side of the output enable buffer Both polarities (true and inverted) of the pin are fed back into the AND array

5 Specifications GAL22V Registered Mode AR AR D Q D Q Q Q SP SP ACTVE LOW ACTVE HGH S = S = S = S = Combinatorial Mode ACTVE LOW ACTVE HGH S = S = S = S = 5

6 Specifications GAL22V GAL22V Logic Diagram / JEDEC Fuse Map (2) 396 DP (PLCC) Package Pinouts ASYNCHRONOUS RESET (TO ALL REGSTERS) S 5 S (27) 2 (3) 3 () (5) 5 (6) 6 (7) 7 (9) () 9 () (2) S 5 S 5 S 52 S 53 S 5 S 55 S 56 S 57 S 5 S 59 S 52 S 52 S 522 S 523 S 52 S 525 S 526 S 527 SYNCHRONOUS PRESET (TO ALL REGSTERS) 22 (26) 2 (25) 2 (2) 9 (23) (2) 7 (2) 6 (9) 5 () (7) (3) 3 (6) , 529 Electronic Signature 59, 59 Byte 7 Byte 6 Byte 5 Byte Byte 3 Byte 2 Byte Byte M L SB S B 6

7 Specifications GAL22VD Absolute Maximum Ratings Supply voltage V CC -5 to +7V nput voltage applied -25 to V CC +V Off-state output voltage applied -25 to V CC +V Storage Temperature -65 to 5 C Ambient Temperature with Power Applied -55 to 25 C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device These are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications) Recommended Operating Conditions Commercial Devices: Ambient Temperature (T A ) to +75 C Supply voltage (V CC ) with Respect to Ground +75 to +525V ndustrial Devices: Ambient Temperature (T A ) - to 5 C Supply voltage (V CC ) with Respect to Ground +5 to +55V DC Electrical Characteristics Over Recommended Operating Conditions (Unless Otherwise Specified) SYMBOL PARAMETER CONDTON MN TYP 3 MAX UNTS VL nput Low Voltage Vss 5 V VH nput High Voltage 2 Vcc+ V L nput or /O Low Leakage Current V VN VL (MAX) µa H nput or /O High Leakage Current 35V VN VCC µa VOL Output Low Voltage OL = MAX Vin = VL or VH V VOH Output High Voltage OH = MAX Vin = VL or VH 2 V OL Low Level Output Current 6 ma OH High Level Output Current 32 ma OS 2 Output Short Circuit Current VCC = 5V VOUT = 5V T A = 25 C 3 3 ma COMMERCAL CC Operating Power VL = 5V VH = 3V L-/-5/-7 9 ma Supply Current ftoggle = 5MHz Outputs Open L- 9 3 ma L-5/ ma Q-/-5/ ma NDUSTRAL CC Operating Power VL = 5V VH = 3V L-7/- 9 6 ma Supply Current ftoggle = 5MHz Outputs Open L-5/-2/ ma ) The leakage current is due to the internal pull-up on all pins See nput Buffer section for more information 2) One output at a time for a maximum duration of one second Vout = 5V was selected to avoid test problems caused by tester ground degradation Characterized but not % tested 3) Typical values are at Vcc = 5V and TA = 25 C 7

8 Specifications GAL22VD AC Switching Characteristics Over Recommended Operating Conditions COM COM COM/ND PARAM TEST COND DESCRPTON UNTS MN MAX MN MAX MN MAX tpd A nput or /O to Combinatorial Output 5 75 ns tco A Clock to Output Delay 35 5 ns tcf 2 Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with 67 2 MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High ns twl Clock Pulse Duration, Low ns ten B nput or /O to Output Enabled ns tdis C nput or /O to Output Disabled ns tar A nput or /O to Asynch Reset of Reg ns tarw Asynch Reset Pulse Duration ns tarr Asynch Reset to Clk Recovery Time 3 5 ns tspr Synch Preset to Clk Recovery Time 3 5 ns ) Refer to Switching Test Conditions section 2) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section Characterized initially and after any design or process changes that may affect these parameters Capacitance (T A = 25 C, f = MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5V, V = 2V C /O /O Capacitance pf V CC = 5V, V /O = 2V *Characterized but not % tested

9 Specifications GAL22VD AC Switching Characteristics PARAM TEST COND DESCRPTON Over Recommended Operating Conditions UNTS MN MAX MN MAX MN MAX MN MAX tpd A nput or /O to Comb Output ns tco A Clock to Output Delay ns tcf 2 Clock to Feedback Delay ns tsu Setup Time, nput or Fdbk before Clk ns th Hold Time, nput or Fdbk after Clk ns A Maximum Clock Frequency with MHz External Feedback, /(tsu + tco) fmax 3 A Maximum Clock Frequency with MHz nternal Feedback, /(tsu + tcf) A Maximum Clock Frequency with MHz No Feedback twh Clock Pulse Duration, High 6 3 ns twl Clock Pulse Duration, Low 6 3 ns ten B nput or /O to Output Enabled ns tdis C nput or /O to Output Disabled ns tar A nput or /O to Asynch Reset of Reg ns tarw Asynch Reset Pulse Duration ns tarr Asynch Reset to Clk Recovery Time 2 25 ns tspr Synch Preset to Clk Recovery Time 5 ns ) Refer to Switching Test Conditions section 2) Calculated from fmax with internal feedback Refer to fmax Description section 3) Refer to fmax Description section Capacitance (T A = 25 C, f = MHz) SYMBOL PARAMETER MAXMUM* UNTS TEST CONDTONS C nput Capacitance pf V CC = 5V, V = 2V C /O /O Capacitance pf V CC = 5V, V /O = 2V *Characterized but not % tested COM / ND COM / ND ND COM / ND 9

10 Specifications GAL22V Switching Waveforms NPUT or /O FEEDBACK COMBNATORAL OUTPUT Combinatorial Output VALD NPUT tpd NPUT or /O FEEDBACK REGSTERED OUTPUT VALD NPUT tsu th tco / fmax (external fdbk) Registered Output NPUT or /O FEEDBACK tdis ten OUTPUT nput or /O to Output Enable/Disable REGSTERED FEEDBACK / fmax (internal fdbk) tcf tsu fmax with Feedback tw h tw l / fm ax (w/o fdbk) Clock Width NPUT or /O FEEDBACK DRVNG SP tsu th tspr NPUT or /O FEEDBACK DRVNG AR tarw REGSTERED OUTPUT tco REGSTERED OUTPUT tar tarr Synchronous Preset Asynchronous Reset

11 Specifications GAL22V fmax Descriptions LOGC ARRAY REGSTER LOGC ARRAY REGSTER tsu tco fmax with External Feedback /(tsu+tco) Note: fmax with external feedback is calculated from measured tsu and tco LOGC ARRAY tsu + th REGSTER fmax with No Feedback Note: fmax with no feedback may be less than /(twh + twl) This is to allow for a clock duty cycle of other than 5% tcf tpd fmax with nternal Feedback /(tsu+tcf) Note: tcf is a calculated value, derived by subtracting tsu from the period of fmax w/internal feedback (tcf = /fmax - tsu) The value of tcf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above For example, the timing from clock to a combinatorial output is equal to tcf + tpd

12 Specifications GAL22V Switching Test Conditions nput Pulse Levels GND to 3V nput Rise and D-/-5/-7 5ns % 9% Fall Times D-/-5/-2/-25 2ns % 9% nput Timing Reference Levels 5V Output Timing Reference Levels 5V Output Load See Figure 3-state levels are measured 5V from steady-state active level GAL22VD- Output Load Conditions (see figure below) Test Condition R CL A 5Ω 5pF B Z to Active High at 9V 5Ω 5pF Z to Active Low at V 5Ω 5pF C Active High to Z at 9V 5Ω 5pF Active Low to Z at V 5Ω 5pF +5V Output Load Conditions (except D-) (see figure below) Test Condition R R2 CL TEST PONT R A 3Ω 39Ω 5pF B Active High 39Ω 5pF Active Low 3Ω 39Ω 5pF C Active High 39Ω 5pF Active Low 3Ω 39Ω 5pF FROM OUTPUT (O/Q) UNDER TEST Z = 5Ω, CL* +5V R FROM OUTPUT (O/Q) UNDER TEST TEST PONT R 2 C * L *C L NCLUDES TEST FXTURE AND PROBE CAPACTANCE 2

13 Specifications GAL22V Electronic Signature An electronic signature (ES) is provided in every GAL22V device t contains 6 bits of reprogrammable memory that can contain user-defined data Some uses include user D codes, revision numbers, or inventory control The signature data is always available to the user independent of the state of the security cell The electronic signature is an additional feature not present in other manufacturers' 22V devices To use the extra feature of the user-programmable electronic signature it is necessary to choose a Lattice Semiconductor 22V device type when compiling a set of logic equations n addition, many device programmers have two separate selections for the device, typically a GAL22V and a GAL22V-UES (UES = User Electronic Signature) or GAL22V-ES This allows users to maintain compatibility with existing 22V designs, while still having the option to use the GAL device's extra feature The JEDEC map for the GAL22V contains the 6 extra fuses for the electronic signature, for a total of 592 fuses However, the GAL22V device can still be programmed with a standard 22V JEDEC map (52 fuses) with any qualified device programmer Security Cell A security cell is provided in every GAL22V device to prevent unauthorized copying of the array patterns Once programmed, this cell prevents further read access to the functional bits in the device This cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is programmed The Electronic Signature is always available to the user, regardless of the state of this control cell Output Register Preload When testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations This is because certain events may occur during system operation that throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc) To test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (ie, illegal) state into the registers Then the machine can be sequenced and the outputs tested for correct next state conditions The GAL22V device includes circuitry that allows each registered output to be synchronously set either high or low Thus, any present state condition can be forced for test sequencing f necessary, approved GAL programmers capable of executing test vectors perform output register preload automatically nput Buffers GAL22V devices are designed with TTL level compatible input buffers These buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar TTL devices The input and /O pins also have built-in active pull-ups As a result, floating inputs will float to a TTL high (logic ) However, Lattice Semiconductor recommends that all unused inputs and tri-stated /O pins be connected to an adjacent active input, Vcc, or ground Doing so will tend to improve noise immunity and reduce cc for the device (See equivalent input and /O schematics on the following page) Typical nput Current Latch-Up Protection GAL22V devices are designed with an on-board charge pump to negatively bias the substrate The negative bias is of sufficient magnitude to prevent input undershoots from causing the circuitry to latch Additionally, outputs are designed with n-channel pullups instead of the traditional p-channel pullups to eliminate any possibility of SCR induced latching nput Current (ua) Device Programming nput Voltage (Volts) GAL devices are programmed using a Lattice Semiconductorapproved Logic Programmer, available from a number of manufacturers (see the the GAL Development Tools section) Complete programming of the device takes only a few seconds Erasing of the device is transparent to the user, and is done automatically as part of the programming cycle 3

14 Specifications GAL22V Power-Up Reset Vcc Vcc (min) tsu twl NTERNAL REGSTER Q - OUTPUT tpr nternal Register Reset to Logic "" ACTVE LOW OUTPUT REGSTER Device Pin Reset to Logic "" ACTVE HGH OUTPUT REGSTER Device Pin Reset to Logic "" Circuitry within the GAL22V provides a reset signal to all registers during power-up All internal registers will have their Q outputs set low after a specified time (tpr, µs MAX) As a result, the state on the registered output pins (if they are enabled) will be either high or low on power-up, depending on the programmed polarity of the output pins This feature can greatly simplify state machine design by providing a known state on power-up The timing diagram for power-up is shown below Because of the asynchronous nature of system power-up, some conditions must be met to guarantee a valid power-up reset of the GAL22V First, the Vcc rise must be monotonic Second, the clock input must be at static TTL level as shown in the diagram during power up The registers will reset within a maximum of tpr time As in normal system operation, avoid clocking the device until all input and feedback path setup times have been met The clock must also meet the minimum pulse width requirements nput/output Equivalent Schematics PN PN Feedback (Vref Typical = 32V) Active Pull-up Circuit Vcc Active Pull-up Circuit (Vref Typical = 32V) Vcc ESD Protection Circuit Vref Vcc Tri-State Control Vcc Vref PN Data Output PN ESD Protection Circuit Feedback (To nput Buffer) Typical nput Typical Output

15 Specifications GAL22V GAL22VD-/-5/-7/-L (PLCC): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc Normalized Tpd Normalized Tpd RSE RSE Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp RSE Normalized Tco Normalized Tco RSE Normalized T Normalized T su RSE RSE Temperature (deg C) Temperature (deg C) Temperature (deg C) 25 Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) - -2 RSE Delta Tco (ns) RSE Number of Outputs Switching Number of Outputs Switching 2 Delta Tpd vs Output Loading 2 Delta Tco vs Output Loading Delta Tpd (ns) RSE Delta Tco (ns) RSE Output Loading (pf) Output Loading (pf) 3 5

16 Specifications GAL22V GAL22VD-/-5/-7/-L (PLCC): Typical AC and DC Characteristic Diagrams Vol vs ol Voh vs oh Voh vs oh Vol (V) 2 Voh (V) 3 2 Voh (V) ol (ma) oh(ma) oh(ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq Normalized cc 9 Normalized cc 2 9 Normalized cc Temperature (deg C) Frequency (MHz) 6 Delta cc vs Vin ( input) nput Clamp (Vik) 5 2 Delta cc (ma) Vin (V) ik (ma) Vik (V) 6

17 Specifications GAL22V GAL22VD-7/L (PDP): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc 2 Normalized Tsu vs Vcc Normalized Tpd 5 95 RSE Normalized Tco 5 RSE Normalized Tsu 9 RSE Normalized Tpd vs Temp 2 Normalized Tco vs Temp 3 Normalized Tsu vs Temp Normalized Tpd 2 9 RSE Normalized Tco 9 RSE Normalized Tsu 2 9 RSE Temperature (deg C) Temperature (deg C) Temperature (deg C) Delta Tpd (ns) Delta Tpd vs # of Outputs Switching RSE Number of Outputs Switching Delta Tco (ns) Delta Tco vs # of Outputs Switching RSE Number of Outputs Switching 2 Delta Tpd vs Output Loading 2 Delta Tco vs Output Loading Delta Tpd (ns) RSE Delta Tco (ns) RSE Output Loading (pf) Output Loading (pf) 7

18 Specifications GAL22V GAL22VD-7/L (PDP): Typical AC and DC Characteristic Diagrams Vol (V) Vol vs ol ol (ma) Voh (V) Voh vs oh oh (ma) Voh (V) Voh vs oh oh (ma) 5 Normalized cc vs Vcc 3 Normalized cc vs Temp 2 Normalized cc vs Freq 2 5 Normalized cc 5 95 Normalized cc 9 Normalized cc Temperature (deg C) Frequency (MHz) Delta cc (ma) Delta sb vs Vin ( input) Vin (V) ik (ma) nput Clamp (Vik) Vik (V)

19 Specifications GAL22V GAL22VD-Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams Normalized Tpd vs Vcc Normalized Tco vs Vcc Normalized Tsu vs Vcc 5 2 Normalized Tpd 5 95 RSE Normalized Tco 5 95 RSE Normalized Tsu 9 RSE Normalized Tpd vs Temp Normalized Tco vs Temp Normalized Tsu vs Temp Normalized Tpd 2 9 RSE Temperature (deg C) Normalized Tco 2 9 RSE Temperature (deg C) Normalized Tsu RSE Temperature (deg C) Delta Tpd vs # of Outputs Switching Delta Tco vs # of Outputs Switching Delta Tpd (ns) - - RSE Delta Tco (ns) - - RSE Number of Outputs Switching Number of Outputs Switching 2 Delta Tpd vs Output Loading 2 Delta Tco vs Output Loading Delta Tpd (ns) RSE Delta Tco (ns) 6 2 RSE Output Loading (pf) Output Loading (pf) 9

20 Specifications GAL22V GAL22VD-Q and Slower (L & Q): Typical AC and DC Characteristic Diagrams Vol (V) 6 2 Vol vs ol ol (ma) Voh (V) Voh vs oh 2 6 oh (ma) Voh (V) Voh vs oh oh (ma) Normalized cc vs Vcc Normalized cc vs Temp Normalized cc vs Freq 2 35 Normalized cc 9 Normalized cc Normalized cc Temperature (deg C) Frequency (MHz) Delta cc (ma) Delta cc vs Vin ( input) Vin (V) ik (ma) nput Clamp (Vik) Vik (V) 2

21 Specifications GAL22V Notes 2