TOSHIBA MOS MEMORY PRODUCTS TMM20 I 6AP- I 0 BLOCK DIAGRAM ~,--- 0: UJ A, ~ ~ 0 f=> U UJ -::"" ~ ;: 0. A, v- A 7. ::f~ ~"I '""
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1 MOS MEMORY PRODUCTS 2,048 WORD x 8 BT STATC RAM TMM20 6AP-90 TMM20 6AP- 0 DESCRPTON TMM20 6AP- 2 TMM20 6AP- 5 The TMM2016AP is a 16,384 bits high speed and low power static random access memory organized as 2,048 words by 8 bits and operates from a single 5V supply. Toshiba's high performance device technology provides both high speed and low power features with a maximum access time of 90ns/100ns/ 120ns/150ns and maximum operating current of 80mA/65mA/65mA/65mA. When CS is a logical high, the device is placed in a low power standby mode in which maximum standby current is 7mA. Thus the TMM2016AP is most suitable for use in microcomputer peripheral memory where the low power applications are required. The TMM2016AP is fabricated with ion implanted N channel silicon gate MOS technology for high performance and high reliability. FEATURES Access Time and Current l Access Part Number Time (Max.1 J Operating Standby Current Current (Max. (Max.) TMM2016Ap 90 90ns SOmA 7mA TMM2016Ap l0 loons 65mA 7mA TMM2016AP ns 65mA 7mA 'TMiv12016AP ns 65mA 7mA Single 5V Power Supply Fully Static Operation Power Down Feature: CS Output Buffer Control: OE Three Stage Outputs All nputs and Outputs: Directly TTL Compatible nputs protected: All inputs have prtoection against static charge. PN CONNECTON Vee A, A8 As A9 A4 WE A3 DE AjO CS 1/0, 1/07 1/02 lio, 1/ GND 1/04 PN NAMES SYMBOL Ao A3 A4 A,o CS WE /O, /O, OE Vee GND NAME Column Address nputs Row Address nputs Chip Select nput Write Enable nput Data nput/output Output Enable nput Power (5V) Ground BLOCK DAGRAM A 4 v-,--- A 5 A, A 7 A, v- A 9 0- v- 0: 0 UJ U UJ 0 0 f=> -::"" ;: 0 0: u ::f " '"" MEMORY CELL ARRAY (128 x 16 x 8) Vee ----a GND 1t... 1/0 CRCUT... COLUMN DECODER ffff == 1111
2 MAXMUM RATNGS SYMBOL TEM RATNG UNT Vcc Power Supply Voltage V V'N, VOUT npul/output Voltage V Topr. Operating Temperature 0-70 c Tstg. Storage Temperature c Tsolder Soldering Temperature Time 260' 10 c. sec Po Power Dissipation (Ta 70 C) 1.0 W D.C. RECOMMENDED OPERATNG CONDTONS (Ta = 0-70 C) SYMBOL PARAMETER MN. TYP. MAX. UNT VH nput High Voltage Vcc +1.0 V V,L nput Low Voltage V Vcc Supply Voltage V D.C. CHARACTERSTCS (Ta = 0-70 C, Vee = 5.0V ± 10"10) SYMBOL PARAMETER CONDTONS MN. TYP. MAX. UNT,L nput Leakage Current V,N OV - 5.5V /1A VOH Output High Voltage lout -1.0mA V VOL Output Low Voltage lout 2.1mA V LO Output Leakage Current CS V,H orwe V,L or OE V'H, VOUT OV - 5.5V /1A ssp Peak Power-on Current CS Vcc, lout OmA ma ss Standby Current CS V'H, lout OmA ma CC1 Operating Current TMM20 16AP l 0/ 12/ 15 CS V'L, lout OmA ma CC2 Operating Current TMM2016AP 90 CS V'L, lout OmA ma CAPACTANCE* (Ta = 25 C, f = 1.0 MHz) i SYMBOL i PARAMETER CONDTONS MAX. UNT C'N nput Capacitance V,N A.C. Ground 5 pf COUT Output Capacitance V,N A.C. Ground 10 pf.. Note: This parameter is periodically sampled and is not 100% tested
3 A.C. CHARACTERSTCS (Ta = 0 70 C. Vee = 5V ± 10",{,) READ CYCLE MM201:O_ 16AP-10 jtmm2016ap-12 TMM2015AP-15 SYMBOL PARAMETER UNT M.N. MAX. MN. MAX. i MN. MAX. MN. MAX. trc Read Cycle Time ns tacc Address Access Time ns tco Chip Select Access Ti me ns toe Output Enable Time , - 55 ns Output Data Hold Time from toh Address Change ns tclz Output in Low-Z from CS ns tchz Output in High-Z from CS ns tolz Output in Low-Z from OE ns tohz Output in High-Z from OE ns tpu Chip Selection to Power Up Time - -b ns tpd ChipDeselection to Power Down Time ns WRTE CYCLE TMM2015AP-90 TMM2016AP-10 TMM2016AP-12 TMM2016AP-15 SYMBOLl PARAMETER UNT MN. MAX. MN. MAX. MN. MAX. MN. MAX_ f.--twc Write Cycle Time ns tcw Chip Selection to End of Write ns f.--- tas Address Set up Time ns f--.- twp Write Pulse Width ns --f----- Write Recovery Time twr a - a ns tos Data Set up Time ns toh Data Hold Time a ns twlz Output in Low-Z from WE ns - Output in High-Z from WE L - 50 ns A.C. TEST CONDTONS nput Pulse Leveis nput Rise and Fall Time o -3.5V 10 ns nput and Output Reference Le')els 1.5V Output Load 1 TTL Gate & CL loop F 79
4 TMNG WAVEFORMS (A) READ CYCLE [1] (1) RC ADDRESSES tacc \\\\\\\\\\ toe HGH MPEDANCE DOUT UNKNOWN toh OUTPUT DATA VALD to HZ ljllil HGH MPEDANCE WMN. (B) READ CYCLE [2](1)(21 Supply Current :::mnm"t UNKNOWN OUTPUT DATA VAllO (C) WRTE CYCLE [1] (31 twc ADDRESSES DOUT
5 (D) WRTE CYCLE [2]13) twe ADDRESSES DOUT Note: (1) The WE is high for read cycle. Device is continuously selected, CS = VL in read cycle [11. (2) All address are valid perior to or simultaneously with CS transistions. (3) A write occurs during the overlap of low CS and low WE. The tcw is specified as the time from the chip selection to end of write in write cycle, and the twp is specified as the overlap time of low CS and low WE. OE is allowed to be low or high level in write cycle. f the 6E is high, the output buffers remain in a high impedance state in this period. (4) f the CS low transistion occurs simultaneously with or latter to the WE low transition, the output buffers remain in a high impedance state in this period. (5) f the CS high transition occurs simultaneously with WE high transition, the output buffers remain in a high impedance state in this period. These parameters are specified as follows and measured by using the load shown in Fig. 1. (A) tclz, tolz, twlz.. (8) tchz, tohz. twhz.. Output Enable Time Output Disable Time (;S, OE r f-- l- A) HGH MPEDANCE SV O.lSV O.lSV 18) O.lSV GH MPEDANCE O.lSV 1.8Kn DOUTo---r----- CL =30pF r 1.0Kn Fig. 1 Output load condition for enable and disable time measurement. 81
6 OUTLNE DRAWNGS Unit: mm ::c:::] X 32.4 MAX ± ±O.15 «:; TYP. t::!:t 17.4 MAX. O.5±O.15 Note: Each lead pitch is 2.S4mm. All leads are located within O.25mm of their true longitudinal position with respect to No.1 and No, 24 leads. Note: Toshiba does not assume any responsibility for use of any circuitry described; no circuit patent licenses are implied, and Toshiba reserves the right, at any time without notice, to change said circuitry. Feb., 1983 Toshiba Corporation
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