TMS JL. TMS JL. TMS 27L08-45 JL 1024-WORD BY 8-BIT ERASABLE PROGRAMMABLE READ-ONLY MEMORIES
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1 MOS LS 124-WORD BY 8-BT ERASABLE PROGRAMMABLE READ-ONLY MEMORES DECEMBER 1979-REVSED MAY X 8 Organization All nputs and Outputs Fully TTL Compatible Static Operation (No Clocks, l'jo Refresh) Performance Ranges: Max Access TMS ns TMS TMS 27L State Outputs for OR-Ties N-Channel Silicon-Gate Technology 8-Bit Output for Use in Microprocessor Based Systems Min Cycle 35 ns Low Power on TMS 27L mw (Typ) 1% Power Supply Tolerance (TMS 27L8-45 Only) Plug-Compatible Pin-Outs Allowing nterchangeability/upgrade to 16K With Minimum Board Change A7 A6 A5 A4 A3 A2 A1 AO Vss PN CERPAK DUAL-N-LNE PACKAGE (TOPVEWl vee AS A9 Vas es(pe) Voo Program description The TMS , TMS , and TMS 27L8-45 JL are ultra-violet light-erasable, electrically programmable read only memories. They have 8,192 bits organized as 124 words of 8-bit length. The devices are fabricated using N-channel silicon-gate technology for high speed and simple interface with MOS and bipolar circuits. All inputs (including program data inputs) can be driven by Series 74 TTL circuits without the use of external pull-up resistors. Each output can drive one Series 74 or 74LS TL circuit without external resistors. The TMS 27L8 guarantees 2 mv de noise immunity in the high state and 25 mv in the low state. The data outputs for the TMS , TMS , and TMS 27L8-45 are three-state for OR-tying multiple devices on a common bus. These EPROMs are designed for high-density fixed-memory applications where fast turn arounds and/or program changes are required. They are supplied in a 24-pin dual-in-line ceramic cerdip (JL suffix) package designed for insertion in mounting-hole rows on 6-mil (15.2 mm) centers. They are designed for operation from e to 7 e. operation (read mode) address (AO-A9) The address-valid interval determines the device cycle time. The 1-bit positive-logic address is decoded on-chip to select one of the 124 words of 8-bit length in the memory array. AO is the least-significant bit and A9 is the most-significant bit of the word address. chip select, program enable [CS (PE)] When the chip select is low, all eight outputs are enabled and the eight-bit addressed word can be read. When the chip select is high, all eight outputs are in a high-impedance state. 16
2 TMS JL. TMS JL. TMS 27L8-45 JL data out ( 1-8) The chip must be selected before the eight-bit output word can be read. Data will remain valid until the address is changed or the chip is deselected. When deselected, the three-state outputs are in a high-impedance state. The outputs will drive TTL circuits without external components. program The program pin must be held below Vee in the read mode. operation (program mode) erase Before programming, the TMS , TMS , or TMS 27L8-45 is erased by exposing the chip through the transparent lid to high-intensity ultraviolet light (wavelength 2537 angstroms). The recommended minimum exposure dose ( = UV intensity x exposure time) is fifteen watt-seconds per square centimeter. Thus, a typical 1 2 milliwatt per square centimeter, filterless UV lamp will erase the device in a minimum of 21 minutes. The lamp should be located about 2.5 centimeters above the chip during erasure. After erasure, all bits are in the high state. programming Programming consists of successively depositing a small amount of charge to a selected memory cell that is to be changed from the erased high state to the low state. A low can be changed to a high only by erasure. Programming is normally accomplished on a PROM or EPROM Programmer, an example of which is Tl's Universal PROM Programming Module in conjunction with the 99 prototyping system. Programming must be done at room temperature (25 C) only. to start programming (see program cycle timing diagram) First bring the CS (PE) pin to +12 V to disable the outputs and convert them to inputs. This pin is held high for the duration of the programming sequence. The first word to be programmed is addressed (it is customary to begin with the "O" address) and the data to be stored is placed on the 1-8 program inputs. Then a +25 V program pulse is applied to the program pin. After.1 to 1. milliseconds the program pin is brought back to O V. After at least one microsecond the word address is sequentially changed to the next location, the new data is set up and the program pulse is applied. Programming continues in this manner until all words have been programmed. This constitutes one of N program loops. The entire sequence is then repeated N times with N x tw(pr);;. 1 ms. Thus, if tw(pr) = 1 ms; then N = 1, the minimum number of program loops required to program the EPROM. to stop programming After cycling through the N program loops, the last program pulse is brought to O V, then Program Enable [CS (PE)] is brought to V1L which takes the device out of the program mode. The data supplied by the programmer must be removed before the address is changed since the program inputs are now data outputs and change of address could cause a voltage conflict on the output buffer. 1-8 outputs are invalid up to 1 microseconds after the program enable pin is brought from V1H(PE) to V1L- 161
3 logic symbol t EPROM 124x8 (8) AO (7) A1 (6) l9l a1 A'v A2 (1) 2 (5) A'v A3 (11) (4) 3 A4 (13) 4 (3) A123 A5 (14) 5 (2) A6 A'::;J (15) 6 (1) A7 (16) Q7 (23) A 'v AS 1171 (22) A 'v as A9 9 cs (2) t This symbol is in accordance with EEE Std 91 /ANS Y32.14 and recent decisions by EEE and EC. See explanation on page 289. absolute maximum ratings over operating free-air temperature range (unless otherwise noted)* Supply voltage, Vee (see Note 1) Supply voltage, Voo (see Note 1) Supply voltage, Vss (see note 1) All input voltage (except program) (see Note 1 )... Program input (see Note 1) -.3to15V -.3to2V -.3to15V -.3to2V -.3to35V Output voltage (operating, with respect to Vss) to 7V Operating free-air temperature range... e to 1 e Storage temperature range e to 12 5 e NOTE 1: Under absolute maximum ratings, voltage values are with respect to the most-negative supply voltage, Vee lsubstrate). unless otherwise noted. Throughout the remainder of this data sheet, voltage values are with respect to V55. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions beyond those indicated in the "Recommended Operating Conditions" section of this specification is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 162 POST OFFCE BOX DALLAS, TEXAS 75265
4 recommended operating conditions TMS278-35, TMS TMS27L8-45 PARAMETER UNT MN NOM MAX MN NOM MAX Supply voltage, Vee V Supply voltage, V cc V Supply voltage, Voo V Supply voltage, Vss V High-level input voltage, V1H (except program and program enable) 2.4 Vcc Vcc+1 V High-level program enable input voltage, V1HPEl V High-level program input voltage, V1H(PR) V Low-level input voltage, V1L (except program) Vss.65 Vss.65 V Low-level program input voltage, V1L(PR) Note: V1L(PR) max s; V1H(PR) -25 V Vss 1 Vss 1 V H1gn-1evel program pulse input current \sink), l1h(pr) 4 4 ma Low-level program pusle input current (source), l1l(pr) 3 3 ma Operating free-air temperature, TA 7 7 c electrical characteristics over full ranges of recommended operating conditions (unless otherwise noted) TMS , PARAMETER TEST CONDTONS TMS TMS 27L8-45 UNT MN TYPt MAX MN TYPt MAX VoH High-level output voltage OH = -1 µa OH = -1 ma V Vol Low-level output voltage OL = 1.6 ma.45.4 V 11 nput current (leakage) V1 = V to 5.25 V µa lo Output current (leakage) CS(PE) = 5 V, Vo =.4 V to 5.25 V µa lee Supply current from Vee All inputs high, ma ice Supply current from V cc CS(PE) = 5 V, ma loo Supply current from Voo TA = C (worst case) ma TA = 7 C 8 35 PD(AV) Power Dissipation TA= C cs= ov mw TA= C CS = +5 V t All typical values are at TA = 25 C and nominal voltages. capacitance over recommended supply voltage range and operating free-air temperature range, f = 1 MHz PARAMETER TYPt MAX UNT Ci nput capacitance 4 6 pf Co Output capacitance 8 12 pf t All typical values are at TA = 25 C and nominal voltages. 163
5 switching characteristics over recommended supply voltage range and operating free-air temperature range PARAMETER TEST CONDTONS ta(adl Access time from address ta(cs) Access time from CS CL= 1 pf tv(a) Output data valid after address change 1 Series 74 TTL load tdis Output disable time T tf(cs), tf(adl = 2 ns tc(rd) Read cycle time 3 TMS MN MAX TMS278 TMS27L8 MN MAX UNT 12 ns ns 12 ns t Value calculated from.5 volt delta to measured output level. TA 25 C program characteristics over recommended supply voltage range tw(pr) T T(PR) tsu(ad) tsu(da) tsu(pe) th(ad) th(ad,da R) th(da) th(pe) tcl,adx PARAMETER Pulse width, program pulse Transition times (except program pulse) Transition times, program pulse Address setup time Data setup time l'rogram enable setup tome Address hold time Address hold time after program input data stopped Data hold time l"rog ram enable hold time Delay time, CS(PE) low to address change MN MAX UNT.1 1 ms 2 ns 5 2 ns 1 µ.s 1 µ.s 1 µ.s 1 ns ns 1 ns 5 ns ns PARAMETER MEASUREMENT NFORMATON V 2.9 V "'"~i::~: J' '-,oo fl 1 CL 1pF FGURE 1 - TYPCAL OUTPUT LOAD CRCUT 164
6 TMS JL. TMS JL, TMS 27L8-45 JL read cycle timing tc(rd) ADDRESSES ADDRESSES VALD ADDRESSES VALD tc(rd) v'"ylflf+ l = V1L V1H \ CS(PE) 1 V1L --- ta(ad) ta(cs) j { l tv(a)-1..- VoH Q1-Q8 Hi-Z VALD VALD Nomuot VOL t --' 1--- dis }-"',_ program cycle timing CS (PE)* ADDRESSES t OF N* PROGRAM LOOPS i V1H(PJ.1,:, /, :::,i.. V1L ;.-, tsu(pe) th(pe) --+j! -ti r- tcl, ad x V1H V1L AOD",S O ADDmSL..,o,, ( ADDms,o,s O -m... th(ad) --, ~ htsulad) th(adl..,...-i- r;-tsu(ad) ' f- tw(pr) --J i 1-- tw(pr) --J 1-- tw(pr --+l j ~-- ~.:::::, 1! 4Lr-tl t,uldal -j j.- th(dal--, -ft [-_t,u(da) th(dal~ -=!"'" l,..t,u(dal th(da)~ th(ad,dar ~:iu~~~m : 1 ~3 1_N_Pu_T -JX NPUT )t NPUT EPUT *CS (PE) is at +12 V through N program loops where N;;;, 1 ms/tw (PR). NOTE: Q1-Q8 outputs are invalid up to 1 µsec after programming [cs(pe) goes low]. All timing reference points in this data sheet (inputs and outputs) are 9% points. 165
7 TYPCAL TMS 27L8-45 CHARACTERSTCS DEVCE POWER DSSPATON vs TEMPERATURE 8 4 CURRENT vs TEMPERATURE 7 ~ 6 E C l 5 = 4 i ~ ::._4)(1rv,urv, --Rt case ~nditions --r:::: - TYPtc4 :--- l-65% --~~Cle - 3 E ~ u = 2 > ii (/J " = 1 1cclMAX) CS=s v TA - Free-Air Tempafature - C TA - Free-Air Temperature - 'C :c > 4 & a 3.6 > & = = ~ 3.! a.8.6.j >.4.2 STATC OUTPUT VOLTAGE vs OUTPUT CURRENT ~ ~ TYPCAL CONDTONS ~ - i,.., lol - Output Current - ma ~ ~ 4 5 ~. ACCESS TME vs TEMPERATURE 4~-~-~--~-~-~--~-~ 3 E j: 2 i " ;/. 1 TYPCAL talcs) o~-~-~--~-~-~--~-~ TA - Free-Air Temperature - C 166
TMS27C BIT UV ERASABLE PROGRAMMABLE READ-ONLY MEMORY TMS27PC BIT PROGRAMMABLE READ-ONLY MEMORY
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NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM
NM27C040 4,194,304-Bit (512K x 8) High Performance CMOS EPROM General Description The NM27C040 is a high performance, 4,194,304-bit Electrically Programmable UV Erasable Read Only Memory. It is organized
10-Bit µp-compatible D/A converter
DESCRIPTION The is a microprocessor-compatible monolithic 10-bit digital-to-analog converter subsystem. This device offers 10-bit resolution and ±0.1% accuracy and monotonicity guaranteed over full operating
CD54HC273, CD74HC273, CD54HCT273, CD74HCT273
Data sheet acquired from Harris Semiconductor SCHS174B February 1998 - Revised May 2003 CD54HC273, CD74HC273, CD54HCT273, CD74HCT273 High-Speed CMOS Logic Octal D-Type Flip-Flop with Reset [ /Title (CD74
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
54ACT11020, 74ACT11020 DUAL 4-INPUT POSITIVE-NAND GATES
Inputs Are TTL-Voltage Compatible Flow-Through Architecture to Optimize PCB Layout Center-Pin V CC and GND Configurations to Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS)
SN54LS06, SN74LS06, SN74LS16 HEX INVERTER BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
AS4C256K16E0. 5V 256K 16 CMOS DRAM (EDO) Features. Pin designation. Pin arrangement. Selection guide
5V 256K 16 CMOS DRAM (EDO) Features Organization: 262,144 words 16 bits High speed - 30/35/50 ns access time - 16/18/25 ns column address access time - 7/10/10/10 ns CAS access time Low power consumption
SN5407, SN5417, SN7407, SN7417 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS SDLS032A DECEMBER 1983 REVISED NOVEMBER 1997
Converts TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays s Fully Compatible With Most TTL Circuits
4-megabit (512K x 8) Single 2.7-volt Battery-Voltage Flash Memory AT29BV040A
Features Single Supply Voltage, Range 2.7V to 3.6V Single Supply for Read and Write Software Protected Programming Fast Read Access Time 200 ns Low Power Dissipation 15 ma Active Current 50 µa CMOS Standby
Philips Semiconductors Programmable Logic Devices
DESCRIPTION The PLD is a high speed, combinatorial Programmable Logic Array. The Philips Semiconductors state-of-the-art Oxide Isolated Bipolar fabrication process is employed to produce maximum propagation
EEPROM AS8ER128K32 FUNCTIONAL BLOCK DIAGRAM. 128K x 32 Radiation Tolerant EEPROM. PIN ASSIGNMENT (Top View) AVAILABLE AS MILITARY SPECIFICATIONS
128K x 32 Radiation Tolerant EEPROM AVAILABLE AS MILITARY SPECIFICATIONS MIL-PRF-38534 FEATURES Access time of 150ns, 200ns, 250ns Operation with single 5V + 10% supply Power Dissipation: Active: 1.43
ua9637ac DUAL DIFFERENTIAL LINE RECEIVER
ua967ac Meets or Exceeds the Requirements of ANSI Standards EIA/TIA--B and EIA/TIA--B and ITU Recommendations V. and V. Operates From Single -V Power Supply Wide Common-Mode Voltage Range High Input Impedance
256K (32K x 8) OTP EPROM AT27C256R
Features Fast Read Access Time 45 ns Low-Power CMOS Operation 100 µa Max Standby 20 ma Max Active at 5 MHz JEDEC Standard Packages 28-lead PDIP 32-lead PLCC 28-lead TSOP and SOIC 5V ± 10% Supply High Reliability
SN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of ANSI EIA/TIA-232-E and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Max Transition Time
SN55451B, SN55452B, SN55453B, SN55454B SN75451B, SN75452B, SN75453B, SN75454B DUAL PERIPHERAL DRIVERS
PERIPHERAL DRIVERS FOR HIGH-CURRENT SWITCHING AT VERY HIGH SPEEDS Characterized for Use to 00 ma High-Voltage Outputs No Output Latch-Up at 0 V (After Conducting 00 ma) High-Speed Switching Circuit Flexibility
SN54LS07, SN74LS07, SN74LS17 HEX BUFFERS/DRIVERS WITH OPEN-COLLECTOR HIGH-VOLTAGE OUTPUTS
Convert TTL Voltage Levels to MOS Levels High Sink-Current Capability Clamping Diodes Simplify System Design Open-Collector Driver for Indicator Lamps and Relays description These hex buffers/drivers feature
HIGH-PERFORMANCE CMOS BUS TRANSCEIVERS
Integrated Device Technology, Inc. HIGH-PERFORMAE CMOS BUS TRANSCEIVERS IDT54/74FCT86A/B IDT54/74FCT863A/B FEATURES: Equivalent to AMD s Am2986-64 bipolar registers in pinout/function, speed and output
SN54HC373, SN74HC373 OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
Eight High-Current Latches in a Single Package High-Current -State True s Can Drive up to LSTTL Loads Full Parallel Access for Loading Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline
6-Bit A/D converter (parallel outputs)
DESCRIPTION The is a low cost, complete successive-approximation analog-to-digital (A/D) converter, fabricated using Bipolar/I L technology. With an external reference voltage, the will accept input voltages
A23W9308. Document Title 524,288 X 8 BIT CMOS MASK ROM. Revision History. Rev. No. History Issue Date Remark
Preliminary 524,288 X 8 BIT CMOS MASK ROM Document Title 524,288 X 8 BIT CMOS MASK ROM Revision History Rev. No. History Issue Date Remark 0.0 Initial issue November 2, 1999 Preliminary PRELIMINARY (November,
DS in-1 Low Voltage Silicon Delay Line
3-in-1 Low Voltage Silicon Delay Line www.dalsemi.com FEATURES All-silicon timing circuit Three independent buffered delays Initial delay tolerance ±1.5 ns Stable and precise over temperature and voltage
UT54LVDS032 Quad Receiver Advanced Data Sheet
Standard Products UT54LVDS032 Quad Receiver Advanced Data Sheet December 22,1999 FEATURES >155.5 Mbps (77.7 MHz) switching rates +340mV differential signaling 5 V power supply Ultra low power CMOS technology
SN75150 DUAL LINE DRIVER
Meets or Exceeds the Requirement of TIA/EIA-232-F and ITU Recommendation V.28 Withstands Sustained Output Short Circuit to Any Low-Impedance Voltage Between 25 V and 25 V 2-µs Maximum Transition Time Through
CMOS STATIC RAM 1 MEG (128K x 8-BIT)
CMOS STATIC RAM 1 MEG (12K x -BIT) IDT71024 Integrated Device Technology, Inc. FEATURES: 12K x advanced high-speed CMOS static RAM Commercial (0 to 70 C), Industrial (-40 to 5 C) and Military (-55 to 125
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
IS62C64 8K x 8 LOW POR CMOS STATIC RAM FEATURES CMOS low power operation 400 mw (max.) operating 25 mw (max.) standby Automatic power-down when chip is deselected TTL compatible interface levels Single
HT27C020 OTP CMOS 256K 8-Bit EPROM
OTP CMOS 256K 8-Bit EPROM Features Operating voltage: +5.0V Programming voltage V PP=12.5V±0.2V V CC=6.0V±0.2V High-reliability CMOS technology Latch-up immunity to 100mA from -1.0V to V CC+1.0V CMOS and
DS1202, DS1202S. Serial Timekeeping Chip FEATURES PIN ASSIGNMENT. ORDERING INFORMATION DS pin DIP DS1202S 16 pin SOIC DS1202S8 8 pin SOIC
DS22, DS22S Serial Timekeeping Chip FEATURES Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation 2 x 8 RAM for scratchpad data
DS1642 Nonvolatile Timekeeping RAM
www.dalsemi.com Nonvolatile Timekeeping RAM FEATURES Integrated NV SRAM, real time clock, crystal, power fail control circuit and lithium energy source Standard JEDEC bytewide 2K x 8 static RAM pinout
AD557 SPECIFICATIONS. T A = 25 C, V CC = 5 V unless otherwise noted) REV. B
SPECIFICATIONS Model Min Typ Max Unit RESOLUTION 8 Bits RELATIVE ACCURACY 0 C to 70 C ± 1/2 1 LSB Ranges 0 to 2.56 V Current Source 5 ma Sink Internal Passive Pull-Down to Ground 2 SETTLING TIME 3 0.8
NM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE Bus Interface)
NM93C56 2K-Bit Serial CMOS EEPROM (MICROWIRE Bus Interface) General Description The NM93C56 devices are 2048 bits of CMOS non-volatile electrically erasable memory divided into 28 6-bit registers. They
DS1804 NV Trimmer Potentiometer
NV Trimmer Potentiometer www.dalsemi.com FEATURES Single 100-position taper potentiometer Nonvolatile on-demand wiper storage Operates from 3V or 5V supplies Up/down, increment-controlled interface Available
P4C147 ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM
ULTRA HIGH SPEED 4K x 1 STATIC CMOS RAM FEATURES Full CMOS, 6T Cell High Speed (Equal Access and Cycle Times) 1/1/15//5 (Commercial) 15//5/35 (Military) Low Power Operation 715 mw Active 1 (Commercial)
DECODER I/O DATA CIRCUIT CONTROL CIRCUIT
32K x 8 LOW VOLTAGE CMOS STATIC RAM June 2005 FEATURES High-speed access times: -- 8, 10, 12, 15 ns Automatic power-down when chip is deselected CMOS low power operation -- 345 mw (max.) operating -- 7
UT54ACS162245SLV Schmitt CMOS 16-bit Bidirectional MultiPurpose Low Voltage Transceiver Datasheet
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M74HCT04. Hex inverter. Features. Description
Hex inverter Features High speed: t PD = 11 ns (typ.) at =4.5V Low power dissipation: I CC = 1 μa (max.) at T A =25 C Compatible with TTL outputs: V IH = 2 V (min.) V IL = 0.8 V (max) Balanced propagation
IS62WV10248EALL/BLL IS65WV10248EALL/BLL. 1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM
1Mx8 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM KEY FEATURES High-speed access time: 45ns, 55ns CMOS low power operation 36 mw (typical) operating TTL compatible interface levels Single power supply
DS1307/DS X 8 Serial Real Time Clock
DS1307/DS1308 64 X 8 Serial Real Time Clock www.dalsemi.com FEATURES Real time clock counts seconds, minutes, hours, date of the month, month, day of the week, and year with leap year compensation valid
PART TEMP RANGE PIN-PACKAGE
General Description The MAX6922/MAX6932/ multi-output, 76V, vacuum-fluorescent display (VFD) tube drivers that interface a VFD tube to a microcontroller or a VFD controller, such as the MAX6850 MAX6853.
PI3B V, Synchronous 16-Bit to 32-Bit FET Mux/DeMux NanoSwitch. Description. Features. Pin Configuration. Block Diagram.
PI363 3.3, Synchronous 6-it to 3-it FET Mux/DeMux NanoSwitch Features Near-Zero propagation delay. Ω Switches Connect etween Two Ports Packaging: - -pin 40mil Wide Thin Plastic TSSOP (A) - -pin 300mil
2M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr..15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 2,097,152-bit high-speed Static Random Access Memory organized as 128K(256) words
4M Async Fast SRAM. Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 1 Rev. 1.0 GENERAL DESCRIPTION The and are a 4,194,304-bit high-speed Static Random Access Memory organized as 256K(512) words
1M Async Fast SRAM. Revision History CS16FS1024(3/5/W) Rev. No. History Issue Date
Revision History Rev. No. History Issue Date 1.0 Initial issue Apr.15,2014 2.0 Add 32TSOPII-400mil pin configuration and outline May 26, 2014 3.0 Delete 128kx8 products May 22, 2015 4.0 Add part no. CS16FS10245GC(I)-12
Tel: Fax:
B Tel: 78.39.4700 Fax: 78.46.33 SPECIFICATIONS (T A = +5 C, V+ = +5 V, V = V or 5 V, all voltages measured with respect to digital common, unless otherwise noted) AD57J AD57K AD57S Model Min Typ Max Min
74ACT11374 OCTAL EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS
Eight D-Type Flip-Flops in a Single Package -State Bus Driving True s Full Parallel Access for Loading Inputs Are TTL-Voltage Compatible Flow-Through Architecture Optimizes PCB Layout Center-Pin V CC and