Test bench for evaluation of radiation hardness in Application Specific Integrated Circuits

Transcription

1 SHEP 2016 Workshop on Sensors and High Energy Physics Test bench for evaluation of radiation hardness in Application Specific Integrated Circuits Vlad Mihai PLĂCINTĂ 1,3 Lucian Nicolae COJOCARIU 1,2 1. Horia Hulubei National Institute for R&D in Physics and Nuclear Engineering 2. Stefan Cel Mare University of Suceava 3. University POLITEHNICA of Bucharest SHEP 2016 SUCEAVA

2 OUTLINE Introduction Devices under Tests Test bench arhitecture DAQ system LabVIEW GUI Irradiation procedure Test beam Conclusions and future plans SHEP 2016 SUCEAVA 1

3 Introduction Most of detectors from space applications and particle accelerator experiments use ASICs (Applications Specific Integrated Circuits) as front-end circuits to read-out the analog signals from photo-detectors; Such applications requires radiation tolerant or radiation hardened components; Even if they are radiation hardened by design (RHBD), need to be fully characterized and qualified for the worse case scenario of its target application. Examples of applications: front-end electronics of the LHCb RICH sub-detectors and space applications. SHEP 2016 SUCEAVA 2

4 Introduction Radiation induced effects can change the functionality of the components by creating changes in logic or configuration which leads to failure or at best inneficiency. Some examples of radiation induced single event effects: o Single Event Upset (SEU) => recoverable errors represented by a change of a state caused by ionizing radiation which causes one or multiple bits of information to be changed by the charge collection; o Single Event Transient (SET) => recoverable errors causes the generation of transient voltage pulse at a specific node propagated to the device output; o Single Event Function Interrupt (SEFI) => recoverable errors causes the component to reset, freeze, or goes in a unknown state; o Single Event Latch-up (SEL) => recoverable errors potentially destructive condition involving parasitic circuit elements forming a silicon controlled rectifier (SCR) which leads to high-current consumptions rates; o Single Event Gate Rupture (SEGR) => non-recoverable errors the gate dielectric is permanently damaged; o Single Event Burnout (SEB) => non-recoverable errors similar to SEL in that it generates high-current consumptions, but it can not be recovered; o Stuck Bits => non-recoverable errors when the bistable element is stuck in one state of its 2 possible states. SHEP 2016 SUCEAVA 3

5 Devices under tests MAROC3 dice snapshot MAROC3 ASIC (Multi Anode ReadOut Chip) Technology:0.35 µm SiGe BiCMOS; Package: CQFP240; Active die area:16mm 2 (4mm x 3.9mm); Power consumption: 3.5 mw/channel; Voltage supply: 3.5 V; Detector compliant: MaPMT, SiPM, RPC; Number of channels: 64; Input polarity: negative; Applications: ATLAS luminometer (LHC-CERN), MaPMT read-out in LHCb RICH sub-detectors (LHC- CERN), Double-Chooz, Memphyno, medical imaging. c-front-end-chip.html SHEP 2016 SUCEAVA 4

6 Devices under tests Graphical User Interface for configuring the ASIC, provided by the designer; 181 slow control bits are used to set the registers of the ASIC; Allow to test the DAC linearity and efficiency curves, so called S-curves. MAROC3 Test Board MAROC3 Naked DICE SHEP 2016 SUCEAVA 5

7 Devices under tests SPACIROC2 dice snapshot SPACIROC2 ASIC (Spatial Photomultiplier Array Counting and Integration ReadOut Chip) Technology:0.35 µm SiGe BiCMOS; Package: CQFP240/FPBGA144; Active die area:19mm 2 (4.6mm x 4.1mm); Power consumption: 1 mw/channel; Voltage supply: 3 V; Detector compliant: MaPMT; Number of channels: 64; Input polarity: negative; Applications: JEM-EUSO (International Space Station-ISS). oc.html SHEP 2016 SUCEAVA 6

8 Devices under tests Graphical User Interface for configuring the ASIC, provided by the designer; 891 slow control bits are used to set the registers of the ASIC; Allow to test the DAC linearity and efficiency curves, so called S-curves. SPACIROC2 Test Board (fully assembled by our group) SPACIROC2 Naked DICE SHEP 2016 SUCEAVA 7

9 Test bench architecture The pulser is used to inject a signal which simulates a signal from a detector => need to be tested in realistic conditions; All the connections from/to ASIC are about 3-5 meters length => because of radiation issues no other active part/systems need to be in the near of the DUT. SHEP 2016 SUCEAVA 8

10 DAQ system Designed around 8 bit microcontroller ATmega2560, embedded in Arduino MEGA dev board; 3 multiplexed inputs of its Atmega2560 ADC are used for supply rails measurements: main positive, analog and digital rails; (10 bit resolution=>2.5 mv per LSB) 8 multiplexed inputs of its MAX1270 ADC are used for precision measurements of the functionality parameters provided by ASIC: voltage references, DAC thresholds etc. ; (12 bit resolution=>1.22 mv per LSB) All the parameters are buffered using rail to rail input-output op-amps and RC anti-aliasing filters; Can perform power cycle of the ASIC, by enabling/disabling the output voltages on the custom SMPS; All the data and control commands are archived via UART interface at kbps; SHEP 2016 SUCEAVA 9

11 DAQ system IR Temperature Sensor in lead shielding along with its electronic readout GUI implemented in LabVIEW and used to monitor the dice temperature IR Temperature Sensor implemented using MLX SHEP 2016 SUCEAVA 10

12 LabVIEW GUI Main positive rail; Analog rail; Digital rail; Internal reference; DAC thresholds. All parameters are read at each 50 ms and displayed; Data is saved in ASCII files for later analyses; SHEP 2016 SUCEAVA 11

13 Irradiation procedure ~MAROC3~ Before /After IRRADIATION DAC s linearity S curves for one/all channels Power consumption for of ASIC Vbandgap DC voltage of Slow/Fast Shaper CHIP Temperature During IRRADIATION Threshold linearity ASIC power consumption for Vbandgap DC voltage of Slow/Fast Shaper CHIP Temperature Irradiation has to be done in steps, and after each step, a full test should be carried out. SHEP 2016 SUCEAVA 12

14 Before /After IRRADIATION SHEP Workshop on Sensors and High Energy Physics Irradiation procedure ~SPACIROC2~ DAC s linearity S curves for all channels Power consumption for the board (positive rail), ASIC digital and analogic part Vbandgap Vth_discri_pa Vth_discri_fs Vth_ki_sum During IRRADIATION Power consumption for the board (positive rail), ASIC digital and analogic part Vbandgap Vth_discri_pa Vth_discri_fs Vth_ki_sum PA_BUFF PA_BUFF Irradiation has to be done in steps, and after each step, a full test should be carried out. SHEP 2016 SUCEAVA 13

15 Test Beam Beam line 200 MeV proton beam with a flux value around 10 9 particles /cm 2 /s; 3 samples were irradiated in about 12 hours with ~ 100 krad each; DaQ system & SMPS Irradiation room using Proton Irradiation Facility from Paul Scherrer Institute, august 2016, Switzerland; SHEP 2016 SUCEAVA 14

16 Test Beam ~MAROC3 pre irradiation tests~ DAC linearity Efficiency curves Internal voltage reference Current value SHEP 2016 SUCEAVA 15

17 Test Beam ~SPACIROC2 pre irradiation tests~ 150 fc input charge SHEP 2016 SUCEAVA 16

18 Conclusions & future plans The system proved to be very reliable for our test beams; Its architecture is simple, easy to implement with respect to the application/asic constrains; For the next irradiation we plan to perform a readback of the configuration registers in order to find out if some SEU have occurred; All the results from the test beams will be published in scientific journals; For the next year we have 2 test beam sessions in Italy and Germany, which are already approved by the facility management; As future plan, we intend to design an FPGA based custom DAQ system for mode speed and reliability. Thank you for your attention! SHEP 2016 SUCEAVA 17