Radiation Test Plan for GLAST LAT TKR ASICs

Transcription

1 Page 1 of 20 GLAST LAT PROCUREMENT DOCUMENT Document # Date Effective LAT-PS /31/03 Author(s) Supersedes Riccardo Rando Hartmut Sadrozinski Subsystem/Office TKR Document Title Radiation Test Plan for the GLAST LAT TKR ASICs Gamma-ray Large Area Space Telescope (GLAST) Large Area Telescope (LAT) Tracker Radiation Test Plan for GLAST LAT TKR ASICs

2 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 2 of 20 CHANGE HISTORY LOG Revision Effective Date Description of Changes Original version

3 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 3 of PURPOSE Radiation testing of GLAST LAT TKR Front End (GTFE) and Readout Control (GTRC) chips [1-3] will be carried out as part of the Q/A process of flight parts. 2. SCOPE The GLAST LAT ASICs will be produced in Agilent 0.5 micron CMOS. Based on the predicted particle environment for the GLAST mission, testing of both TID and SEE effects are performed for both the GTFE and the GTRC ASICs of the TKR. The 60 Co dose for TID testing and the energy and fluence of heavy ions for SEE testing are given and the tests flow and procedures defined. Screening criteria are based on the analysis of acceptable failure rates. 3. DEFINITIONS 3.1 Acronyms ASIC Application Specific Integrated Circuit 60 Co Cobalt 60 FC Faraday cup GCR Galactic Cosmic Ray GLAST Gamma-ray Large Area Space Telescope IEEE Institute of Electrical and Electronics Engineers INFN Istituto Nationale di Fisica Nucleare LAT Large Area Telescope LET Linear Energy Transfer LETth Linear Energy Transfer Threshold LNL Laboratori Nationali di Legnaro MCM Multi-chip module SAA South Atlantic Anomaly SEE Single Event Effect SEL Single Event Latch-up SEU Single Event Upset SPE Solar Particle Event TIB Test interface board TID Total Ionizing Dose TKR Tracker VC Vacuum chamber 3.2 Definitions Bit Basic unit of information (0 or 1) Byte 8 Bits cm centimeter deg degree

4 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 4 of 20 ev Electron Volt km kilometer krad 1000 rad MeV Million Electron Volt mg milligram min minute rad unit of TID s, sec second y year 4. APPLICABLE DOCUMENTS Response to AO 99-OSS-03. P. Michelson et al, GLAST Large Area Telescope, Flight Investigation: An Astro-Particle Physics Partnership Exploring the High- Energy Universe., Nov SPEC-0001 GLAST Mission System Specification, CH 07, 5/02/ INFN LNL web site INFN Padova web site 4.1 References [1] LAT-SS-00168, Conceptual Design of the LAT Tracker Electronics Readout System [2] LAT-SS-00169, Conceptual Design and Specification of the GLAST Tracker Front-End Electronics (GTFE) ASIC [3] LAT-SS-00170, Conceptual Design of the GLAST Tracker Readout Controller Electronics (GTRC) ASIC [4] L.R. Rockett, IEEE Trans. Nucl. Sci. Vol 35, No. 6, 1988 [5] LAT-TD-00153, Test Plan for the Tracker Electronics [6] LAT-PS-01279, Tracker Electronics Test Plans [7] 433-SPEC-0001, GLAST Mission System Specification [8] LAT-TD-00333, SEE Test of the LAT TKR Front-End ASIC [9] LAT-TD-01172, GLAST LAT Readout Controller ASIC SEE Test at LNL [9] LAT-TD-0xxx, GLAST LAT TKR Frontend ASIC SEE Test at LNL

5 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 5 of Radiation Test Plan of GLAST LAT TKR ASICs 5.1 Devices The GLAST LAT TKR ASICs are produced in Agilent 0.5mm CMOS technology, with single event upset (SEU) hardened registers [4]. The front-end GTFE chips consist of an analog part (amplifier-shaper-threshold) and the necessary digital blocks, for digitalization, event buffering and overall control. The GTRC chips implement access and communication with the GTFE chips. Both total dose (TD) and single event effects (SEE) tests will be performed on both kind of ASICs. Total dose irradiations will be done with 60 Co, and SEE with heavy ions (H.I.). In [5] the testing procedures and the number of ASICs to test are specified: in total 7 parts for TID and 3 parts for SEE per production lot. This will be achieved by testing the 3 parts irradiated with H.I. for TID also, leaving 4 parts for 60 Co irradiation. The GTRC will be produced in one lot, and the GTFE in several (6) lots. One mini-mcm per GTFE lot will be assembled, containing 7 GTFE from the same lot. All min-mcm s will contain two GTRCs from the one flight lot. The mini-mcms have to be clearly marked with a consecutive number, the Lot number of the GTFE, the date of assembly,. The ASICs on the MCMs have to be numbered in a consistent manner. The location of the numbers is indicated in Fig Irradiations For 60 Co, on each board, one GTRC ( #2) and 4 samples of GTFE chips (odd numbers, #1,3,5,7) will be tested ( refer to Fig.1). The test flow is in the TID test sheet (appendix A). The integrated total dose per ASIC shall be 10 krad, given in four steps of 2.5 krad, ten times the expected value for a 5 year mission and more than twice the engineering safety limit. This dose shall be delivered in more than one hour, on powered and clocked chips. After irradiation accelerated aging at high temperature is not required. The tests performed before and after irradiation will be those listed in Tables 1 and 2. In addition the power drawn will be measured. A summary of the LAT specifications for TID and SEE performances can be found in [7]. The screening values are in Table 3. For H.I., one GTRC (#1) and 3 samples of GTFE chips (even numbers #2,4,6) will be tested on every board. In order to limit the fluence per ASIC to 10krad, the ASICs will be divided into two groups, A and B, which will be irradiated with different species of ions. The test flow is indicated on the SEE test sheet (Appendix B). The H.I. species, delivered fluence and TID for the SEE tests are given in Table 5. The test flow is in Table Pattern will be asserted in the data channels and the configuration registers with special attention to sensitive cells. These patterns then will be read back periodically and checked. In addition, SELs will be counted by monitoring the power lines. 5.3 Experimental Setup Testing before, during and after irradiation will be performed in the INFN laboratories located in Padova and at the INFN Legnaro Laboratory, near Padova. The experimental setup is based on a VME custom IO board for data interchange with the GTRC chips, and an interface board for conversion between the VME CMOS signals and the LVDS signals used by the LAT electronics [6]; a schematic of this setup is shown in Fig. 2. To allow the insertion

6 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 6 of 20 of the device under test (DUT) in the vacuum chamber a custom flange with two 50-pin feedthroughs and two 50 cm long Teflon cables is used, including adapters between standard (Canon) 50 pin connectors and LAT 37 pin connectors. A complete testing of DAQ functionality with these non standard fittings has to be performed prior to irradiation, without problems at the required operational frequency of 20 MHz. Power is delivered to the PWB interface board, located outside the vacuum chamber, through a custom SEL prevention circuit, based on fast comparators monitoring the voltage drop across small (R 5Ω) series resistors in the power lines. The status of the power lines (AVDDA, AVDDB and DVDD) is read out into the PC running the DAQ through a serial (RS232) connection. The program performing the tests, written in Padova and running under Linux, is based on the software developed in Santa Cruz by the SCIPP group. Test patterns are created following command-line specifications, written in the chip registers and read back after a delay, set to 10 seconds. 5.4 Testing steps The following steps are to be taken to ensure proper testing. They are part of the test flows of Appendix A and B; most of them pertain to SEE testing, as indicated. P1: Visual inspection Each mini-mcm will be examined under a microscope for missing/damage bonds. Bonds will be subjected to a light stress with a stream of dry pressurized air to ensure an appropriate resistance. Any damage bond will be completely removed and replaced. In the case this happens, a test of functionality must be performed connecting the mini-mcm directly to the TIB board (i.e., without using the VC wires and without flange). All cables and connectors must show no disconnected or faulty wire. P2: Lab Test Power and external clock will be turned on. The currents drawn by the mini-mcm and by the TIB will be checked and must agree with standard values The DAQ software will be run with delay set to 1 second and no SEU/SEL must be observed in 100 tests. P3: Parts connection (SEE only) The mini-mcm will be placed on the sample holder. The chip-side extremities of the Teflon vacuum cables will be connected to the mini-mcm and the cables will be securely tied to the sample holder in the proximity of the BUT to ensure that no mechanical solicitation could be transmitted to the mini-mcm. The flange-side extremities of the cables will be connected to the CF-160+2x50 vacuum flange. The outdoor cables will connect the TIB to the CF-160+2x50 vacuum flange. The TIF board will be connected to the COM board, and then to the SEL-prevention power-supply circuit. P4: Connection test (SEE only) Power and external clock (when needed) will be turned on. The currents drawn by the mini-mcm and by the TIB will be checked and must agree with the values measured in the laboratory.

7 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 7 of 20 The DAQ software will be run with delay set to 1 second and no SEU/SEL must be observed in 100 tests. In the case the mini-mcm behavior do not conform to expectations the module will be removed and connected directly to the TIB. If the mini-mcm works properly in this configuration, a complete electrical test of the cables-flange-cables apparatus will be performed to locate and correct the fault. Else, the testing of the mini-mcm will start again from point P1 (Visual inspection). P5: Placement of DUT in the vacuum chamber (SEE only) The sample holder will be inserted in the vacuum chamber and the flange will be in position but not sealed. The vertical position of the chip inside the VC will be checked to ensure that a correct positioning will be obtained during irradiation. The sample holder will be moved to its extreme positions to ensure that the cables are correctly placed and will cause no problems during the irradiations. P6: Functionality test prior VC sealing (SEE only) Before sealing the VC a complete test of the chips functionality will be performed. The DAQ software will be run with delay set to 1 second and no SEU/SEL must be observed in 500 tests. Then the VC will be sealed and pumps activated. P7: Beam setup(see only) During the beam setup the mini-mcm must remain outside the beam window, to ensure the chips cannot get irradiated in case a failure of the beam positioning arises. After the beam is correctly prepared and its uniformity has been measured with the dosimetry diodes, the beam will be intercepted with the FC and the mini-mcm will be put in position. The DAQ software shall be run with delay set to 10 seconds and no SEU/SEL must be observed in tests. The bit pattern will be an alternating pattern of 1 and 0. The power consumption of the mini-mcm must remain normal. P8: Irradiation and DAQ (SEE only) The FC will be removed and the fluence monitoring must show the beginning of the irradiation phase. In the REG register all enable bits (29-33) will always be set to 1, all read only status bits (22-28) will be set to the expected value of 0, while the remaining data bits (21-00) will be loaded with a pattern of alternating 0 s and 1 s. Also the SYNC register was loaded with such an alternating pattern. For each irradiation step, performed with a specific ion species, the testing will be divided into two phases: first an alternating pattern is selected and employed until half of the chosen dose is delivered, then the pattern will be changed into its complementary and the testing phase will conclude. This allows to monitor both 1 0 and 0 1 upsets for each chip; the choice of an alternating pattern instead of simpler all 1 and all 0 patterns allows us to have a clearer distinction between upsets and communication failures. In addition, two other SEU errors of the entire GTRC will be recorded: communication errors ( COM-Error ) and Single Event Functional Interrupts (SEFI s) which leaves the ASIC in a state requiring re-initialization.

8 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 8 of 20 After the observation of a sufficient number of SEUs (~100), the FC will be used to stop the beam and the software will be terminated and started again with the complementary pattern. A fluence similar to the precedent case will be delivered and then the beam will be stopped again. The irradiation and testing will be repeated, if needed, on another chip, then the sample holder will be put in the parking position, with the mini-mcm away from the beam window, and the ion species can be changed. P9: Functionality tests during and after irradiation(see only) After a cumulative fluence corresponding to a total dose 10 krad, a complete test of the chip functionality will be performed. The DAQ software will be run with delay set to 1 second and no SEU/SEL must be observed in 500 tests. After the end of the irradiation a similar test will be performed. 5.5 Irradiation Facilities For TID irradiations, the CNR-FRAE 60 Co γ source will be used. It is a spherical radiation source. The flux will be between 1 krad/hr, at a distance of 1 m and 4 krad/hr at a distance of 50 cm, which ensures a uniformity of better than 2%. For SEE testing, the SIRAD ion beam line of the INFN Laboratory in Legnaro will be used as the irradiation facility: powered by a 14 MV Tandem accelerator, this facility permits to conduct SEE experiments with ions species ranging from Li (60 MeV) to Au (300 MeV) with complete device monitoring during irradiation. The ion species to be used are listed in Table 5 for A and B ASICs, respectively. The flux will be between 100 and 15,000 ions/(cm 2 s). 5.6 Experimental procedures for 60 Co γ Irradiations TID irradiations will be performed in the 60 Co experimental room. The test sheet for TID tests (Appendix A) has to be filled out to document the testing.a wide metal table surrounds the γ source and permits to put the required setup within cm of the device under test (DUT), behind an appropriate lead shielding. The full set of tests of Table 1 is performed to check the functionality of data and control interface. The power consumption is measured and the basic analog performance of the GTFE is tested according to Table 2. The tests are performed pre-rad and post-rad after TID steps of 2.5 krad. Screening values are in Table 3. After the target dose of 10krad is reached, another complete set of tests is performed after disabling the γ source. Then the DUT is moved to the laboratory to monitor the annealing of the damage. No accelerated aging at high temperature is performed. 5.7 Experimental procedures for Heavy Ion Irradiations The test flow for the heavy ion testing is detailed in Sec. 5.5, with the screening values in Fig. 4 and test sheet in Appendix B. The DUT is placed, with the appropriate shielding on the parts that don t require irradiation, inside the vacuum chamber of the SIRAD line. The flat cables are connected thru the flanges multi-pin connectors to the interface board and then to the DAQ. The chamber is closed and the pumps are started. Once the pressure is low enough the beam is turned on

9 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 9 of 20 and the test proper begins. Different patterns are loaded into the chip registers and subsequently downloaded and checked for errors. Used patterns are: all one s, alternating one s and two s and the complementary patterns. Data are examined on line and logged for further analysis. After sufficient ions are delivered, the source is changed by the Tandem operators and the test start again with a different atomic species without having opened the vacuum chamber. The ion beams use are (Table 5) Silicon (LET Si =8.59 Mev cm 2 /mg) and Bromine (LET Br =38.6 Mev cm 2 /mg) for ASICs A and Nickel (LET Ni = 28 Mev cm 2 /mg) and Silver (LET Ag = 54.7 Mev cm 2 /mg) for ASICs B. 5.8 Screening Screened parameters and their acceptable values are given in Tables 3 and 4. They are derived from the TKR requirements Refs [2] and [3]. TID tests ensure that radiation does not lead to excessive power consumption or functional failures, or loss of efficiency or large noise increases. We expect no problems in the ASICs, because the radiation levels involved are relatively small for the ASIC technology used. Table 3 lists the screening values on the tests performed. SEE tests have been performed with registers laid out in the same technology [8], [9], [10]. Ref [9] also relates measured cross section to predicted failure rates in the LAT TKR in a 5 year mission. For SEL, the requirement is that the projected probability of any SEL failure in the LAT TRK is less than 5% in the 5 year mission. During previous testing, no latch-up was observed. For SEU, the requirement is that the projected probability of any SEU in the Configuration registers is unity in 5 years, and that the SEU rates in the Cal registers are 100x larger. The measured SEU cross sections are much below the values of Table 4.

10 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 10 of 20 GTFE # GTRC # 1 GTRC #2 MCM ID, Lot number Date Fig.1: mini-mcm for the TKR ASIC radiation testing, showing the component side with the numbering convention of the GTFE and GTRC respectively. The mini-mcm ID will be on the back-side. H.I. irradiation will be done on even GTFE #2,4,6 and GTRC #1, 60 Co will be done on odd GTFE # 1,3,5,7 and GTRC # 2.

11 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 11 of 20 Readout System for GLAST LAT TKR Radiation Tests Fig.2: Block diagram of the readout system for the TKR radiation testing.

12 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 12 of 20 Table 1: Summary of functionality tests to be performed on GTFE and GTRC chips after irradiation (TID testing). ID Name Short description TM704 GTRC Configuration Load bit pattern in GTRC configuration registers and read back. Register and Readback Repeat with complementary pattern. Both L & R chips. TM705 Selected GTFE Configuration Register Load and Readback Load bit pattern in all 5 configuration registers, one by one, and read back. Repeat with complementary pattern. Repeat using L & R GTRC chips. TM706 TM707 TM709 Broadcast GTFE Configuration Register Load and Readback GTRC Addressing Hard and Soft Reset Load bit pattern (broadcasting) in mask & DAC registers, then read back one at a time. Repeat using L & R GTRC chips. Load bit pattern in configuration registers and read back. Repeat changing the chips address code. Use all possible codes. Both L & R chips. Load non-default bit patterns in GTFE configuration registers (broadcasting). Pulse hard reset and read back, one at a time. Check for default values. Repeat with soft reset. Table 2: Summary of performance tests to be performed on GTFE and GTRC chips after irradiation (TID testing). ID Name Short description Thresh DAC Assign one GTFE ASIC output to L GTRC. TM710 Noise rate Measure noise rate on OR. Repeat with GTFE ASIC output assigned to R GTRC. TM711 TM712 TM713 Readout with Charge Injection Channel and Trigger Mask Test Threshold Test with Charge Injection Do 100 CAL-TRG-readout sequences, one for each readout buffer. Check for signal and layer- OR. Repeat with other channels (skipping bad ones). Repeat using L & R GTRC chips. Do CAL-TRG-readout sequence. Check that data and layer-or be empty. Assign GTFE output to L a GTRC. Do 1000 TRG-readout sequences. Plot channel map. Repeat with GTFE ASIC output assigned to R GTRC. Cal Masks DAC 10 0 Enable all Nonadjacent Pattern. Cycle through all channels Enable all CAL Disable all TRG and Data Nonadjacent Pattern. Cycle through all channels

13 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 13 of 20 Table 3: Screening parameters and acceptance values (after 10kRad TID) ID Name Acceptance value TM704 GTRC Configuration 100 % readback Register and Readback Selected GTFE 100 % readback TM705 Configuration Register Load and Readback Broadcast GTFE 100 % readback TM706 Configuration Register Load and Readback TM707 GTRC Addressing 100 % readback TM709 Hard and Soft Reset 100 % readback TM710 Noise rate Noise rate < 100Hz per ASIC TM711 Readout Sequence 100 % readback on data and OR with Charge Injection TM712 Channel and Trigger!00% Empty data and OR (same as pre-rad) Mask Test TM713 Threshold Test with Population identical to pre-rad Charge Injection Power All 3 power lines < 20% increase in power Table 4: Screening parameters and acceptance values (SEE) Error Target Cross section SEL All ASICs σ < 3*10-5 cm 2 per device SEU Config. Reg σ < 5*10-4 cm 2 per device SEU Cal GTFE σ < 5*10-2 cm 2 per device

14 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 14 of 20 Table 5a: Particle type and fluence required for the SEE test of ASIC A. For each particle, the fluence will be delivered in two equal steps. Ion species Energy (MeV) LET (MeV cm 2 /mg) Range (um) Total fluence (ions/cm 2 ) Dose (krad) Dose after 1 st half (krad) 28 Si Br Dose at the end (krad) Table 5b: Particle type and fluence required for the SEE test of ASIC B. For each particle, the fluence will be delivered in two equal steps. Ion species Energy (MeV) LET (MeV cm 2 /mg) Range (um) Total fluence (ions/cm 2 ) Dose (krad) Dose after 1 st half (krad) 58 Ni Ag Dose at the end (krad)

15 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 15 of 20 Appendix A: Test sheet for TID testing

16 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 16 of 20 GLAST LAT TKR GTFE TID Test Sheet Board # ASIC # Test ID Date/Time Tester Value Ok? Comment Visual Lab Test Before irradiation P1 P2 CLOCK I(AVDDA) I(AVDDB) I(DVVD) DAQ Test Register single mode TM705 Register broadcasting TM706 Hard and Soft Reset TM709 CHN and TRG Mask TM712 After 2.5 krad Register single mode TM705 Register broadcasting TM706 Hard and Soft Reset TM709 CHN and TRG Mask TM712 After 5 krad Register single mode TM705 Register broadcasting TM706 Hard and Soft Reset TM709 CHN and TRG Mask TM712 After 7.5 krad Register single mode TM705 Register broadcasting TM706 Hard and Soft Reset TM709 CHN and TRG Mask TM712 [MHz] Comment: Comment: Comment: Comment:

17 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 17 of 20 After 10 krad Register single mode TM705 Register broadcasting TM706 Hard and Soft Reset TM709 CHN and TRG Mask TM712 After irradiation tests Comment: Test ID Date/Time Tester Value Ok? Comment Visual P1 Lab Test P2 CLOCK [MHz] I(AVDDA) I(AVDDB) I(DVVD) DAQ Test

18 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 18 of 20 Appendix B: Test sheet for SEE testing

19 LAT-PS Radiation Test Plan for the GLAST LAT TKR ASICs Page 19 of 20 GLAST LAT TKR ASIC SEE Test Sheet Board # ASIC # GTRC / GTFE Test ID Date/Time Tester Value Ok? Comment Visual P1 Lab Test P2 CLOCK I(AVDDA) I(AVDDB) I(DVVD) DAQ Test Connections P3 Connections Test P4 Placement in Vac Cham P5 DAQ.Test P6 Vac Cham Sealing Beam Set-up P7 Irradiations P8 Si Fluence Ni Fluence Br Fluence Ag Fluence Au Fluence Functionality Test P9 [MHz] 10 krad CLOCK [MHz] I(AVDDA) I(AVDDB) I(DVVD) DAQ Test 20 krad CLOCK [MHz] I(AVDDA) I(AVDDB) I(DVVD) DAQ Test END krad CLOCK [MHz] I(AVDDA) I(AVDDB) I(DVVD) DAQ Test Comments

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