ATLAS Upgrade SSD. ATLAS Upgrade SSD. Specifications of Electrical Measurements on SSD. Specifications of Electrical Measurements on SSD

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1 ATLAS Upgrade SSD Specifications of Electrical Measurements on SSD ATLAS Project Document No: Institute Document No. Created: 17/11/2006 Page: 1 of 7 DRAFT 2.0 Modified: Rev. No.: 2 ATLAS Upgrade SSD Specifications of Electrical Measurements on SSD ATLAS Upgrade Document no.: Contact persons: Prepared by: Hartmut F.-W. Sadrozinski, UC Santa Cruz (hartmut@scipp.ucsc.edu) Alexandre Chilingarov, Lancaster U. (a.chilingarov@lancaster.ac.uk) Kuzuhiko Hara Tsukuba U. (hara@hep.px.tsukuba.ac.jp) Checked by: Distribution List Approved by:

2 ATLAS Project Document No: Page: 2 of 8 History 22 September 2006 Order 0 draft 10 October2006 Order 1 draft HFWS, AC, 14 November 2006 Order 2 draft AC 17 November Draft 2.0 HFWS

3 ATLAS Project Document No: Page: 3 of 8 1 PURPOSE These specifications define electrical characterization of silicon strip detectors (SSD) being developed for the upgrade of the ATLAS Inner Detector. These characterizations need to be done before and after irradiations and during the annealing process. 2 SCOPE After operation of about 5-10 years at full luminosity at the LHC, the ATLAS Inner detector (ID) will have to be replaced because of radiation damage. In addition, there is a plan to upgrade the LHC with a luminosity increase. The requirements for the SSD to be developed become much more stringent, requiring a survival fluence level of about neq/cm 2, a factor of 10 increase wrt to the present LHC. Electrical characterization allows prediction of detector performance, i.e. allowable bias voltage range, and bias voltage dependence of signal and noise [1]. The proposed measurements do not replace but support the dynamic characterization of SSD with particles or laser. 3 DEFINITIONS 3.1 Acronyms 60 CO Cobalt gamma source ASIC Application Specific Integrated Circuit DUT Device under Test ID Inner Detector LCR meter Inductance-Capacitance-Resistance Meter D Dissipation factor SCT (ATLAS) SemiConductor Tracker SSD Silicon Strip Detector TID Total Ionizing Dose TKR Tracker 3.2 Definitions and Abbreviations cm centimeter krad 1000 Rad MeV Million Electron Volt MRad 10 6 Rad Rad unit of TID s, sec second y year k Boltzmann constant ev/k

4 ATLAS Project Document No: Page: 4 of 8 4 APPLICABLE DOCUMENTS 4.1 ATLAS & LHC Documents SLHC Physics: F. Gianotti, M.L. Mangano, T. Virdee, et al. CERN-TH/ (April 1, 2002) SLHC Machine: O. Bruhning et al., LHC Project Report 626SLHC 4.2 References [1] H. F.-W. Sadrozinski, A. Seiden, M. Bruzzi, Operation of Short-Strip Silicon Detectors based on p-type Wafers in the ATLAS Upgrade ID, SCIPP 05/09 [2] M. Bruzzi, Radiation Damage in Silicon Detectors for High-Energy Physics Experiments, IEEE Transaction on Nuclear Science, Vol. 48 n.4 (2001). [3] M. Moll et al., Leakage current of hadron irradiated silicon detectors material dependence, Nucl Instr Meth A 426 (1999) [4] J.A.J. Matthews et al., Bulk radiation damage in silicon detectors and implications for LHC experiments Nucl.Instr.and Meth. A 381 (1996) 338. [5] A. Chilingarov, Recommendations towards a standardisation of the macroscopic parameter measurements, RD50 Technical Note 2003/ Version 5 / [6] D. Campbell et al. Frequency and temperature dependence of the depletion voltage from CV measurements for irradiated Si detectors, Nucl Instr Meth A492 (2002) 402 [7] E. Borchi, M. Bruzzi et al, Temperature and frequency dependence of the capacitance of heavily irradiated silicon diodes, Solid State Elecronics, 42, 11, 2093 (1998). [8] M. Bruzzi, Capacitance-Voltage analysis at different temperatures in heavily irradiated silicon detectors, SCIPP 06/12, Sept [9] H.F.-W. Sadrozinski et al., Total Dose Dependence of Oxide Charge, Interstrip Capacitance and Breakdown Behavior of slhc Prototype Silicon Strip Detectors and Test Structures of the SMART Collaboration, 6th International Hiroshima Symposium on the Development and Application of Semiconductor Tracking Detectors, September 2006, Carmel, CA, USA,

5 ATLAS Project Document No: Page: 5 of 8 Specifications of Electrical Measurements on SSD 4.3 Devices Tests described below will be performed with test diodes (TD) and SSD Pre-rad 4.4 General Procedures Before irradiation the measurements should be made at room temperature (RT). The nomial current value should be corrected to 20 o C Post-rad After irradiation the measurements should be made at -10 o C. Care should always be taken to calculate the bias applied to the DUT itself. 4.5 Measurements Current - Voltage (I-V) The I-V curve should be measured from zero to maximum bias U max defined as follows. For depletion voltage U d < 450 V U max = 500 V; for 450 V < U d < 950 V U max = U d + 50 V; for U d > 950 V U max = 1000 V. If a clear breakdown develops the maximum bias should be limited by the onset of the breakdown. (The breakdown represents a steep rise with no saturation of the current with bias.) The bias rise rate should be <10V/s. Some stabilisation time (min 2 s) should be allowed after every bias change before measuring the current. The current should be measured with the grounding scheme envisaged for other measurements with this device: CCE, test beam etc. If the guard ring is not floating the current through the sensitive area of the detector should be measured in addition to the total current Equipment HV Power Supply up to 1000 V, and ammeter(s) controlled by a computer Set-up Measurement should be made via computer with temperature continuously monitored (with an accuracy not worse than 1 o C). If during the measurement the temperature changes significantly the I-V should be corrected to an average temperature Temperature dependence The leakage current I(T) should be corrected from temperature T 0 to temperature T with the formula: where E b = 1.12 ev Results 2 T Eb 1 1 ( ) ( 0 ) exp( ) 0 2 I T = I T T k T0 T The measured IV should be presented in a) the linear plot I vs. V b) the log-log plot. The average measurement temperature should be quoted. The nominal current value should be given at bias value U d + 50 V (if available). For measurements at RT this value should be corrected to 20 o C, for measurements near -10 o C to exactly -10 o C and to 20 o C.

6 ATLAS Project Document No: Page: 6 of 8 If annealing is done, it should be done at 60 o C. The current per volume value at 80 min is used to check on the fluence value F using the known values for α: Backplane Capacitance Voltage (C-V) I(20 o C, 60 o C) / Vol = α*f α n = 4.0*10-17 [A/cm] for 1 MeV neutrons α p = 2.5*10-17 [A/cm] for 26 GeV protons. Capacitance should be measured between the back plane and the sensitive area of the detector. For SSD the grounding scheme should be the same as for the I-V measurements. For TD the guard ring should be kept at the same potential as the sensitive area (if this does not lead to a breakdown) but not included in the C measurement. The current through the detector should be monitored during the C-V measurement to prevent data taking in a breakdown region Equipment Computer controlled HV source meter up to 1000V and LCR meter able to work at various frequencies including 550 Hz and10 khz. Measurements should be made via computer. The DUT temperature should be monitored with better than 1 o C accuracy Set-up Measurements at should be done at 10 khz frequency to extract U d. In addition at -10 o C the measurement should be done at 550 Hz to extract the expected shape of the CCE curve [8]. The bias rate rise and stabilisation time should be the same as in I-V measurement (see Sec ) The measurements on TD should be made in C p mode. The bias rate rise and stabilisation time should be the same as in I-V measurement (see above). The full impedance should be measured (e.g. as C p -D) to allow corrections (if necessary) for the effects of the DC bias circuit. The measurements on SSD should be made in C s -R s mode, with both C s and R s recorded Temperature dependence The dependence of U d on temperature below 0 o C is negligible (see Ref.[6]). The corrections may be needed only if due to some reasons the temperature is well above 0 o C. In this case the corrections should be made as recommended in Ref.[6]. For evaluation of the CCE curve the measurements should be performed at the frequency shown in the Table 1 [8]. Table1. Optimal frequency for CCE shape C-V measurements T [ o C] T [K] e(t)/e(rt) f [khz] Results For finding U d the C-V should be presented in log-log plot. The U d should be found from a crossing of two straight lines in this plot. See p.5 of Ref.[5] for further details. The CCE estimate should be made in a form of 1/C s curve vs. bias at both 10 khz and the optimal frequency.

7 ATLAS Project Document No: Page: 7 of Interstrip Capacitance Voltage (Cint V) Equipment Computer controlled HV source meter up to 1000V and LCR meter able to work 1 MHz. Measurements should be made via computer. The DUT temperature should be monitored with better than 1 o C accuracy Set-up Measurements at should be done at 1 MHz frequency in C s -R s mode as a function of bias voltage up to 1000 V or to break down. The bias rate rise and stabilisation time should be the same as in I-V measurement (see Sec ). The measurement should be done between a test strip (on high on the LCR meter) and three pairs of next neighbors ( connected to low on the LCR meter). The next three strips on each side should be grounded to shield to the bias ring. Refer to Fig. 1 and Ref. [9] for details. Since the measurement requiring several probes and careful corrections might not be performed below zero degree, it should be done at 0 degree or above. Fig. 1 Set up for the Cint measurement Frequency dependence Measurements should be done at 1MHz, and in addition at 100kHz and 10 khz (for control). The values at the three frequencies should be comparable Results Plot of Cint at 1MHz vs. bias voltage on linear scales. In addition, the I-V curve should be shown Interstrip Resistance Voltage (Rint V) Equipment One power supply with ammeter for biasing the SSD capable in large steps up to 100V, a second power supply to vary the voltage between -5 and +5 in 0.2 steps. A high impedance electrometer to measure the potential of the strip under test. All need to be controlled and read out with a computer. The sweep is 0.2V/s Set-up Refer to Ref. [9] for details. The biasing P.S. connects the bias to the back plane, and the ground to the bias ring. The electrometer is connected to the DC pad of the strip under test, measuring the potential V 1 relative to the

8 ATLAS Project Document No: Page: 8 of 8 ground. The pair of next neighbor strips connected together is biased by the second power supply, whose voltage V 2 is swept from -5V to +5V. The current I 1 on the strip under test is calculated from the known biasing resistor R b and the measured potential across the biasing resistor V 1 : I 1 = V 1 / R b. The interstrip resistance is then determined from the linear part of the I 1 = I 1 (V 2 ) curve Rint = 2* V 2 / I Results Linear plot I 1 vs. V 2 for at 10V, 50V and 100V bias. Calculated Rint for the three bias voltages.

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ATLAS Upgrade SSD: Specifications of the ATLAS Upgrade SSD ATLAS Project Document No: Institute Document No. Created: 30/10/2006 Page: 1 of 7 DRAFT 1.0 Modified: ATLAS Upgrade SSD Project: Specifications