Thin Silicon R&D for LC applications

Size: px

Start display at page:

Download "Thin Silicon R&D for LC applications"

Avis Gray
5 years ago
Views:

1 Thin Silicon R&D for LC applications D. Bortoletto Purdue University Status report Hybrid Pixel Detectors for LC

2 Next Linear Collider:Physic requirements Vertexing 10 µ mgev σ r φ,z(ip ) 5µ m 3 / 2 p sin θ / c b, c tagging for H bb vs cc, e + e - tth (8 jets 4- b-flavoured) 1/5 r beampipe, 1/30 pixel size, 1/3 thinner w.r.t. LHC sensors Central tracking σ 5 1 ( 1/ p ) 5 10 (GeV / c T ) M H by e + e - ZH, slepton mass 1/10 LHC, 1/6 material in tracking volume Forward tracking SUSY t-channel production σ ( 1 / p ) σ( δ ) T µ rad 4 (GeV to cos / c) 1 θ 0.99 θ

3 TESLA TDR Pixel micro-vertex r=1.5 cm -6 cm (VTX) Time Projection Chamber (TPC) provides not only good p/p but also excellent de/dx Silicon tracker (SIT) in barrel (to improve p/p) Silicon disks (FTD) and forward chamber (FCH) provide tracking in the forward region

4 LC: Pixel Vertex Detector CCD are the default option in the barrel small pixel size (20?m m ) 2 excellent spatial resolution (<5?m) Slow readout (R&D) Concern about radiation hardness (R&D) Cooling DEPFET, MAPS Stefania Xella 5 layers, 0.1%X 0 /layer Thinning SI bulk to 50?m 4 layers, 0.2%X 0 /layer

5 Hybrid Active Pixels Thin Hybrid Pixels Advantages: fast time stamping sparse data read out excellent radiation tolerance. Further improvements are needed for: point resolution,, which is currently limited by the pixel dimensions of 50 µ m 300 µ m limited by the VLSI. Advances in chip design should lead to smaller ROC Resolution be improved by using interleaved pixel cells which induce a signal on capacitively coupled read out pixels reduction in material (thin silicon) Interesting for the FTD??? Purdue is collaborating with Fermilab (J. Fast, S. Kwan, W. Wester and C. Gingu). Proposal was submitted to the NSF.

6 Interleaved pixels Work has been done by Caccia, Battaglia, Niemiec et al. Readout pixel Interleaved pixel Polyresistor readout pitch = n x pixel pitch p + n Large enough to house the VLSI front end cell Small enough for an effective sampling Structures with: 60 µ m implant width, 100 µ m pixel pitch, 200 µ m readout pitch yield resolution: r Interleaved pixels (max charge sharing): 3 µm Readout pixels (min charge sharing): 10 µm New prototypes with Pixel pitch 25 µm m x 25 µm m and 25 µm m x 50 µm m should yield improved performance

7 TESLA: Forward tracking Layout of a forward pixel layer Layout of a forward strip layer Material minimization is important

8 LC: tracking Gaseous detector (TPC- TESLA): Large many samplings/track de/dx Bruce Schumm Silicon option NLC: Small 5 samplings/track No de/dx Reduce volume of Ecal (SiW) SD thin achieves good momentum resolution 3 thin inner layers (200?m) 2 outer layers (300?m)

9 Thin silicon R&D at Purdue Technical challenges: Manufacturing of thin devices is difficult Thinning after processing is difficult Industry has expressed interest in thin silicon devices Collaboration with vendors is critical How thin? The m.i.p. signal from such a thin, 50µm, silicon sensor layer is only ~3500 e h pairs. Minimum thickness is likely to be different for pixel and strips Advances in ROC design will likely improve S/N

10 Thin silicon R&D at Purdue R&D at Purdue has started last year. We received quotes from two vendors: Sintef and Micron Sintef: minimum thickness 140 µm on 4 inch wafers Micron: 4" Thickness range from 20 μ m to 2000 μ m, 6" Thickness range from 100 μ m to 1000 μ m We have selected Micron and we are exploring both n on n and p on n options. Schedule: Thin silicon strips sensors should be available in January (p on n) Thin pixel sensors in May (n on n)

11 Thin silicon strips R&D Silicon strips sensors are fabricated with CDF L00 masks (50 μm m pitch and intermediate strips) Plan to compare: 150, 200 and 300 µ m thick strip detectors performance using the SVX4 chip developed for the so called run 2b

12 Pixel Mask Layout Masks (6 ) are fabricated and processing (oxygenation) is starting this week. Devices will be available in 3-4 months Funded by DOE ADR

13 Area is dominated by CMS pixel devices compatible with the 0.25 µ m chip

14 Circled in red the RD50 structures (diodes)

15 RAL p-on-n pixels & Micron n-on-p pad detectors P-side N-side

16 As usual diodes and other test structure for process control

CMS Radiation Hard Design Guard ring design: Limits lateral extension of the depletion region Prevents breakdown at the device edge 11 guard ring design

ring Leakage Current (A) Diode S22P47 S22P29 1.E-03 S24P29 1.E-04 S4P47 1.E-05 1.E-06 φ = 6 10 14 n 1.

17 CMS Radiation Hard Design Guard ring design: Limits lateral extension of the depletion region Prevents breakdown at the device edge 11 guard ring design implemented in SINTEF 1999 submission achieved NO BREAKDOWN up to >800 V after irradiation to φ = eq /cm 2 n eq TDR A : Double open ring F: Single open ring Leakage Current (A) Diode S22P47 S22P29 1.E-03 S24P29 1.E-04 S4P47 1.E-05 1.E-06 φ = n 1.E-07 eq /cm Reverse Bias (V) n + on n option: Allows operation of un depleted sensors after type inversion N side pixel isolation P stops (CMS) SINTEF 1999 showed that F design was promising

18 Conclusions Material minimization for LC applications makes thin silicon development very interesting Thin silicon is also more rad hard Synergy between our LC interest and LHC commitments Several thin silicon strip and pixel sensors will be available to study: Mechanical stability Bump bonding feasibility Readout and geometry not yet optimal for LC application Simulation studies are needed to guide this effort and to provide input for future submissions and optimize geometry

Large Silicon Tracking Systems for ILC

Large Silicon Tracking Systems for ILC Aurore Savoy Navarro LPNHE, Universite Pierre & Marie Curie/CNRS-IN2P3 Roles Designs Main Issues Current status R&D work within SiLC R&D Collaboration Tracking Session