2 Figure 1. End view of the 6-layer silicon tracker. This is a substantial reduction in parts inventory compared to the Run IIa detector and is expect

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1 1 The D Silicon Detector for Run IIb at the Tevatron J. Fast a for the D Run IIb Silicon Group a Fermi National Accelerator Lab, M.S. 310, P.O. Box 500, Batavia, IL , USA The D collaboration has designed a new silicon tracking system for the Fermilab Tevatron Run IIb physics program, during which the experiment anticipates collecting up to 15fb ;1 of integrated luminosity ofpp collisions at 1.96TeV center of mass energy. The detector is a 6-layer barrel device employing about 2300 single sided silicon microstrip detectors. The sensors will be readout using the radiation hard SVX4 chip. The design, prototyping eort and project status of this detector will be presented. 1. INTRODUCTION The existing D silicon microstrip tracker [1] (SMT) was designed with an anticipated integrated luminosityof2fb ;1 for Run II at the Tevatron. This device consists of 4-layer barrels interleaved with disks for large coverage. In recentyears the Fermilab Run II program has been extended with a goal of delivering 15fb ;1 per experiment before data is available from the LHC experiments. This puts the Higgs within reach if it exists in the expected mass range, as well as providing access to a considerable region of phase-space for super-symmetric particles and other physics beyond the standard model [2]. The current SMT, however, cannot withstand the additional radiation dose, with the inner layers becoming inoperable at 4fb ;1. In order to maximize integrated luminosity prior to the LHC era, the D collaboration proposed a full replacement of the existing device with the detector described in this article. 2. DETECTOR DESIGN OVERVIEW The new detector design [3] was driven by several factors. First, the physics program of Run IIb is focused on high p T processes such as Higgs production and supersymmetry, hence a barrel-only design was adopted, rather than the more complex barrel and disk design currently in use. The severe radiation environment dictated the use of only single-sided silicon sensors coupled with a new version of the SVX chip, the SVX4, in the intrinsically radiation hard 0:25 mcmos process. For the Higgs search a b-tagging eciency of 65% or better is required, necessitating that the innermost layer be positioned closer to the interaction point, at 20mm vs. the current radius of 27mm. Finally, the signicantly higher instantaneous luminosity expected in Run IIb, up to cm ;2 s ;1, requires improvements in pattern recognition achieved by the addition of two silicon layers, for a total of six, with the outer radius increased from 100mm to 165mm, with the outer diameter constrained by the 180mm bore of the scintillating ber tracker. Layer 0 and 1 have only axial readout while layers 2-5 have both axial and stereo readout. An end view of the new detector is shown in Figure 1. The time constraint imposed by the expected Tevatron performance and imminent arrival of physics from the LHC require that the design be realizable on a short time scale, by the end of 2005, with a minimal shutdown period required for installation. This implies that the design must be as simple as possible consistent with the physics requirements and that a minimum of the supporting infrastructure be replaced, particularly infrastructure that can only be replaced during the detector installation shutdown. The design utilizes a minimum of component types: One stave design for the outer 4 layers Three sensor types, all single sided axial layout stereo readout by sensor rotation Four hybrid types.

2 2 Figure 1. End view of the 6-layer silicon tracker. This is a substantial reduction in parts inventory compared to the Run IIa detector and is expected to reduce production problems both in-house and at vendors. The majority of the downstream electronics will be retained with only a few modications required to accommodate the SVX4 chip which operates at 2.5V with dierential signals, as opposed to the SVX2e which operates at 5V with singleended signals. This conversion will take place on adapter cards located in the inter-cryostat gap between the central and end-cap calorimeters. The only additional modication is for the high voltage for the inner two layers where new cabling must be provided all the way tothe power supplies to allow for voltages up to 700V. 3. SILICON SENSORS Three sensor types will be used in the detector, summarized in Table 1. The layer 2-5 sensor geometry was chosen such that two sensors will t on a 6" silicon wafer. In all layers there are a total of 12 sensors along the beam axis, 6 to either side of Z=0. All sensors have intermediate oating strips to improve the single hit resolution and axial strips. Small angle stereo is achieved in layers 2-5 by rotating the sensors. Table 1 Silicon sensor parameters. Area (mm 2 ) Pitch (m) Layer width x length readout/strip x / x / x /30 The sensor design and specications draw on the extensive experience of the LHC experiments, particularly the CMS design. The sensor breakdown voltage should be well above the expected depletion voltage to allow for the over-depletion needed to recover the charge collection eciency which is expected to degrade with irradiation.

3 3 For the inner two layers the breakdown voltage is specied at > 700V while in the outer layers the specication is > 300V, which is the operational limit of the existing high voltage distribution system. The sensor specications for the inner layers require that the detector depletion voltage remains below 700V after 15 MRad of irradiation, slightly above the dose expected in the innermost silicon layer with an integrated luminosity of15fb ; Sensor radiation damage and temperature requirements The innermost layer of sensors is expected to seeupto =cm 2 1 MeV neutron equivalent radiation. To control the rate of rise of depletion voltage after type inversion the sensor temperature should be kept below 0 C. This is most critical in layer 0 and in layer 2, the innermost layers in each HV group, 700V maximum and 300V maximum, respectively. The leakage current rise with irradiation is independent of the sensor temperature during exposure, but it depends exponentially on the operating temperature, decreasing by roughly a factor of 2 for every 7 C. The leakage current must be controlled to keep the noise down to an acceptable level. Our design criteria is a signal to noise ratio, S=N >10 over the entire data taking period. This imposes a tighter temperature constraint in the inner layers than the depletion voltage: T < ;10 C for layer 0 and T < ;5 C for layer 1, the latter being the most dicult due to the on-board electronics. 4. DATA PATH, READOUT MODULES AND ELECTRONICS The sense strips of the sensors are, with the exception of layer 0, described below, connected directly to the SVX4 chip inputs. The sensor pitch issuch that the sense strips can be bonded directly to the SVX4 input pads. The total number of wire bonds required is 950K, not including the chiptohybrid bonds that will be made at the hybrid stung vendors. The data is digitized in the SVX4 chips and routed to a connector on the hybrid circuits. From there digital jumper cables carry the signals out to junction cards and twisted pair cables bring the signals from there out to the adapter cards. The adapter cards, which reside in the gap between the central and endcap calorimeters, are the interface which merges the new system into the existing Run IIa tracker electronics SVX4 readout chip The SVX4 chip is the latest in the line of readout chips designed by Fermilab and LBL engineers which includes the SVX2e used in D and the SVX3 used by CDF. It is fabricated in micron CMOS technology at Taiwan Semiconductor. The SVX4 is a common design to be used by both experiments and has readout modes suitable for both groups. The new chip operates in both \D " and \CDF" modes, emulating the SVX2e and SVX3, respectively. Each SVX4 chip has 128 inputs at a 48 micron pitch, with a 46 cell deep switched capacitor pipeline array on each input. Each pipeline cell contains the integrated charge from silicon sensor during one beam crossing. The shaping time of the amplier was matched to a 132ns spacing of beam bunches. The chip will be operated in sparsied nearest neighbor mode where only channels above threshold, typically 2:5 above the pedestal, and their two neighbors are readout. The major changes from the SVX2e chip are an operating voltage of 2.5V rather than 5V and differential low voltage rather than single-ended T- TL. First prototypes were delivered in June 2002 and have been successfully operated in both D and CDF modes. These chips have been mounted on prototype hybrids and readout modules. The chips are fully functional, with noise performance within the design specication of < 2000e ; with 40pF load. Prototype chips have been irradiated to > 20Mrad without any signs of damage, as one expects using the deep sub-micron processing Layer 0 modules and analog cables In layer 0 the readout module consists of a sensor, analog ex cable and hybrid. The hybrids in this layer are mounted beyond the active volume to reduce mass for improved impact parameter resolution, to facilitate maintenance of the

4 4 very low sensor temperature required and to keep within extremely tight space constraints. The analog ex cables, up to 465mm in length, carry the signals from the sensor strips to the hybrid electronics. The capacitance of these cables must be kept low, 30-40pF/cm, to maintain the required signal to noise ratio. They are composed of m wide gold plated copper strips on 91m pitch, with two additional traces for HV and ground. A pair of cables is laminated together with a 45m oset to allow for readout of the 50m pitch sensors. In order to achieve high yield we have one additional trace on each cable so that cables with one open trace can be accepted while still providing 100% readout. Prototype cables have been received from Dyconex (Zurich). In the second prototype run 16/27 cables were perfect, 9/27 of the cables had one open strip, and the other 2 had 2 shorts or opens. The additional strip improves the yield from 60% to 93%. There are a total of 144 modules in the detector, with six module types used, diering only in the analog cable length Layer 1 modules In layer 1 there are 6 sensors to either side of Z=0 with each sensor instrumented with SVX4 chips. Pairs of sensors are combined with a double-ended hybrid to form modules, as shown in Figure 2. There are a total of 144 sensors in 72 modules. Figure 2. A L1 module consisting of two sensors and a 6-chip, double ended hybrid. The prototype shown has only 4 of the 6 SVX4 chips mounted Layer 2-5 modules In the outer four layers of the detector there are four modules used. All four module types use the same sensors. Two hybrids are used, one for axial modules and one for stereo modules. The hybrids only dier in a transverse oset of the SVX4 chip locations required for bonding the chips directly to the sensors. The modules closest to Z=0 use 2 sensors and a hybrid, similar to the L1 module shown above. Each sensor is readout independently with it's own set of SVX4 chips. The modules further from Z=0 have 4 sensors, with pairs of sensors ganged together at either end of the hybrid, making the readout length feeding each SVX4 chip 20cm rather than 10cm. This ganging was necessary to keep the number of readout cables within the capacity of the downstream electronics. 5. Support structure The detector will be assembled in two identical barrels, north and south, with a joint at Z=0. This allows the detector to be installed without rolling the entire D detector out of the collision hall and removing an end-cap calorimeter from the platform, all of which wouldleadtoanexcessively long shutdown period. The silicon tracker is divided into two radial regions, the inner region containing layer 0 and layer 1, and the outer region containing layers 2-5. The outer region is populated with 168 staves, 84 each in the north and south barrel assemblies. The staves, described below, are mounted between composite bulkheads located at Z=0 and Z=610mm using sapphire rods and ruby jewel bearings which are inexpensive commercially available parts with a t tolerance of +10 ;0 m. The two bulkheads are xed relative to one another by two concentric carbon ber cylinders, a single wall cylinder inside of layer 2 and a double-walled cylinder outside of layer 5. The inner region has modules bonded to crenelated cylindrical support structures, one for layer 0 and another for layer 1, described below. Short extension cylinders will span the region between the end of the main barrel assemblies at Z=610mm and the ber tracker support points at Z=830mm. Cooling manifolds will be located inside the extension cylinders.

5 5 Figure 3. End view of the layer 2-5 stave Layer 2-5 staves The layer 2-5 stave structure end view is shown in Figure 3. The stave consists of a cooled core with the stave locating features, silicon modules bonded to both sides - axial on one side, small angle stereo on the other - and carbon ber C- channels along the two edges which provide mechanical stiness. The total stave mass, including the water/glycol coolant, is estimated to be 147 grams. The primary element of the stave core is the cooling tube. It is a formed tube with a turnaround (U-bend) near Z=0 so that the inlet and outlet are both located at the Z=610mm end of the stave. The baseline design is a carbon ber laminate tube using 4 plies in a [+45 ;45] s layup with a wall thickness of 200m. Fabrication of leak-tight tubes has been problematic so an alternative tube made by heat forming 100m wall round extruded PEEK tubing is being pursued in parallel. The nished tube has a rectangular prole 1.9mm tall and 7-10mm wide. Rigid outriggers are built into the core at each sensor joint to carry the load of the sensors and hybrids to the C-channels along the length of the structure. The remaining area is lled with Rohacell 51 foam, with all of the parts bonded together with 25 ;75m Kapton skins. At each end of the stave carbon ber ange pieces tie the core, cooling nozzles, locating pins and C-channels together rigidly. In addition to providing direct cooling to the silicon and carrying the load to the C- channels, the core structure functions as a shear web between the silicon sensor planes eectively creating a sti composite panel that can hold the sensors, which have a natural bowing of 50m or more, at. This is also the structure that maintains the relative alignment of the sensor modules within the stave. The C-channels which stien the stave are designed so that the sag of the staves is kept below 60m. The channels are a 9 ply construction with a ply layup of [0,+45,-45,0 3,-45,+45,0] using Mitsubishi K1392U ber (55 gsm FAW) in Bryte EX1515 cyanate ester resin. The nished thickness of the parts is 380 ; 400m. The fabrication tolerances on these parts are rather stringent. We have achieved straightness of 50m along the edge where the C-channel meets the stave core and ange positions above the sensors and hybrids within 200m of ideal along the full 610mm length with the parts in a free state Layer 0andlayer 1 structures The inner silicon layers pose challenges both with very limited space and stringent sensor temperature constraints. The structures for each layer consist of two carbon ber shells with carbon ber cooling channels incorporated between the shells. The shells will be fabricated using Mitsubishi K13C2U carbon ber and the cooling tubes with K1392U ber. The K13C2U ber has a thermal conductivity of 600W/mK, providing a good thermal path to the cooling lines embed-

6 ded in the structure. The K1392U ber has a conductivity of 200W/mK, which provides some additional distribution of the heat along the tube length and around the tube circumference.

6 6 ded in the structure. The K1392U ber has a conductivity of 200W/mK, which provides some additional distribution of the heat along the tube length and around the tube circumference. The inner carbon ber shell in each layer has a 4- ply [0 90] s layup and is quasi-cylindrical, with 12 facets. The outer shells are crenelated structures made with a 6-ply [0 +25 ;25] s layup the shallow ply angles are required to avoid fracturing the bers in the corners of the crenelations, but they also are favorable structurally and thermally as they provide greater stiness to bending along the long axis of the structures and distribute the heat load longitudinally in layer 1, which is localized in Z at the SVX4 chip locations. Aprototype structure consisting of the two concentric shells has been built for layer 0, shown in Figure 4. The cooling tubes have a roughly 2mm x 3mm rectangular prole with rounded corners, and a 200m wall thickness made with a 4-ply [+30 ;30] s layup. Prototypes have been successfully fabricated. A new silicon tracker has been designed for the D experiment to take full advantage of the expected luminosity available from the Tevatron in the pre-lhc era. The design will enhance the b- tagging capabilities of the D detector by 40% relative to the current detector system, primarily due to the reduced inner radius of 20mm. Additional tracking layers have been added to provide adequate pattern recognition with the factor of 2.5 increase in instantaneous luminosity. Simplicity and ease of assembly are critical for the rapid development, construction and deployment required to take advantage of the opportunity for Higgs discovery by the D and CDF collaborations. REFERENCES 1. The D0 Collaboration, The D0 Silicon Tracker Technical Design Report, Fermilab D0 note 2169 (1994). 2. M. Carena, et. al, Report of the Higgs Working Group of the Tevatron Run 2 SUSY/Higgs Workshop, hep-ph/ (2000). 3. The D0 Collaboration, Run IIb Upgrade Technical Design Report, Fermilab-Pub- 02/327-E (2002). Figure 4. Prototypelayer 0 carbon ber structure 6. Conclusions

Layout and prototyping of the new ATLAS Inner Tracker for the High Luminosity LHC

Layout and prototyping of the new ATLAS Inner Tracker for the High Luminosity LHC Ankush Mitra, University of Warwick, UK on behalf of the ATLAS ITk Collaboration PSD11 : The 11th International Conference