STRH8N10. Rad-Hard 100 V, 6 A N-channel Power MOSFET. Features. Applications. Description

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1 Rad-Hard 100 V, 6 A N-channel Power MOSFET Features Datasheet - production data V DSS I D R DS(on) Q g 100 V 6 A 0.30 Ω 22 nc SMD.5 Fast switching 100% avalanche tested Hermetic package 50 krad TID SEE radiation hardened Applications Figure 1. Internal schematic diagram Satellite High reliability Description This N-channel Power MOSFET is developed with STMicroelectronics unique STripFET process. It has specifically been designed to sustain high TID and provide immunity to heavy ion effects. This Power MOSFET is fully ESCC qualified. Table 1. Device summary Order code ESCC part number Quality level Package Lead finish Mass (g) Temp. range EPPL STRH8N10S1 - Engineering model SMD.5 Gold to 150 C - STRH8N10SG 5205/023/01 ESCC flight Target February 2017 DocID Rev 8 1/18 This is information on a product in full production.

2 Contents STRH8N10 Contents 1 Electrical ratings Electrical characteristics Pre-irradiation Radiation characteristics Electrical characteristics (curves) Test circuit Package information SMD.5 package information Order code Other information Revision history /18 DocID Rev 8

3 Electrical ratings 1 Electrical ratings (T C = 25 C unless otherwise specified) Table 2. Absolute maximum ratings (pre-irradiation) Symbol Parameter Value Unit V DS (1) V GS (2) Drain-source voltage (V GS = 0) 100 V Gate-source voltage ±20 V (3) I D Drain current (continuous) at T C = 25 C 6 A I D Drain current (continuous) at T C = 100 C 4.1 A (4) I DM Drain current (pulsed) 24 A P TOT Total dissipation at T C = 25 C 62.5 W P TOT Total dissipation at T a = 25 C 2.4 W dv/dt (5) Peak diode recovery voltage slope 6.4 V/ns T stg Storage temperature -55 to 150 C T j Max. operating junction temperature 150 C 1. This rating is T J > 25 C (see Figure 10: Normalized V DSS(BR)DSS vs temperature). 2. This value is guaranteed over the full range of temperature. 3. Rated according to the R thj-case + R thc-s. 4. Pulse width limited by safe operating area. 5. I SD 6 A, di/dt 1060 A/µs, V DD = 80% V (BR)DSS Table 3. Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case 2 C/W R thj-amb Thermal resistance junction-amb 52 C/W DocID Rev 8 3/18 18

4 Electrical ratings STRH8N10 Table 4. Avalanche characteristics Symbol Parameter Value Unit I AR E (1) AS E AS E AR E AR Avalanche current, repetitive or not-repetitive (pulse width limited by Tj max) Single pulse avalanche energy (starting Tj =25 C, Id = Iar, Vdd = 50 V) Single pulse avalanche energy (starting Tj =110 C, Id = Iar, Vdd =50 V) Repetitive avalanche (Vdd = 50 V, I AR = 4 A, f = 100 khz, T J = 25 C, duty cycle = 10%) Repetitive avalanche (Vdd = 50 V, I AR = 4 A, f = 100 khz, T J = 110 C, duty cycle = 10%) 4 A 457 mj 134 mj 4.3 mj 1.4 mj 1. Maximum rating value. 4/18 DocID Rev 8

5 Electrical characteristics 2 Electrical characteristics (T CASE = 25 C unless otherwise specified). 2.1 Pre-irradiation Table 5. On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit I DSS I GSS V GS(th) R DS(on) Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) Gate threshold voltage Static drain-source on resistance 100% BV Dss 1 ma 80% BV Dss 80% BV Dss, T C = 125 C V GS = 20 V V GS = -20 V V GS = 20 V, T C = 125 C V GS = -20 V, T C = 125 C V DS = V GS, I D = 1mA V DS = V GS, I D = 1mA, T C = 125 C V DS = V GS, I D = 1mA, T C = -55 C V GS = 12 V, I D = 4 A V GS = 12 V, I D = 4 A, T C = 125 C µa na V Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance (1) C oss Output capacitance V DS = 25 V, f =1 MHz, pf V GS = 0 V Reverse transfer C rss capacitance (1) Equivalent output C oss eq. capacitance (2) V DD = 80 V, V GS = 0 V 162 pf Q g Total gate charge Q gs Gate-to-source charge V DD = 50 V, I D = 4 A, nc V GS = 12 V Gate-to-drain ( Miller ) Q gd charge R G (3) Gate input resistance f = 1MHz gate DC bias = 0 test signal level = 20 mv open drain 1. This value is guaranteed over the full range of temperature. 2. This value is defined as the ratio between the Q oss and the voltage value applied. 1.6 Ω 3. Not tested, guaranteed by process. DocID Rev 8 5/18 18

6 Electrical characteristics STRH8N10 Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max Unit t d(on) t r t d(off) t f Turn-on delay time Rise time Turn-off-delay time Fall time V DD = 50 V, I D = 4 A, R G = 4.7 Ω, V GS = 12 V ns ns ns ns Table 8. Source drain diode (1) Symbol Parameter Test conditions Min. Typ. Max Unit I SD I SDM (2) Source-drain current Source-drain current (pulsed) 6 24 A A V SD (3) Forward on voltage I SD = 8 A, V GS = 0 I SD = 8 A, V GS = 0, T C = 125 C V t rr (4) Q rr (4) I RRM (4) Reverse recovery time Reverse recovery charge Reverse recovery current I SD = 8 A, di/dt = 100 A/µs V DD = 17 V, Tj = 25 C ns µc A t rr (4) Q rr (4) I RRM (4) Reverse recovery time Reverse recovery charge Reverse recovery current I SD = 8 A, di/dt = 100 A/µs, V DD = 17 V, Tj = 150 C ns µc A 1. Refer to the Figure 16: Source drain diode. 2. Pulse width limited by safe operating area. 3. Pulsed: pulse duration = 300 µs, duty cycle 1.5% 4. Not tested in production, guaranteed by process. 6/18 DocID Rev 8

7 Radiation characteristics 3 Radiation characteristics The STMicroelectronics Rad-Hard technology renders these Power MOSFETs extremely resistant to radiative environments. Every manufacturing lot is tested with the SMD.5 package for total ionizing dose (according to ESCC Basic Specification, Window 1), and single event effects (according to MIL-STD-750E Method 1080), up to 3e+5 ions/cm² fluence. Both pre-irradiation and post-irradiation performance characteristics are tested and specified using the same circuitry and test conditions for direct comparison. (T amb = 22 ± 3 C unless otherwise specified). Total dose radiation (TID) testing One bias conditions using the SMD.5 package: V GS bias: + 15 V applied and V DS = 0 V during irradiation The following parameters are measured (see Table 9, Table 10 and Table 11): before irradiation after irradiation after 24 room temperature after C anneal Table 9. Post-irradiation on/off T J = 25 C, (Co60 γ rays 50 K Rad(Si)) Symbol Parameter Test conditions Drift values Δ Unit I DSS I GSS BV DSS Zero gate voltage drain current (V GS = 0) Gate body leakage current (V DS = 0) Drain-to-source breakdown voltage 80% BV Dss +1 µa V GS = 20 V V GS = -20 V V GS = 0, I D = 1 ma -25% V na V GS(th) Gate threshold voltage V DS = V GS, I D = 1 ma -60% / + 30% V R DS(on) Static drain-source on resistance V GS = 10 V, I D = 4 A ±10% Ω Table 10. Dynamic T J = 25 C, (Co60 γ rays 50 K Rad(Si)) Symbol Parameter Test conditions Drift values Δ Unit Q g Total gate charge -5% / + 40% Q gs Gate-source charge I G = 0.2 ma, V GS = 12 V, V DS = 50 V, I DS = 4 A ±35% Q gd Gate-drain charge -5% / + 130% nc DocID Rev 8 7/18 18

8 Radiation characteristics STRH8N10 Table 11. Source drain diode T J = 25 C, (Co60 γ rays 50 K Rad(Si)) (1) Symbol Parameter Test conditions Drift values Δ. Unit V SD (2) Forward on voltage I SD = 8 A, V GS = 0 ±2% V 1. Refer to Figure Pulsed: pulse duration = 300 µs, duty cycle 1.5% Single event effect, SOA The STMicroelectronics Rad-Hard technology renders these Power MOSFETs extremely resistant to heavy ion environments for single event effects (irradiation as per MIL-STD- 750E, method 1080 bias circuit in Figure 3.: Single event effect, bias circuit SEB and SEGR tests were performed with a fluence of 3e+5 ions/cm². The accept/reject criteria are: SEB test: drain voltage checked, trigger level is set to V ds = - 5 V. Stop condition: as soon as a SEB occurs or if the fluence reaches 3e+5 ions/cm². SEGR test: the gate current is monitored every 100 ms. A gate test is performed before and after irradiation. Stop condition: as soon as the gate current reaches 100 na (during irradiation or during PIGS test) or if the fluence reaches 3e+5 ions/cm². The results are: Single-event burnout (SEB) test :immune at 60 MeV/mg/cm2 Single-event gate rupture (SEGR) test: immune at 60 MeV/mg/cm2 within the safe operating area (SOA) given in Table 12: Single event effect (SEE), safe operating area (SOA) and Figure 2: Single event effect, SOA) Table 12. Single event effect (SEE), safe operating area (SOA) Ion Let (Mev/(mg/cm 2 ) Energy (MeV) Range (µm) V DS GS GS = -2 GS = -5 GS = -10 GS = -20 V Kr Xe /18 DocID Rev 8

9 Radiation characteristics Figure 2. Single event effect, SOA 100 Kr (32 MeV.cm²/mg, 768MeV) Xe (60 MeV.cm²/mg, 1217MeV) Vgs (V) Vds (% Vdsmax) Figure 3. Single event effect, bias circuit (a) a. Bias condition during radiation refer to Table 12: Single event effect (SEE), safe operating area (SOA). DocID Rev 8 9/18 18

10 Electrical characteristics (curves) STRH8N10 4 Electrical characteristics (curves) Figure 4. Safe operating area Figure 5. Thermal impedance Id[A] µs 1ms ms Vds[V] Figure 6. Output characteristics Figure 7. Transfer characteristics ID (A) VGS = 10 V HV33200 ID (A) VGS = 7 V VGS = 6 V VGS = 5 V VDS(V) 15 0 C 25 C -55 C VGS(V) Figure 8. Gate charge vs gate-source voltage Figure 9. Capacitance variations VGS (V) 12 VDS = 50 V ID = 8 A HV33210 C (pf) 1000 Ciss HV ID = 4 A 100 Coss 4 2 ID = 2 A 10 Crss Qg(nC) VDS(V) 10/18 DocID Rev 8

11 Electrical characteristics (curves) Figure 10. Normalized V DSS(BR)DSS vs temperature Figure 11. Static drain-source on-resistance RDS(on) (mω) VGS=12 V HV ID(A) Figure 12. Normalized gate threshold voltage vs temperature Figure 13. Normalized on-resistance vs temperature Figure 14. Source drain-diode forward characteristics VSD (V) Tj = -50 C HV Tj = 25 C Tj = 150 C ISD(A) DocID Rev 8 11/18 18

12 Test circuit STRH8N10 5 Test circuit Figure 15. Switching times test circuit for resistive load (1) 1. Max driver V GS slope = 1V/ns (no DUT) Figure 16. Source drain diode 12/18 DocID Rev 8

13 Package information 6 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 6.1 SMD.5 package information Figure 17. SMD.5 package outline Pin n 1 identification ( rev.5) DocID Rev 8 13/18 18

14 Package information STRH8N10 Table 13. SMD.5 mechanical data Dim. mm Inch Min. Typ. Max. Min. Typ. Max. A A b b b b D D E e /18 DocID Rev 8

15 Order code 7 Order code Table 14. Ordering information Order code ESCC part number Quality level EPPL Package Lead finish Marking Packing STRH8N10S1 - Eng. model - STRH8N10S1 SMD.5 Gold STRH8N10SG 5205/023/01 ESCC flight Target F Strip pack For specific marking only the complete structure is: ST Logo ESA Logo Date code (date of sealing of the package) : YYWWA YY: year WW: week number A: week index ESCC part number (as mentioned in the table) Warning signs (e.g. BeO) Country of origin: FR (France) Serial number of the part within the assembly lot Contact ST sales office for information about the specific conditions for products in die form and for other packages. 7.1 Other information Date code The date code for ESCC flight is structured as follows: yywwz where: yy: last two digits of year ww: week digits z: lot index in the week Documentation The table below provide a summary of the documentation provided with each type of products. DocID Rev 8 15/18 18

16 Order code STRH8N10 Table 15. Documentation provided for each type of product Quality level Radiation level Documentation Engineering model - - ESCC flight 50 krad Certificate of conformance Radiation verification test report 16/18 DocID Rev 8

17 Revision history 8 Revision history Table 16. Document revision history Date Revision Changes 20-May First release. 09-Nov Jun Dec Apr Updated dynamic values on Table 6: Dynamic, Table 7: Switching times. Added new package and mechanical data: SMD.5 Removed TO-39 package. Updated Description Minor text changes 26-May Updated Figure Mar Document status promoted from preliminary data to production data Modified: Figure 2. Minor text changes. Updated: Features, Table 5, Table 6, Table 9, Table 10, Table 11 and Table 15. Updated Section 6: Package information. Minor text changes. 10-Feb Updated Table 6: Dynamic and Table 8: Source drain diode. DocID Rev 8 17/18 18

18 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 18/18 DocID Rev 8

Features. Description. Table 1. Device summary. Gold TO-257AA

Features. Description. Table 1. Device summary. Gold TO-257AA Rad-Hard 100 V, 12 A P-channel Power MOSFET Features Datasheet - production data V DSS I D R DS(on) Q g 100V 12 A 265 mω 40 nc TO-257AA 1 2 3 Fast switching 100% avalanche tested Hermetic package 100 krad