STD16N50M2, STF16N50M2, STP16N50M2

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1 Datasheet N-channel 500 V, 0.24 Ω typ., 13 A MDmesh M2 Power MOSFETs in DPAK, TO-220FP and TO-220 packages TAB DPAK Features Order code V DS at T J max. R DS(on) max. I D Packages TAB STD16N50M2 DPAK TO TO-220FP STF16N50M2 STP16N50M2 550 V 0.28 Ω 13 A TO-220FP TO-220 G(1) D(2, TAB) Extremely low gate charge Excellent output capacitance (C OSS ) profile 100% avalanche tested Zener-protected Applications S(3) AM01475V1 Switching applications Product status link STD16N50M2 STF16N50M2 STP16N50M2 Description These devices are N-channel Power MOSFETs developed using the MDmesh M2 technology. Thanks to their strip layout and improved vertical structure, these devices exhibit low on-resistance and optimized switching characteristics, rendering them suitable for the most demanding high-efficiency converters. DS Rev 6 - December 2018 For further information contact your local STMicroelectronics sales office.

2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value DPAK TO-220 TO-220FP Unit V GS Gate-source voltage ±25 V I D Drain current (continuous) at T C = 25 C 13 A I D Drain current (continuous) at T C = 100 C 8 A I (1) DM Drain current (pulsed) 52 A P TOT Total power dissipation at T C = 25 C W dv/dt (2) Peak diode recovery voltage slope 15 V/ns dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns V ISO T stg T j Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s, T C = 25 C) Storage temperature range Operating junction temperature range 2500 V -55 to 150 C 1. Pulse width is limited by safe operating area. 2. I SD 13 A, di/dt 400 A/µs, V DS peak < V (BR)DSS, V DD = 80% V (BR)DSS 3. V DS 400 V Table 2. Thermal data Symbol Parameter Value DPAK TO-220 TO-220FP Unit R thj-case Thermal resistance junction-case R thj-amb Thermal resistance junction-ambient 62.5 C/W R thj-pcb (1) Thermal resistance junction-pcb When mounted on 1 inch² FR-4, 2 Oz copper board. Table 3. Avalanche characteristics Symbol Parameter Value Unit I AR Avalanche current, repetitive or non-repetitive (pulse width limited by T jmax ) 4 A E AS Single pulse avalanche energy (starting T j = 25 C, I D = I AR, V DD = 50 V) 215 mj DS Rev 6 page 2/24

3 Electrical characteristics 2 Electrical characteristics (T C = 25 C unless otherwise specified). Table 4. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage drain current V GS = 0 V, I D = 1 ma 500 V V GS = 0 V, V DS = 500 V 1 µa V GS = 0 V, V DS = 500 V, T C = 125 C 100 µa I GSS Gate-body leakage current V DS = 0 V, V GS (1) = ±25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V R DS(on) Static drain-source onresistance V GS = 10 V, I D = 6.5 A Ω 1. Defined by design, not subject to production test Table 5. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 100 V, f = 1 MHz, V GS = 0 V pf C rss Reverse transfer capacitance pf C oss eq. (1) Equivalent output capacitance V DS = 0 V to 400 V, V GS = 0 V pf R G Intrinsic gate resistance f = 1 MHz, I D = 0 A Ω Q g Total gate charge V DD = 400 V, I D = 13 A, nc Q gs Gate-source charge V GS = 0 to 10 V (see Figure 18. Test circuit for gate nc Q gd Gate-drain charge charge behavior) nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as Coss when VDS increases from 0 to 80% VDSS. Table 6. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 250 V, I D = 6.5 A ns t r Rise time R G = 4.7 Ω, V GS = 10 V (see Figure 17. Test circuit for ns t d(off) Turn-off-delay time resistive load switching times and Figure 22. Switching time ns t f Fall time waveform) ns DS Rev 6 page 3/24

4 Electrical characteristics Table 7. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 13 A I (1) SDM Source-drain current (pulsed) - 52 A V (2) SD Forward on voltage V GS = 0 V, I SD = 13 A V t rr Reverse recovery time I SD = 13 A, di/dt = 100 A/µs, ns Q rr Reverse recovery charge V DD = 60 V (see Figure 19. Test circuit for µc I RRM Reverse recovery current inductive load switching and diode recovery times ) A t rr Reverse recovery time I SD = 13 A, di/dt = 100 A/µs, ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C (see Figure 19. Test circuit for µc I RRM Reverse recovery current inductive load switching and diode recovery times ) - 21 A 1. Pulse width is limited by safe operating area. 2. Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DS Rev 6 page 4/24

5 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area for DPAK Figure 2. Thermal impedance for DPAK ID (A) GIPG LM K GC µs 10 1 Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse 100 µs 1 ms 10 ms VDS(V) t p (s) Figure 3. Safe operating area for TO-220FP Figure 4. Thermal impedance for TO-220FP ID (A) GIPG LM K GC Operation in this area is limited by max RDS(on) 10 µs 100 µs 1 ms ms 10-2 TJ=150 C Tc=25 C Single pulse VDS(V) t p (s) DS Rev 6 page 5/24

6 Electrical characteristics (curves) Figure 5. Safe operating area for TO-220 ID (A) GIPG LM Figure 6. Thermal impedance for TO Operation in this area is Limited by max RDS(on) 10µs 100µs 1ms Tj=150 C Tc=25 C Single pulse VDS(V) 10ms Figure 7. Output characteristics Figure 8. Transfer characteristics ID (A) VGS=7,8, 9, 10V GIPG LM 6V ID (A) VDS=17.5 V GIPG LM V V VDS(V) VGS(V) Figure 9. Gate charge vs. gate-source voltage VGS (V) VDS VDD=400 V ID=13 A GIPG LM VDS (V) Qg(nC) 50 C (pf) Figure 10. Capacitance variations GIPG LM Ciss Coss 1 Crss VDS(V) DS Rev 6 page 6/24

7 Electrical characteristics (curves) Figure 11. Normalized gate threshold voltage vs. temperature VGS(th) (norm) ID=250 µa GIPG LM TJ( C) Figure 12. Normalized V (BR)DSS vs. temperature GIPG LM V(BR)DSS (norm) 1.08 ID=1 ma TJ( C) Figure 13. Static drain-source on-resistance Figure 14. Normalized on-resistance vs. temperature RDS(on) (Ω) VGS=10V GIPG LM RDS(on) (norm) 2.2 VGS=10V GIPG LM ID(A) TJ( C) Figure 15. Output capacitance stored energy Figure 16. Source- drain diode forward characteristics Eoss (µj) 4 GIPG LM VSD (V) TJ=-50 C GIPG LM TJ=25 C TJ=150 C VDS(V) ISD(A) DS Rev 6 page 7/24

8 Test circuits 3 Test circuits Figure 17. Test circuit for resistive load switching times Figure 18. Test circuit for gate charge behavior VDD VD RL μf 3.3 μf VDD VGS 12 V IG= CONST 47 kω 100 Ω 100 nf D.U.T. 1 kω VGS pulse width RG D.U.T. pulse width 2200 μf kω 47 kω VG 1 kω AM01468v1 AM01469v1 Figure 19. Test circuit for inductive load switching and diode recovery times Figure 20. Unclamped inductive load test circuit G 25 Ω A D D.U.T. S B A fast diode B A B G 100 µh D µf + µf VDD D.U.T. VD ID L µf 3.3 µf VDD + _ RG S Vi pulse width D.U.T. AM01471v1 AM01470v1 Figure 21. Unclamped inductive waveform Figure 22. Switching time waveform V(BR)DSS t on t off VD t d(on) t r t d(off) t f 90% 90% IDM ID 0 10% V DS 10% VDD VDD V GS 90% AM01472v1 0 10% AM01473v1 DS Rev 6 page 8/24

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DS Rev 6 page 9/24

10 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 23. DPAK (TO-252) type A2 package outline _type-A2_rev25 DS Rev 6 page 10/24

11 DPAK (TO-252) type A2 package information Table 8. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e e H L L L L R 0.20 V2 0 8 DS Rev 6 page 11/24

12 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 24. DPAK (TO-252) type C2 package outline _C2_25 DS Rev 6 page 12/24

13 DPAK (TO-252) type C2 package information Table 9. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e H L L REF L L BSC L L BSC θ θ V2 0 8 DS Rev 6 page 13/24

14 DPAK (TO-252) type C2 package information Figure 25. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_ _25 DS Rev 6 page 14/24

15 DPAK (TO-252) packing information 4.3 DPAK (TO-252) packing information Figure 26. DPAK (TO-252) tape outline 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 DS Rev 6 page 15/24

16 DPAK (TO-252) packing information Figure 27. DPAK (TO-252) reel outline 40mm min. access hole at slot location T B D C A N Full radius Tape slot in core for tape start 2.5mm min.width G measured at hub AM06038v1 Table 10. DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W DS Rev 6 page 16/24

17 TO-220FP package information 4.4 TO-220FP package information Figure 28. TO-220FP package outline _Rev_12_B DS Rev 6 page 17/24

18 TO-220FP package information Table 11. TO-220FP package mechanical data Dim. mm Min. Typ. Max. A B D E F F F G G H L2 16 L L L L L Dia DS Rev 6 page 18/24

19 TO-220 type A package information 4.5 TO-220 type A package information Figure 29. TO-220 type A package outline _typeA_Rev_22 DS Rev 6 page 19/24

20 TO-220 type A package information Table 12. TO-220 type A package mechanical data Dim. mm Min. Typ. Max. A b b c D D E e e F H J L L L L øp Q DS Rev 6 page 20/24

21 Ordering information 5 Ordering information Table 13. Ordering information Order code Marking Package Packing STD16N50M2 DPAK Tape and reel STF16N50M2 STP16N50M2 16N50M2 TO-220FP TO-220 Tube DS Rev 6 page 21/24

22 Revision history Table 14. Document revision history Date Revision Changes 04-Jul Initial release. 18-Jul Updated Figure Jul Updated Figure 2 and Figure Aug May Dec Datasheet promoted from preliminary data to production data Changed: Section 4.1: "DPAK (TO-252) type A2 package information" Minor text changes Updated marking in Table 1: "Device summary". Updated Figure 3: "Thermal impedance for DPAK". Minor text changes Updated Features, Table 1. Absolute maximum ratings, Table 4. On /off states, Table 5. Dynamic. Added Section 4.2 DPAK (TO-252) type C2 package information and Section 5 Ordering information. DS Rev 6 page 22/24

23 Contents Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information DPAK (TO-252) type A2 package information DPAK (TO-252) type C2 package information DPAK (TO-252) packing information TO-220FP package information TO-220 type A package information Ordering information...21 Revision history...22 Contents...23 DS Rev 6 page 23/24

24 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DS Rev 6 page 24/24

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