N-channel 600 V, Ω typ., 13 A MDmesh II Plus low Q g Power MOSFET in a TO-220FP package. Features. Description. AM15572v1
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1 STF18N6M2 N-channel 6 V,.255 Ω typ., 13 A MDmesh II Plus low Q g Power MOSFET in a TO-22FP package Features Datasheet production data Order code V T Jmax R DS(on) max I D STF18N6M2 65 V.28 Ω 13 A TO-22FP Figure 1. Internal schematic diagram Extremely low gate charge Lower R DS(on) x area vs previous generation Low gate input resistance 1% avalanche tested Zener-protected Applications Switching applications LLC converters, resonant converters Description This device is an N-channel Power MOSFET developed using a new generation of MDmesh technology: MDmesh II Plus low Q g. This revolutionary Power MOSFET associates a vertical structure to the company's strip layout to yield one of the world's lowest on-resistance and gate charge. It is therefore suitable for the most demanding high efficiency converters. AM15572v1 Table 1. Device summary Order code Marking Package Packaging STF18N6M2 18N6M2 TO-22FP Tube February 214 DocID24729 Rev 3 1/13 This is information on a product in full production. 13
2 Contents STF18N6M2 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package mechanical data Revision history /13 DocID24729 Rev 3
3 STF18N6M2 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 25 V I D Drain current (continuous) at T C = 25 C 13 (1) A I D Drain current (continuous) at T C = 1 C 8 (1) A I (2) DM Drain current (pulsed) 52 (1) A P TOT Total dissipation at T C = 25 C 25 W dv/dt (3) Peak diode recovery voltage slope 15 V/ns dv/dt (4) MOSFET dv/dt ruggedness 5 V/ns V ISO Insulation withstand voltage (RMS) from all three leads to external heat sink (t = 1 s,t C = 25 C) T stg Storage temperature T j Max. operating junction temperature 1. Limited by maximum junction temperature 2. Pulse width limited by safe operating area 3. I SD 13 A, di/dt 4 A/μs; V DS peak < V (BR)DSS, V DD =4 V. 4. V DS 48 V 25 V - 55 to 15 C Table 3. Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 5 C/W R thj-amb Thermal resistance junction-ambient max 62.5 C/W Table 4. Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetetive or not repetetive (pulse width limited by T jmax ) Single pulse avalanche energy (starting T j =25 C, I D = I AR ; V DD =5) 3 A 135 mj DocID24729 Rev 3 3/13
4 Electrical characteristics STF18N6M2 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 5. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage drain current (V GS = ) I D = 1 ma, V GS = 6 V V DS = 6 V 1 μa V DS = 6 V, T C =125 C 1 μa I GSS Gate-body leakage current (V DS = ) V GS = ± 25 V ±1 μa V GS(th) Gate threshold voltage V DS = V GS, I D = 25 μa V R DS(on) Static drain-source on-resistance V GS = 1 V, I D = 6.5 A Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 1 V, f = 1 MHz, pf C rss V GS = Reverse transfer capacitance pf C (1) Equivalent output oss eq. capacitance V DS = to 48 V, V GS = pf R G Intrinsic gate resistance f = 1 MHz, I D = Ω Q g Total gate charge V DD = 48 V, I D = 13 A, nc Q gs Gate-source charge V GS = 1 V nc Q gd Gate-drain charge (see Figure 15) nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from to 8% V DSS Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time ns t V DD = 3 V, I D = 6.5 A, r Rise time ns R G = 4.7 Ω, V GS = 1 V t d(off) Turn-off delay time ns (see Figure 14 and Figure 19) t f Fall time ns 4/13 DocID24729 Rev 3
5 STF18N6M2 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 13 A I (1) SDM Source-drain current (pulsed) - 52 A V (2) SD Forward on voltage I SD = 13 A, V GS = V t rr Reverse recovery time - 35 ns Q rr Reverse recovery charge I SD = 13 A, di/dt = 1 A/μs V DD = 6 V (see Figure 16) μc I RRM Reverse recovery current - 22 A t rr Reverse recovery time I SD = 13 A, di/dt = 1 A/μs ns Q rr Reverse recovery charge V DD = 6 V, T j = 15 C μc I RRM Reverse recovery current (see Figure 16) - 22 A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 3 μs, duty cycle 1.5% DocID24729 Rev 3 5/13
6 Electrical characteristics STF18N6M2 2.1 Electrical characteristics (curves) Figure 2. Safe operating area Figure 3. Thermal impedance ID (A) AM15834v1 1 1 Operation in this area is Limited by max RDS(on) 1µs 1µs.1 Tj=15 C Tc=25 C Single pulse VDS(V) 1ms 1ms Figure 4. Output characteristics Figure 5. Transfer characteristics ID (A) 3 VGS=7, 8, 9, 1V AM15837v1 ID (A) 3 VDS=18V AM15838v V V 5 4V VDS(V) Figure 6. Gate charge vs gate-source voltage VGS (V) 12 VDS VDD=48V ID=13A AM15839v1 VDS (V) VGS(V) Figure 7. Static drain-source on-resistance RDS(on) (Ω) VGS=1V.27 AM1584v Qg(nC) ID(A) 6/13 DocID24729 Rev 3
7 STF18N6M2 Electrical characteristics Figure 8. Capacitance variations Figure 9. Normalized gate threshold voltage vs. temperature C (pf) AM15841v1 VGS(th) (norm) ID=25 µa AM15828v1 1 Ciss Coss Crss VDS(V) TJ( C) Figure 1. Normalized on-resistance vs temperature RDS(on) (norm) ID=6.5 A VGS=1V AM15829v TJ( C) Figure 12. Normalized V (BR)DSS vs temperature Figure 11. Source-drain diode forward characteristics VSD (V) TJ=15 C TJ=-5 C TJ=25 C AM15842v ISD(A) Figure 13. Output capacitance stored energy V(BR)DSS (norm) ID=1mA AM15831v1 Eoss(µJ) 6 AM15843v TJ( C) VDS(V) DocID24729 Rev 3 7/13
8 Test circuits STF18N6M2 3 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD VGS VD RG RL D.U.T. 22 μf 3.3 μf VDD Vi=2V=VGMAX 22 μf 12V IG=CONST 2.7kΩ 47kΩ 1Ω 1nF D.U.T. 1kΩ VG PW 47kΩ PW 1kΩ AM1468v1 AM1469v1 Figure 16. Test circuit for inductive load switching and diode recovery times Figure 17. Unclamped inductive load test circuit G 25 Ω D S A D.U.T. B A FAST DIODE B A B D L=1μH μf μf VDD VD ID L 22 μf 3.3 μf VDD G RG S Vi D.U.T. AM147v1 Pw AM1471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform V(BR)DSS ton toff VD tdon tr tdoff tf ID IDM 9% 1% VDS 1% 9% VDD VDD VGS 9% AM1472v1 1% AM1473v1 8/13 DocID24729 Rev 3
9 STF18N6M2 Package mechanical data 4 Package mechanical data In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DocID24729 Rev 3 9/13
10 Package mechanical data STF18N6M2 Figure 2. TO-22FP drawing 71251_Rev_K_B 1/13 DocID24729 Rev 3
11 STF18N6M2 Package mechanical data Table 9. TO-22FP mechanical data Dim. mm Min. Typ. Max. A B D E.45.7 F.75 1 F F G G H L2 16 L L L L L Dia DocID24729 Rev 3 11/13
12 Revision history STF18N6M2 5 Revision history Table 1. Document revision history Date Revision Changes 4-Jun First release. 5-Jun Feb Added: note 2 in Table 2 Modified: typical value for C iss, C oss eq., Q g, Q gs, Q gd Modified: Figure 1 and 11 Minor text changes Modified: note 1 in Table 2 R thj-case value in Table 3 Minor text changes 12/13 DocID24729 Rev 3
13 STF18N6M2 Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST s terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. ST PRODUCTS ARE NOT DESIGNED OR AUTHORIZED FOR USE IN: (A) SAFETY CRITICAL APPLICATIONS SUCH AS LIFE SUPPORTING, ACTIVE IMPLANTED DEVICES OR SYSTEMS WITH PRODUCT FUNCTIONAL SAFETY REQUIREMENTS; (B) AERONAUTIC APPLICATIONS; (C) AUTOMOTIVE APPLICATIONS OR ENVIRONMENTS, AND/OR (D) AEROSPACE APPLICATIONS OR ENVIRONMENTS. WHERE ST PRODUCTS ARE NOT DESIGNED FOR SUCH USE, THE PURCHASER SHALL USE PRODUCTS AT PURCHASER S SOLE RISK, EVEN IF ST HAS BEEN INFORMED IN WRITING OF SUCH USAGE, UNLESS A PRODUCT IS EXPRESSLY DESIGNATED BY ST AS BEING INTENDED FOR AUTOMOTIVE, AUTOMOTIVE SAFETY OR MEDICAL INDUSTRY DOMAINS ACCORDING TO ST PRODUCT DESIGN SPECIFICATIONS. PRODUCTS FORMALLY ESCC, QML OR JAN QUALIFIED ARE DEEMED SUITABLE FOR USE IN AEROSPACE BY THE CORRESPONDING GOVERNMENTAL AGENCY. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. 214 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco - Philippines - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America DocID24729 Rev 3 13/13
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STD3NF4LT N-channel 4 V,.3 Ω typ., 3 A, STripFET II Power MOSFET in a DPAK package Features Datasheet production data Order code V DSS R DS(on) max I D STD3NF4LT 4 V
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STB80NF10 STP80NF10 N-channel 100 V, 0.012 Ω, 80 A, TO-220, D 2 PAK low gate charge STripFET II Power MOSFET Features Type V DSS R DS(on) max I D STP80NF10 100 V < 0.015 Ω 80 A STB80NF10 100 V < 0.015
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N-channel 600 V, 0.76 Ω typ., 4.8 A MDmesh II Plus low Q g Power MOSFET in a PowerFLAT 5x6 HV package Features Datasheet - production data Order code V DS @ T Jmax R DS(on) max I D 650 V 0.86 Ω 4.8 A 1
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2N7000 2N7002 N-channel 60 V, 1.8 Ω, 0.35 A, SOT23-3L, TO-92 STripFET Power MOSFET Features Type V DSS R DS(on) max I D 2N7000 60 V < 5 Ω(@10V) 0.35 A 2N7002 60 V < 5 Ω(@10V) 0.20 A Low Q g Low threshold
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