Features. Description. AM15572v1. Table 1. Device summary. Order code Marking Package Packaging. STD7N65M2 7N65M2 DPAK Tape and reel

Transcription

1 N-channel 650 V, 0.98 Ω typ., 5 A MDmesh M2 Power MOSFET in a DPAK package Features Datasheet - production data TAB Order code V DS R DS(on) max STD7N65M2 650 V 1.15 Ω 5 A I D DPAK 1 3 Extremely low gate charge Excellent output capacitance (C oss ) profile 100% avalanche tested Zener-protected Applications Figure 1. Internal schematic diagram G(1) D(2, TAB) Switching applications Description This device is an N-channel Power MOSFET developed using the MDmesh M2 technology. Thanks to the strip layout associated to an improved vertical structure, the device exhibits both low on-resistance and optimized switching characteristics. It is therefore suitable for the most demanding high efficiency converters. S(3) AM15572v1 Table 1. Device summary Order code Marking Package Packaging STD7N65M2 7N65M2 DPAK Tape and reel May 2015 DocID Rev 2 1/17 This is information on a product in full production.

2 Contents STD7N65M2 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information DPAK (TO-252) type A package information DPAK (TO-252) type C package information Packaging mechanical data Revision history /17 DocID Rev 2

3 Electrical ratings 1 Electrical ratings Table 2. Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 25 V I D Drain current (continuous) at T C = 25 C 5 A I D Drain current (continuous) at T C = 100 C 3.2 A I (1) DM Drain current (pulsed) 20 A P TOT Total dissipation at T C = 25 C 60 W dv/dt (2) Peak diode recovery voltage slope 15 dv/dt (3) MOSFET dv/dt ruggedness 50 V/ns T stg Storage temperature T j Operating junction temperature - 55 to 150 C 1. Pulse width limited by safe operating area 2. I SD 5 A, di/dt 400 A/µs; V DS peak < V (BR)DSS, V DD =400 V 3. V DS 520 V Table 3. Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case max 2.08 C/W R thj-pcb Thermal resistance junction-pcb max 50 (1) C/W 1. When mounted on 1 inch² FR-4, 2 Oz copper board. Table 4. Avalanche characteristics Symbol Parameter Value Unit I AR Avalanche current, repetitive or not repetitive (pulse width limited by T jmax ) E AS Single pulse avalanche energy (starting T j =25 C, I D = I AR ; V DD =50 V) 1 A 103 mj DocID Rev 2 3/17 17

4 Electrical characteristics STD7N65M2 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 5. On /off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage drain current V GS = 0, I D = 1 ma 650 V V GS = 0, V DS = 650 V 1 µa V GS = 0, V DS = 650 V, T C =125 C 100 µa Gate-body leakage I GSS V current DS = 0, V GS = ± 25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V Static drain-source R DS(on) V on-resistance GS = 10 V, I D = 2.5 A Ω Table 6. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 100 V, f = 1 MHz, pf C rss V GS = 0 Reverse transfer capacitance pf C (1) Equivalent output oss eq. capacitance V DS = 0 to 520 V, V GS = pf R G Intrinsic gate resistance f = 1 MHz open drain Ω Q g Total gate charge V DD = 520 V, I D = 5 A, nc Q gs Gate-source charge V GS = 10 V nc Q gd Gate-drain charge (see Figure 15) nc 1. C oss eq. is defined as a constant equivalent capacitance giving the same charging time as C oss when V DS increases from 0 to 80% V DSS Table 7. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time ns V DD = 325 V, I D = 2.5 A, t r Rise time ns R G = 4.7 Ω, V GS = 10 V t d(off) Turn-off delay time ns (see Figure 14 and 19) t f Fall time ns 4/17 DocID Rev 2

5 Electrical characteristics Table 8. Source drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 5 A I (1) SDM Source-drain current (pulsed) - 20 A V (2) SD Forward on voltage I SD = 5 A, V GS = V t rr Reverse recovery time ns Q rr Reverse recovery charge I SD = 5 A, di/dt = 100 A/µs V DD = 60 V (see Figure 19) µc I RRM Reverse recovery current A t rr Reverse recovery time I SD = 5 A, di/dt = 100 A/µs ns Q rr Reverse recovery charge V DD = 60 V, T j = 150 C µc I RRM Reverse recovery current (see Figure 19) A 1. Pulse width limited by safe operating area. 2. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DocID Rev 2 5/17 17

6 Electrical characteristics STD7N65M2 2.1 Electrical characteristics (curves) ID (A) Figure 2. Safe operating area GIPG FSR Figure 3. Thermal impedance Operation in this area is Limited by max RDS(on) Tj=150 C Tc=25 C Single pulse VDS(V) 10μs 100μs 1ms 10ms Figure 4. Output characteristics Figure 5. Transfer characteristics ID (A) VGS=7, 8, 9, 10V GIPG FSR ID (A) VDS=20V GIPG FSR V 6 4 5V 4 2 4V VDS(V) Figure 6. Gate charge vs gate-source voltage VGS GIPG FSR VDS (V) (V) VDS VDD=520V 12 ID=5A VGS(V) Figure 7. Static drain-source on-resistance RDS(on) (Ω) 1.04 VGS=10V GIPG FSR Qg(nC) ID(A) 6/17 DocID Rev 2

7 Electrical characteristics Figure 8. Capacitance variations Figure 9. Output capacitance stored energy C (pf) GIPG FSR Eoss (μj) GIPG FSR Ciss Coss Crss VDS(V) Figure 10. Normalized gate threshold voltage vs temperature VDS(V) Figure 11. Normalized on-resistance vs temperature VGS(th) (norm) 1.1 ID=250μA AM18065v1 RDS(on) (norm) 2.2 ID=2.5A VGS=10V AM18066v TJ( C) Figure 12. Source-drain diode forward characteristics TJ( C) Figure 13. Normalized V (BR)DSS vs temperature VSD (V) 1.1 GIPG FSR TJ=-50 C V(BR)DSS (norm) 1.08 ID=1mA AM18067v TJ=25 C TJ=150 C ISD(A) TJ( C) DocID Rev 2 7/17 17

8 Test circuits STD7N65M2 3 Test circuits Figure 14. Switching times test circuit for resistive load Figure 15. Gate charge test circuit VDD VGS VD RG RL D.U.T μf 3.3 μf VDD Vi=20V=VGMAX 2200 μf 12V IG=CONST 2.7kΩ 47kΩ 100Ω 100nF D.U.T. 1kΩ VG PW 47kΩ PW 1kΩ AM01468v1 AM01469v1 Figure 16. Test circuit for inductive load switching and diode recovery times Figure 17. Unclamped inductive load test circuit G 25 Ω D S A D.U.T. B A FAST DIODE B A B D L=100μH μf μf VDD VD ID L 2200 μf 3.3 μf VDD G RG S Vi D.U.T. AM01470v1 Pw AM01471v1 Figure 18. Unclamped inductive waveform Figure 19. Switching time waveform ton toff tdon tr tdoff tf 0 90% 10% VDS 10% 90% VGS 90% 0 10% AM01473v1 8/17 DocID Rev 2

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 4.1 DPAK (TO-252) type A package information Figure 20. DPAK (TO-252) type A package outline DocID Rev 2 9/17 17

10 Package information STD7N65M2 Table 9. DPAK (TO-252) type A package mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e e H L (L1) L L R 0.20 V /17 DocID Rev 2

11 Package information 4.2 DPAK (TO-252) type C package information Figure 21. DPAK (TO-252) type C package outline DocID Rev 2 11/17 17

12 Package information STD7N65M2 Table 10. DPAK (TO-252) type C package mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E e E H L L REF L L BSC L L BSC Θ Θ V /17 DocID Rev 2

13 Package information Figure 22. DPAK footprint (a) a. All dimensions are in millimeters DocID Rev 2 13/17 17

14 Packaging mechanical data STD7N65M2 5 Packaging mechanical data Figure 23. Tape for DPAK (TO-252) 10 pitches cumulative tolerance on tape +/- 0.2 mm T Top cover tape P0 D P2 E B1 K0 B0 F W For machine ref. only including draft and radii concentric around B0 A0 P1 D1 User direction of feed R User direction of feed Bending radius AM08852v1 14/17 DocID Rev 2

15 Packaging mechanical data REEL DIMENSIONS Figure 24. Reel for DPAK (TO-252) T 40mm min. Access hole At slot location B D C A N Full radius Tape slot in core for tape start 25 mm min. width G measured at hub AM08851v2 Table 11. DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W DocID Rev 2 15/17 17

16 Revision history STD7N65M2 6 Revision history Table 12. Document revision history Date Revision Changes 07-Aug First release. 06-May Document status promoted from preliminary to production data. Updated Section 4: Package information. 16/17 DocID Rev 2

17 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DocID Rev 2 17/17 17