Features. Description. Table 1: Device summary Order code Marking Package Packing STL90N10F7 90N10F7 PowerFLAT 5x6 Tape and reel

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1 N-channel 100 V, Ω typ., 70 A STripFET F7 Power MOSFET in a PowerFLAT 5x6 package Datasheet - production data Features Order code V DS R DS(on) max. I D P TOT 100 V Ω 70 A 100 W PowerFLAT 5x6 Among the lowest R DS(on) on the market Excellent figure of merit (FoM) Low C rss /C iss ratio for EMI immunity High avalanche ruggedness Figure 1: Internal schematic diagram Applications Switching applications Description This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low onstate resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Table 1: Device summary Order code Marking Package Packing 90N10F7 PowerFLAT 5x6 Tape and reel March 2015 DocID Rev 4 1/14 This is information on a product in full production.

2 Contents Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information PowerFLAT 5x6 type R package information PowerFLAT 5x6 packing information Revision history /14 DocID Rev 4

3 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit V DS Drain-source voltage 100 V V GS Gate-source voltage ± 20 V I D (1) I D (1) I D (2) I D (2) I DM (1)(3) I DM (2)(3) P TOT (1) P TOT (2) E AS (4) Drain current (continuous) at T C = 25 C 70 A Drain current (continuous) at T C= 100 C 50 A Drain current (continuous) at T pcb = 25 C 16 A Drain current (continuous) at T pcb= 100 C 11 A Drain current (pulsed) 280 A Drain current (pulsed) 64 A Total dissipation at T C = 25 C 100 W Total dissipation at T pcb = 25 C 5 W Single pulse avalanche energy 300 mj T stg Storage temperature - 55 to 175 C T j Maximum junction temperature 175 C Notes: (1) This value is rated according to Rthj-c. (2) This value is rated according to Rthj-pcb. (3) Pulse width is limited by safe operating area. (4) Starting Tj = 25 C, I D = 10 A, V DD = 50 V. Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case 1.5 R thj-pcb (1) Thermal resistance junction-pcb 31 Notes: (1) When mounted on 1 inch², 2 Oz. Cu FR-4 board C/W DocID Rev 4 3/14

4 Electrical characteristics 2 Electrical characteristics (T C = 25 C unless otherwise specified) Table 4: Static Symbol Parameter Test conditions Min. Typ. Max. Unit Drain-source breakdown voltage V GS = 0 V, I D = 250 µa 100 V I DSS V GS = 0 V, V DS = 100 V 1 µa Zero gate voltage drain current V GS = 0 V, V DS = 100 V, 100 µa T c = 125 C I GSS Gate-body leakage current V DS = 0 V, V GS = 20 V 100 na V GS(th) Gate threshold voltage V DS = V GS, I D = 250 µa V V (BR)DSS R DS(on) Static drain-source onresistance V GS = 10 V, I D = 8 A Ω Table 5: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS= 50 V, f = 1 MHz, pf C rss V GS = 0 V Reverse transfer capacitance pf Q g Total gate charge V DD = 50 V, I D = 16 A, nc Q gs Gate-source charge V GS = 10 V (see Figure 14: - 18 nc Q gd Gate-drain charge "Gate charge test circuit") - 13 nc Table 6: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 50 V, I D = 8 A ns t r Rise time R G = 4.7 Ω, V GS = 10 V (see Figure 13: "Switching times ns t d(off) Turn-off-delay time test circuit for resistive load" ns t f Fall time and Figure 18: "Switching time waveform") ns 4/14 DocID Rev 4

5 Table 7: Source-drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 16 A I SDM (1) V SD (2) Source-drain current (pulsed) - 64 A Forward on voltage V GS = 0 V, I SD = 16 A V t rr Reverse recovery time I SD = 16 A, di/dt = 100 A/µs, ns Q rr Reverse recovery charge V DD = 80 V, T j = 150 C (see Figure 15: "Test circuit for nc I RRM Reverse recovery current inductive load switching and diode recovery times") A Notes: (1) Pulse width is limited by safe operating area. (2) Pulse test: pulse duration = 300 µs, duty cycle 1.5%. DocID Rev 4 5/14

6 Electrical characteristics 2.1 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/14 DocID Rev 4

7 Figure 8: Capacitance variations Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized on-resistance vs temperature Figure 11: Normalized V(BR)DSS vs temperature Figure 12: Source-drain diode forward characteristics DocID Rev 4 7/14

8 Test circuits 3 Test circuits Figure 13: Switching times test circuit for resistive load Figure 14: Gate charge test circuit VDD 12 V 47 k Ω 1 kω 100 nf Vi V GS I G = CONST 100 Ω D.U.T μ F 2.7 k Ω VG 47 k Ω PW 1 kω AM01469v1 Figure 15: Test circuit for inductive load switching and diode recovery times Figure 16: Unclamped inductive load test circuit G A D D.U.T. A FAST DIODE A L=100 µh 25Ω S B B B D µf µf VDD G D.U.T. RG S AM01470v1 Figure 17: Unclamped inductive waveform V (B R)DS S Figure 18: Switching time waveform t on toff t d(on) t r t d(off) t f V D 90% 90% I DM 10% I D 0 10% V DS V DD V DD V GS 90% AM01472v1 0 10% AM01473v1 8/14 DocID Rev 4

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. 4.1 PowerFLAT 5x6 type R package information Figure 19: PowerFLAT 5x6 type R package outline DocID Rev 4 9/14

10 Package information Table 8: PowerFLAT 5x6 type R mechanical data mm Dim. Min. Typ. Max. A A A b D E D e 1.27 L K E E E Figure 20: PowerFLAT 5x6 recommended footprint (dimensions are in mm) 10/14 DocID Rev 4

11 REF.R0.50 Package information 4.2 PowerFLAT 5x6 packing information Figure 21: PowerFLAT 5x6 tape (dimensions are in mm) T (0.30 ±0.05) Do Ø1.55±0.05 Y P 2 2.0±0.1 (I) P 0 4.0±0.1 (II) E1 1.75±0.1 C L Bo (5.30±0.1) D1 Ø1.5 MIN. REF 0.20 F(5.50±0.1)(III) W(12.00±0.3) Y Ko (1.20±0.1) P1(8.00±0.1) Ao(6.30±0.1) SECTION Y-Y (I) Measured from centerline of sprocket hole to centerline of pocket. (II) Cumulative tolerance of 10 sprocket holes is ± (III) Measured from centerline of sprocket hole to centerline of pocket. Base and bulk quantity 3000 pcs _Tape_rev_C Figure 22: PowerFLAT 5x6 package orientation in carrier tape DocID Rev 4 11/14

12 Package information Figure 23: PowerFLAT 5x6 reel 12/14 DocID Rev 4

13 Revision history 5 Revision history Table 9: Document revision history Date Revision Changes 16-Apr First release. 06-Mar Dec Mar Modified: R DS(on) value in cover page Modified: V GS(th) values in Table 4 Modified: R DS(on) typ. and max values in Table 4 Modified: typical values in Table 5, 6 and 7 Updated: Section 4: Package mechanical data Added: Section 2.1: Electrical characteristics (curves) Updated: Section 4: Package mechanical data Document status promoted from preliminary data to production data Updated title, features and description in cover page. Updated R DS(on) values and Figure 7: Static drain-source onresistance. Text edits throughout document Updated cover page title description Updated cover page features table In table 2. Absolute maximum ratings, added "E AS" information and footnote 4 In table 3. Thermal data, added footnote 1 Renamed table 4. Static (was On/off states) Updated table 5. Dynamic Updated table 7. Source drain diode In Section 2.1 Electrical characteristics (curves), updated figures 2, 3, 10 and 11 Updated and renamed Section 4 Package information DocID Rev 4 13/14

14 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 14/14 DocID Rev 4

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