Features. Description. AM15572v1_tab. Table 1: Device summary Order code Marking Package Packing STD7LN80K5 7LN80K5 DPAK Tape and reel

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1 N-channel 800 V, 0.95 Ω typ., 5 A MDmesh K5 Power MOSFET in a DPAK package Datasheet - production data Features Order code V DS R DS(on) max. I D STD7LN80K5 800 V 1.15 Ω 5 A DPAK Figure 1: Internal schematic diagram D(2, TAB) G(1) Industry s lowest R DS(on) x area Industry s best figure of merit (FoM) Ultra-low gate charge 100% avalanche tested Zener-protected Applications Switching applications Description This very high voltage N-channel Power MOSFET is designed using MDmesh K5 technology based on an innovative proprietary vertical structure. The result is a dramatic reduction in on-resistance and ultra-low gate charge for applications requiring superior power density and high efficiency. S(3) AM15572v1_tab Table 1: Device summary Order code Marking Package Packing STD7LN80K5 7LN80K5 DPAK Tape and reel December 2015 DocID Rev 1 1/16 This is information on a product in full production.

2 Contents STD7LN80K5 Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information DPAK (TO-252) type A2 package information DPAK (TO-252) packing information Revision history /16 DocID Rev 1

3 Electrical ratings 1 Electrical ratings Table 2: Absolute maximum ratings Symbol Parameter Value Unit V GS Gate-source voltage ± 30 V I D (1) I D (1) I D (2) Drain current (continuous) at T C = 25 C 5 A Drain current (continuous) at T C = 100 C 3.4 A Drain current (pulsed) 20 A P TOT Total dissipation at T C = 25 C 85 W dv/dt (3) Peak diode recovery voltage slope 4.5 V/ns dv/dt (4) MOSFET dv/dt ruggedness 50 V/ns T stg T j Storage temperature Operating junction temperature Notes: (1) Limited by maximum junction temperature. (2) Pulse width limited by safe operating area. (3) ISD 5 A, di/dt 100 A/µs; V DS peak < V (BR)DSS, V DD=640 V (4) VDS 640 V - 55 to 150 C Table 3: Thermal data Symbol Parameter Value Unit R thj-case Thermal resistance junction-case 1.47 C/W R thj-pcb (1) Thermal resistance junction-pcb 50 C/W Notes: (1) When mounted on FR-4 board of 1 inch², 2 oz Cu Table 4: Avalanche characteristics Symbol Parameter Value Unit I AR E AS Avalanche current, repetetive or not repetetive (pulse width limited by T jmax) (Single pulse avalanche energy (starting T j = 25 C, I D = I AR; V DD = 50 V) 1.5 A 200 mj DocID Rev 1 3/16

4 Electrical characteristics STD7LN80K5 2 Electrical characteristics T C = 25 C unless otherwise specified Table 5: On/off states Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage Drain current V GS = 0 V, I D = 1 ma 800 V V GS = 0 V, V DS = 800 V 1 µa V GS = 0 V, V DS = 800 V, T C = 125 C 50 µa I GSS Gate-body leakage current V DS = 0 V, V GS = ±25 V ±10 µa V GS(th) Gate threshold voltage V DS = V GS, I D =100 µa V R DS(on) Static drain-source onresistance V GS = 10 V, I D = 2.5 A Ω Table 6: Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS= 100 V, f = 1 MHz, pf V GS = 0 V Reverse transfer C rss pf capacitance C o(er) (1) C o(tr) (2) Equivalent capacitance energy related Equivalent capacitance time related V DS = 0 to 640 V, V GS = 0 V nc nc R g Intrinsic gate resistance f = 1 MHz, I D=0 A Ω Q g Total gate charge V DD = 640 V, I D = 5 A, nc Q gs Gate-source charge V GS = 10 V (see Figure 15: "Test circuit for gate charge nc Q gd Gate-drain charge behavior") nc Notes: (1) Energy related is defined as a constant equivalent capacitance giving the same stored energy as Coss when V DS increases from 0 to 80% V DSS (2) Time related is defined as a constant equivalent capacitance giving the same stored energy as Coss when V DS increases from 0 to 80% V DSS Table 7: Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time V DD = 400 V, I D = 2.5 A, R G = 4.7 Ω, ns t V GS r Rise time = 10 V (see Figure 14: "Test ns circuit for resistive load switching t d(off) Turn-off-delay time times" and Figure 19: "Switching time ns t f Fall time waveform") ns 4/16 DocID Rev 1

5 Table 8: Source drain diode Electrical characteristics Symbol Parameter Test conditions Min. Typ. Max. Unit I SD Source-drain current - 5 A I SDM (1) V SD (2) t rr Q rr I RRM t rr Q rr I RRM Source-drain current (pulsed) - 20 A Forward on voltage I SD= 5 A, V GS = 0 V, V Reverse recovery time Reverse recovery charge Reverse recovery current Reverse recovery time Reverse recovery charge Reverse recovery current Notes: (1) Pulse width is limited by safe operating area (2) Pulsed: pulse duration = 300 µs, duty cycle 1.5% I SD = 5 A, di/dt = 100 A/µs, V DD = 60 V (see Figure 16: "Test circuit for inductive load switching and diode recovery times") I SD = 5 A, di/dt = 100 A/µs, V DD = 60 V, T j = 150 C (see Figure 16: "Test circuit for inductive load switching and diode recovery times") ns µc A ns µc A Table 9: Gate-source Zener diode Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)GSO Gate-source breakdown voltage I GS = ±1 ma, I D = 0 A 30 - V The built-in back-to-back Zener diodes are specifically designed to enhance the ESD performance of the device. The Zener voltage facilitates efficient and cost-effective device integrity protection,thus eliminating the need for additional external componentry. DocID Rev 1 5/16

6 Electrical characteristics 2.2 Electrical characteristics (curves) Figure 2: Safe operating area Figure 3: Thermal impedance STD7LN80K5 Figure 4: Output characteristics Figure 5: Transfer characteristics Figure 6: Gate charge vs gate-source voltage Figure 7: Static drain-source on-resistance 6/16 DocID Rev 1

7 Figure 8: Capacitance variations Electrical characteristics Figure 9: Normalized gate threshold voltage vs temperature Figure 10: Normalized V (BR)DSS vs temperature Figure 11: Normalized on-resistance vs temperature Figure 12: Source-drain diode forward characteristics Figure 13: Maximum avalanche energy vs starting T J DocID Rev 1 7/16

8 Test circuits STD7LN80K5 3 Test circuits Figure 14: Test circuit for resistive load switching times Figure 15: Test circuit for gate charge behavior Figure 16: Test circuit for inductive load switching and diode recovery times Figure 17: Unclamped inductive load test circuit Figure 18: Unclamped inductive waveform Figure 19: Switching time waveform 8/16 DocID Rev 1

9 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DocID Rev 1 9/16

10 Package information 4.1 DPAK (TO-252) type A2 package information Figure 20: DPAK (TO-252) type A2 package outline STD7LN80K5 10/16 DocID Rev 1

11 Dim. Package information Table 10: DPAK (TO-252) type A2 mechanical data mm Min. Typ. Max. A A A b b c c D D E E e e H L L L L R 0.20 V2 0 8 DocID Rev 1 11/16

12 Package information Figure 21: DPAK (TO-252) recommended footprint (dimensions are in mm) STD7LN80K5 12/16 DocID Rev 1

13 4.2 DPAK (TO-252) packing information Figure 22: DPAK (TO-252) tape outline Package information DocID Rev 1 13/16

14 Package information Figure 23: DPAK (TO-252) reel outline STD7LN80K5 Table 11: DPAK (TO-252) tape and reel mechanical data Tape Reel Dim. mm mm Dim. Min. Max. Min. Max. A A 330 B B 1.5 B C D D 20.2 D1 1.5 G E N 50 F T 22.4 K P Base qty P Bulk qty P R 40 T W /16 DocID Rev 1

15 Revision history 5 Revision history Table 12: Document revision history Date Revision Changes 16-Dec First release. DocID Rev 1 15/16

16 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved 16/16 DocID Rev 1

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