N-channel 60 V, 6.8 mω typ., 40 A STripFET F7 Power MOSFET in a DPAK. Order code V DS R DS(on ) max. I D

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1 Datasheet N-channel 60 V, 6.8 mω typ., 40 A STripFET F7 Power MOSFET in a DPAK package Features TAB DPAK D(2, TAB) Order code V DS R DS(on ) max. I D STD80N6F7 60 V 8.0 mω 40 A Among the lowest R DS(on) on the market Excellent FoM (figure of merit) Low C rss /C iss ratio for EMI immunity High avalanche ruggedness G(1) Applications Switching applications S(3) AM01475v1_noZen Description This N-channel Power MOSFET utilizes STripFET F7 technology with an enhanced trench gate structure that results in very low on-state resistance, while also reducing internal capacitance and gate charge for faster and more efficient switching. Product status STD80N6F7 Product summary Order code Marking Package Packing STD80N6F7 80N6F7 DPAK Tape and reel DS Rev 5 - February 2018 For further information contact your local STMicroelectronics sales office.

2 Electrical ratings 1 Electrical ratings Table 1. Absolute maximum ratings Symbol Parameter Value Unit V DS Drain-source voltage 60 V V GS Gate-source voltage ±20 V I (1) D Drain current (continuous) at T C = 25 C 40 A I (1) D Drain current (continuous) at T C = 100 C 40 A I (2) (1) DM Drain current (pulsed) 160 A P TOT Total dissipation at T C = 25 C 100 W E (3) AS Single pulse avalanche energy 60 mj dv/dt (4) Peak diode recovery 4.3 V/ns T j T stg Operating junction temperature range Storage temperature range -55 to 175 C 1. This value is limited by package 2. Pulse width limited by safe operating area 3. Starting T j =25 C, I AS =20 A, V DD =40 V. 4. I SD = 20 A, di/dt= 700A/µs, V DD =48 V. Table 2. Thermal data Symbol Parameter Value Unit R (1) thj-pcb Thermal resistance junction-pcb 50 C/W R thj-case Thermal resistance junction-case 1.5 C/W 1. When mounted on FR-4 board of 1 inch², 2oz Cu, t < 10 s DS Rev 5 page 2/14

3 Electrical characteristics 2 Electrical characteristics T C = 25 C unless otherwise specified Table 3. On/off-state Symbol Parameter Test conditions Min. Typ. Max. Unit V (BR)DSS I DSS Drain-source breakdown voltage Zero gate voltage drain current V GS = 0 V, I D = 1 ma 60 V V GS = 0 V, V DS = 60 V 1 µa I GSS Gate-body leakage current V GS = 20 V, V DS = 0 V 100 na V GS(th) Gate threshold voltage V DD = V GS, I D = 250 µa 2 4 V R DS(on) Static drain-source onresistance V GS = 10 V, I D = 20 A mω Table 4. Dynamic Symbol Parameter Test conditions Min. Typ. Max. Unit C iss Input capacitance pf C oss Output capacitance V DS = 30 V, f = 1 MHz, V GS = 0 V pf C rss Reverse transfer capacitance pf Q g Total gate charge V DD = 30 V, I D = 20 A, nc Q gs Gate-source charge V GS = 0 to 10 V nc Q gd Gate-drain charge (see Figure 13. Test circuit for gate charge behavior) nc Table 5. Switching times Symbol Parameter Test conditions Min. Typ. Max. Unit t d(on) Turn-on delay time ns t r Rise time V DD = 30 V, I D = 20 A, R G = 4.7 Ω, V GS = 10 V (see Figure 12. Test circuit for resistive load ns t d(off) Turn-off delay time switching times and Figure 17. Switching time ns waveform) t f Fall time ns Table 6. Source-drain diode Symbol Parameter Test conditions Min. Typ. Max. Unit V (1) SD Forward on voltage I SD = 40 A, V DD = 0 V V t rr Reverse recovery time I D = 40 A, di/dt = 100 A/μs,V DD = 48 V ns Q rr Reverse recovery charge (see Figure 14. Test circuit for inductive load - 36 nc I RRM Reverse recovery current switching and diode recovery times) A 1. Pulsed: pulse duration = 300 µs, duty cycle 1.5% DS Rev 5 page 3/14

4 Electrical characteristics (curves) 2.1 Electrical characteristics (curves) Figure 1. Safe operating area Figure 2. Normalized thermal impedance I D (A) Operation in this area is limited by R DS(on) GADG SOA K δ = 0.5 GADG ZTH 10 2 t p =10 µs δ = 0.2 δ = T j 175 C T c = 25 C single pulse t p =10 ms t p =100 µs t p =1 ms V DS (V) 10-1 Single pulse δ = 0.05 δ = 0.02 δ = t p (s) Figure 3. Output characteristics Figure 4. Transfer characteristics I D (A) V GS = 8, 9, 10 V V GS = 7 V GADG OCH V GS = 6 V I D (A) V DS = 6 V GADG TCH V GS = 5 V 20 V GS = 4 V V DS (V) 60 T J = 25 C 40 T J = 175 C 20 T J = -55 C V GS (V) Figure 5. Gate charge vs gate-source voltage Figure 6. Static drain-source on-resistance V GS (V) GADG QVG R DS(on) (mω) GADG RID V DS = 30 V I D = 20 A 9 8 V GS = 10 V Q g (nc) I D (A) DS Rev 5 page 4/14

5 Electrical characteristics (curves) Figure 7. Capacitance variations Figure 8. Normalized V GS(th) vs temperature C (pf) f = 1 MHz GADG CVR V GS(th) (norm.) 1.2 I D = 250 µa GADG VTH 10 3 C ISS 1 C OSS C RSS V DS (V) T j ( C) Figure 9. Normalized on-resistance vs temperature Figure 10. Normalized V (BR)DSS vs temperature R DS(on) (norm.) GADG RON V (BR)DSS (norm.) GADG BDV V GS = 10 V I D = 20 A I D = 1 ma T j ( C) T j ( C) Figure 11. Source-drain diode forward characteristics V SD (V) GADG SDF T J = -55 C T J = 25 C 0.8 T J = 175 C I SD (A) DS Rev 5 page 5/14

6 Test circuits 3 Test circuits Figure 12. Test circuit for resistive load switching times Figure 13. Test circuit for gate charge behavior V DD RL VGS VD RG RL D.U.T μf 3.3 μf VDD V GS pulse width 2200 μf + I G = CONST 2.7 kω 47 kω 100 Ω D.U.T. V G pulse width 1 kω AM01469v10 AM01468v1 Figure 14. Test circuit for inductive load switching and diode recovery times Figure 15. Unclamped inductive load test circuit G 25 Ω A D D.U.T. S B + RG A fast diode B A B G 100 µh D µf + µf VDD D.U.T. S Vi VD ID L D.U.T µf 3.3 µf VDD _ pulse width AM01471v1 AM01470v1 Figure 16. Unclamped inductive waveform Figure 17. Switching time waveform V(BR)DSS VD ton toff td(on) tr td(off) tf IDM 90% 90% VDD ID VDD 0 10% VDS 10% VGS 90% AM01472v1 0 10% AM01473v1 DS Rev 5 page 6/14

7 Package information 4 Package information In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK packages, depending on their level of environmental compliance. ECOPACK specifications, grade definitions and product status are available at: ECOPACK is an ST trademark. DS Rev 5 page 7/14

8 DPAK (TO-252) type A2 package information 4.1 DPAK (TO-252) type A2 package information Figure 18. DPAK (TO-252) type A2 package outline _type-A2_rev24 DS Rev 5 page 8/14

9 DPAK (TO-252) type A2 package information Table 7. DPAK (TO-252) type A2 mechanical data Dim. mm Min. Typ. Max. A A A b b c c D D E E e e H L L L L R 0.20 V2 0 8 DS Rev 5 page 9/14

10 DPAK (TO-252) type C2 package information 4.2 DPAK (TO-252) type C2 package information Figure 19. DPAK (TO-252) type C2 package outline _C2_24 Table 8. DPAK (TO-252) type C2 mechanical data Dim. mm Min. Typ. Max. A A A b b DS Rev 5 page 10/14

11 DPAK (TO-252) footprint information Dim. mm Min. Typ. Max. c c D D E E e H L L REF L L BSC L L BSC θ θ V DPAK (TO-252) footprint information Figure 20. DPAK (TO-252) recommended footprint (dimensions are in mm) FP_ _24 DS Rev 5 page 11/14

12 Revision history Date Revision Changes 03-Nov First release Table 9. Document revision history 03-Mar Updated Table 2: "Absolute maximum ratings" and Table 5: "Dynamic". Added Section 2.1: "Electrical characteristics (curves)". Minor text changes. 02-May Updated Table 2: "Absolute maximum ratings". 01-Feb Added DPAK (TO-252) type C package information. Removed maturity status indication from cover page. 12-Feb Modified Section 4 Package information. Minor text changes. DS Rev 5 page 12/14

13 Contents Contents 1 Electrical ratings Electrical characteristics Electrical characteristics (curves) Test circuits Package information DPAK (TO-252) type A2 package information DPAK (TO-252) type C2 package information DPAK (TO-252) footprint information Revision history...12 Contents...13 Disclaimer...14 DS Rev 5 page 13/14

14 IMPORTANT NOTICE PLEASE READ CAREFULLY STMicroelectronics NV and its subsidiaries ( ST ) reserve the right to make changes, corrections, enhancements, modifications, and improvements to ST products and/or to this document at any time without notice. Purchasers should obtain the latest relevant information on ST products before placing orders. ST products are sold pursuant to ST s terms and conditions of sale in place at the time of order acknowledgement. Purchasers are solely responsible for the choice, selection, and use of ST products and ST assumes no liability for application assistance or the design of Purchasers products. No license, express or implied, to any intellectual property right is granted by ST herein. Resale of ST products with provisions different from the information set forth herein shall void any warranty granted by ST for such product. ST and the ST logo are trademarks of ST. All other product or service names are the property of their respective owners. Information in this document supersedes and replaces information previously supplied in any prior versions of this document STMicroelectronics All rights reserved DS Rev 5 page 14/14

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